Searched refs:R14 (Results 1 - 15 of 15) sorted by relevance

/drivers/net/wan/
H A Dz85230.c911 c->regs[R14]|= DTRREQ;
912 write_zsreg(c, R14, c->regs[R14]);
1018 c->regs[R14]&= ~DTRREQ;
1019 write_zsreg(c, R14, c->regs[R14]);
1107 c->regs[R14]|= DTRREQ;
1108 write_zsreg(c, R14, c->regs[R14]);
1187 c->regs[R14]
[all...]
H A Dz85230.h39 #define R14 14 macro
/drivers/media/video/
H A Dwm8775.c50 R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R23 = 23, enumerator in enum:__anon1684
111 wm8775_write(sd, R14, vol_l | 0x100); /* 0x100= Left channel ADC zero cross enable */
283 wm8775_write(sd, R14, 0x1d4);
H A Dupd64083.c47 R10, R11, R12, R13, R14, enumerator in enum:__anon1663
/drivers/net/hamradio/
H A Dscc.c358 OutReg(scc->ctrl,R14,SEARCH|scc->wreg[R14]); /* DPLL: enter search mode */
454 OutReg(scc->ctrl,R14,SEARCH|scc->wreg[R14]); /* DPLL: enter search mode */
720 cl(scc,R14,BRENABL); /* disable baudrate generator */
723 or(scc,R14,BRENABL); /* enable baudrate generator */
742 wr(scc, R14, BRSRC); /* BRG source = PCLK */
743 OutReg(scc->ctrl, R14, SSBR|scc->wreg[R14]); /* DPLL source = BRG */
744 OutReg(scc->ctrl, R14, SNRZ
[all...]
H A Dz8530.h20 #define R14 14 macro
H A Ddmascc.c824 write_scc(priv, R14, SSBR | DTRREQ | BRSRC | BRENABL);
826 write_scc(priv, R14, SEARCH | DTRREQ | BRSRC | BRENABL);
829 write_scc(priv, R14, DTRREQ | BRSRC);
/drivers/tty/serial/
H A Dzs.h73 #define R14 14 macro
H A Dip22zilog.c203 write_zsreg(channel, R14, regs[R14] & ~BRENAB);
212 /* Now rewrite R14, with BRENAB (if set). */
213 write_zsreg(channel, R14, regs[R14]);
814 up->curregs[R14] = BRENAB;
1148 up->curregs[R14] = BRENAB;
H A Dpmac_zilog.c171 write_zsreg(uap, R14, regs[R14] & ~BRENAB);
180 /* Now rewrite R14, with BRENAB (if set). */
181 write_zsreg(uap, R14, regs[R14]);
877 uap->curregs[R14] = BRENAB;
1022 uap->curregs[R14] = 0; /* BRG off */
1031 uap->curregs[R14] = 0;
1036 uap->curregs[R14] = 0;
1044 uap->curregs[R14]
[all...]
H A Dip22zilog.h52 #define R14 14 macro
H A Dsunzilog.h44 #define R14 14 macro
H A Dsunzilog.c222 write_zsreg(channel, R14, regs[R14] & ~BRENAB);
231 /* Now rewrite R14, with BRENAB (if set). */
232 write_zsreg(channel, R14, regs[R14]);
880 up->curregs[R14] = BRSRC | BRENAB;
1380 up->curregs[R14] = BRSRC | BRENAB;
H A Dpmac_zilog.h140 #define R14 14 macro
H A Dzs.c278 write_zsreg(zport, R14, regs[14] & ~BRENABL);
282 write_zsreg(zport, R14, regs[14]);
416 write_zsreg(zport, R14, zport->regs[14]);

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