| /drivers/net/hamradio/ |
| H A D | dmascc.c | 502 write_scc(priv, R15, SHDLCE);
503 if (!read_scc(priv, R15)) {
517 write_scc(priv, R15, 0);
530 write_scc(priv, R15, CTSIE);
549 write_scc(priv, R15, 0);
776 write_scc(priv, R15, SHDLCE);
779 write_scc(priv, R15, 0);
783 write_scc(priv, R15, SHDLCE);
811 write_scc(priv, R15, 0);
858 write_scc(priv, R15, DCDI
[all...] |
| H A D | scc.c | 859 or(scc,R15,SHDLCE|FIFOE); /* enable FIFO, SDLC/HDLC Enhancements (From now R7 is R7') */
871 wr(scc,R15, BRKIE|TxUIE|(scc->kiss.softdcd? SYNCIE:DCDIE));
915 or(scc, R15, TxUIE);
924 cl(scc, R15, DCDIE|SYNCIE); /* No DCD changes, please */
951 or(scc,R15, scc->kiss.softdcd? SYNCIE:DCDIE);
962 cl(scc, R15, DCDIE|SYNCIE);
983 or(scc, R15, scc->kiss.softdcd? SYNCIE:DCDIE);
1250 cl(scc, R15, TxUIE); /* count it. */
1322 or(scc, R15, SYNCIE);
1323 cl(scc, R15, DCDI
[all...] |
| H A D | z8530.h | 21 #define R15 15 macro
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| /drivers/media/video/ |
| H A D | wm8775.c | 50 R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R23 = 23, enumerator in enum:__anon1684
112 wm8775_write(sd, R15, vol_r | 0x100); /* 0x100= Right channel ADC zero cross enable */
285 wm8775_write(sd, R15, 0x1d4);
|
| H A D | wm8739.c | 50 R5 = 5, R6, R7, R8, R9, R15 = 15, enumerator in enum:__anon1682
250 wm8739_write(sd, R15, 0x00);
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| H A D | upd64083.c | 48 R15, R16, enumerator in enum:__anon1663
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| /drivers/tty/serial/ |
| H A D | ip22zilog.c | 216 write_zsreg(channel, R15, regs[R15]);
333 if (up->curregs[R15] & BRKIE) {
647 new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
648 if (new_reg != up->curregs[R15]) {
649 up->curregs[R15] = new_reg;
652 write_zsreg(channel, R15, up->curregs[R15]);
1042 up->curregs[R15] |= BRKIE;
|
| H A D | sunzilog.c | 235 write_zsreg(channel, R15, (regs[R15] | WR7pEN) & ~FIFOEN);
238 r15 = read_zsreg(channel, R15);
243 write_zsreg(channel, R15, regs[R15] & ~WR7pEN);
247 regs[R15] &= ~FIFOEN;
748 new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
749 if (new_reg != up->curregs[R15]) {
750 up->curregs[R15] = new_reg;
753 write_zsreg(channel, R15, u
[all...] |
| H A D | pmac_zilog.c | 160 write_zsreg(uap, R15, regs[R15] | EN85C30);
164 write_zsreg(uap, R15, regs[R15] & ~EN85C30);
695 new_reg = uap->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
696 if (new_reg != uap->curregs[R15]) {
697 uap->curregs[R15] = new_reg;
700 write_zsreg(uap, R15, uap->curregs[R15]);
880 uap->curregs[R15]
[all...] |
| H A D | zs.h | 74 #define R15 15 macro
|
| H A D | zs.c | 283 write_zsreg(zport, R15, regs[15]);
467 write_zsreg(zport_a, R15, zport_a->regs[15]);
482 write_zsreg(zport, R15, zport->regs[15]);
512 write_zsreg(zport_a, R15, zport_a->regs[15]);
513 write_zsreg(zport, R15, zport->regs[15]);
794 write_zsreg(zport, R15, zport->regs[15]);
|
| H A D | ip22zilog.h | 53 #define R15 15 macro
|
| H A D | sunzilog.h | 45 #define R15 15 macro
|
| H A D | pmac_zilog.h | 141 #define R15 15 macro
|
| /drivers/net/wan/ |
| H A D | z85230.c | 1271 write_zsreg(&dev->chanA, R15, 0x01);
1274 * If we can set the low bit of R15 then
1278 if(read_zsreg(&dev->chanA, R15)==0x01)
1295 write_zsreg(&dev->chanA, R15, 0);
1393 write_zsreg(c, R15, c->regs[15]|1);
1396 write_zsreg(c, R15, c->regs[15]&~1);
|
| H A D | z85230.h | 40 #define R15 15 macro
|