Searched refs:R7 (Results 1 - 14 of 14) sorted by relevance

/drivers/media/video/
H A Dwm8739.c50 R5 = 5, R6, R7, R8, R9, R15 = 15, enumerator in enum:__anon1682
257 wm8739_write(sd, R7, 0x049);
H A Dwm8775.c49 R7 = 7, R11 = 11, enumerator in enum:__anon1684
273 wm8775_write(sd, R7, 0x000);
/drivers/net/hamradio/
H A Dz8530.h13 #define R7 7 macro
H A Ddmascc.c772 write_scc(priv, R7, FLAG);
778 write_scc(priv, R7, AUTOEOM);
805 write_scc(priv, R7, AUTOEOM | TXFIFOE);
807 write_scc(priv, R7, AUTOEOM);
809 write_scc(priv, R7, AUTOEOM | RXFIFOH);
H A Dscc.c804 wr(scc,R7,FLAG); /* SDLC flag value */
859 or(scc,R15,SHDLCE|FIFOE); /* enable FIFO, SDLC/HDLC Enhancements (From now R7 is R7') */
860 wr(scc,R7,AUTOEOM);
1409 wr(scc, R7, FLAG);
1436 wr(scc, R7, pattern);
/drivers/tty/serial/
H A Dzs.h66 #define R7 7 macro
H A Dip22zilog.h45 #define R7 7 macro
H A Dsunzilog.h17 #define R7p 16 /* Written as R7 with P15 bit 0 set */
37 #define R7 7 macro
H A Dpmac_zilog.h133 #define R7 7 macro
H A Dsunzilog.c214 write_zsreg(channel, R7, regs[R7]);
240 write_zsreg(channel, R7, regs[R7p]);
1356 up->curregs[R7] = 0x7E; /* SDLC Flag */
1372 up->curregs[R7] = 0x7E; /* SDLC Flag */
H A Dip22zilog.c195 write_zsreg(channel, R7, regs[R7]);
H A Dpmac_zilog.c159 /* now set R7 "prime" on ESCC */
161 write_zsreg(uap, R7, regs[R7P]);
163 /* make sure we use R7 "non-prime" on ESCC */
168 write_zsreg(uap, R7, regs[R7]);
/drivers/net/wan/
H A Dz85230.h32 #define R7 7 macro
H A Dz85230.c512 read_zsreg(chan, R7);
1290 * The code assumes R7' and friends are

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