Searched refs:csrow (Results 1 - 25 of 26) sorted by relevance

12

/drivers/edac/
H A Dedac_mc.c48 debugf4("\tchannel->csrow = %p\n\n", chan->csrow);
51 static void edac_mc_dump_csrow(struct csrow_info *csrow) argument
53 debugf4("\tcsrow = %p\n", csrow);
54 debugf4("\tcsrow->csrow_idx = %d\n", csrow->csrow_idx);
55 debugf4("\tcsrow->first_page = 0x%lx\n", csrow->first_page);
56 debugf4("\tcsrow->last_page = 0x%lx\n", csrow->last_page);
57 debugf4("\tcsrow->page_mask = 0x%lx\n", csrow->page_mask);
58 debugf4("\tcsrow->nr_pages = 0x%x\n", csrow->nr_pages);
59 debugf4("\tcsrow->nr_channels = %d\n", csrow
158 struct csrow_info *csi, *csrow; local
645 struct csrow_info *csrow = &csrows[i]; local
818 edac_mc_handle_fbd_ue(struct mem_ctl_info *mci, unsigned int csrow, unsigned int channela, unsigned int channelb, char *msg) argument
885 edac_mc_handle_fbd_ce(struct mem_ctl_info *mci, unsigned int csrow, unsigned int channel, char *msg) argument
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H A Dtile_edac.c84 struct csrow_info *csrow = &mci->csrows[0]; local
96 csrow->edac_mode = EDAC_SECDED;
98 csrow->edac_mode = EDAC_NONE;
101 csrow->mtype = MEM_DDR2;
105 csrow->mtype = MEM_DDR3;
112 csrow->first_page = 0;
113 csrow->nr_pages = mem_info.mem_size >> PAGE_SHIFT;
114 csrow->last_page = csrow->first_page + csrow
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H A Dpasemi_edac.c137 struct csrow_info *csrow; local
142 csrow = &mci->csrows[index];
154 csrow->nr_pages = 128 << (20 - PAGE_SHIFT);
157 csrow->nr_pages = 256 << (20 - PAGE_SHIFT);
161 csrow->nr_pages = 512 << (20 - PAGE_SHIFT);
164 csrow->nr_pages = 1024 << (20 - PAGE_SHIFT);
167 csrow->nr_pages = 2048 << (20 - PAGE_SHIFT);
176 csrow->first_page = last_page_in_mmc;
177 csrow->last_page = csrow
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H A Dcell_edac.c36 struct csrow_info *csrow = &mci->csrows[0]; local
51 edac_mc_handle_ce(mci, csrow->first_page + pfn, offset,
58 struct csrow_info *csrow = &mci->csrows[0]; local
72 edac_mc_handle_ue(mci, csrow->first_page + pfn, offset, 0, "");
126 struct csrow_info *csrow = &mci->csrows[0]; local
142 csrow->first_page = r.start >> PAGE_SHIFT;
143 csrow->nr_pages = resource_size(&r) >> PAGE_SHIFT;
144 csrow->last_page = csrow->first_page + csrow
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H A Damd76x_edac.c188 struct csrow_info *csrow; local
193 csrow = &mci->csrows[index];
205 csrow->first_page = mba_base >> PAGE_SHIFT;
206 csrow->nr_pages = (mba_mask + 1) >> PAGE_SHIFT;
207 csrow->last_page = csrow->first_page + csrow->nr_pages - 1;
208 csrow->page_mask = mba_mask >> PAGE_SHIFT;
209 csrow->grain = csrow
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H A Dr82600_edac.c218 struct csrow_info *csrow; local
229 csrow = &mci->csrows[index];
248 csrow->first_page = row_base >> PAGE_SHIFT;
249 csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1;
250 csrow->nr_pages = csrow->last_page - csrow->first_page + 1;
253 csrow->grain = 1 << 14;
254 csrow->mtype = reg_sdram ? MEM_RDDR : MEM_DDR;
256 csrow
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H A Dedac_mc_sysfs.c131 /* Set of more default csrow<id> attribute show/store functions */
132 static ssize_t csrow_ue_count_show(struct csrow_info *csrow, char *data, argument
135 return sprintf(data, "%u\n", csrow->ue_count);
138 static ssize_t csrow_ce_count_show(struct csrow_info *csrow, char *data, argument
141 return sprintf(data, "%u\n", csrow->ce_count);
144 static ssize_t csrow_size_show(struct csrow_info *csrow, char *data, argument
147 return sprintf(data, "%u\n", PAGES_TO_MiB(csrow->nr_pages));
150 static ssize_t csrow_mem_type_show(struct csrow_info *csrow, char *data, argument
153 return sprintf(data, "%s\n", mem_types[csrow->mtype]);
156 static ssize_t csrow_dev_type_show(struct csrow_info *csrow, cha argument
162 csrow_edac_mode_show(struct csrow_info *csrow, char *data, int private) argument
169 channel_dimm_label_show(struct csrow_info *csrow, char *data, int channel) argument
180 channel_dimm_label_store(struct csrow_info *csrow, const char *data, size_t count, int channel) argument
194 channel_ce_count_show(struct csrow_info *csrow, char *data, int channel) argument
215 struct csrow_info *csrow = to_csrow(kobj); local
227 struct csrow_info *csrow = to_csrow(kobj); local
361 edac_create_csrow_object(struct mem_ctl_info *mci, struct csrow_info *csrow, int index) argument
526 struct csrow_info *csrow = &mci->csrows[csrow_idx]; local
905 struct csrow_info *csrow; local
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H A Di82860_edac.c142 struct csrow_info *csrow; local
155 csrow = &mci->csrows[index];
165 csrow->first_page = last_cumul_size;
166 csrow->last_page = cumul_size - 1;
167 csrow->nr_pages = cumul_size - last_cumul_size;
169 csrow->grain = 1 << 12; /* I82860_EAP has 4KiB reolution */
170 csrow->mtype = MEM_RMBS;
171 csrow->dtype = DEV_UNKNOWN;
172 csrow->edac_mode = mchcfg_ddim ? EDAC_SECDED : EDAC_NONE;
H A Di82443bxgx_edac.c191 struct csrow_info *csrow; local
199 csrow = &mci->csrows[index];
218 csrow->first_page = row_base >> PAGE_SHIFT;
219 csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1;
220 csrow->nr_pages = csrow->last_page - csrow->first_page + 1;
222 csrow->grain = 1 << 12;
223 csrow->mtype = mtype;
225 csrow
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H A Di3000_edac.c381 struct csrow_info *csrow = &mci->csrows[i]; local
390 csrow->mtype = MEM_EMPTY;
394 csrow->first_page = last_cumul_size;
395 csrow->last_page = cumul_size - 1;
396 csrow->nr_pages = cumul_size - last_cumul_size;
398 csrow->grain = I3000_DEAP_GRAIN;
399 csrow->mtype = MEM_DDR2;
400 csrow->dtype = DEV_UNKNOWN;
401 csrow->edac_mode = EDAC_UNKNOWN;
H A Dx38_edac.c369 struct csrow_info *csrow = &mci->csrows[i]; local
376 csrow->mtype = MEM_EMPTY;
380 csrow->first_page = last_page + 1;
382 csrow->last_page = last_page;
383 csrow->nr_pages = nr_pages;
385 csrow->grain = nr_pages << PAGE_SHIFT;
386 csrow->mtype = MEM_DDR2;
387 csrow->dtype = DEV_UNKNOWN;
388 csrow->edac_mode = EDAC_UNKNOWN;
H A Di82975x_edac.c370 struct csrow_info *csrow; local
388 csrow = &mci->csrows[index];
398 if (csrow->nr_channels > 1)
406 * [0-7] for single-channel; i.e. csrow->nr_channels = 1
407 * [0-3] for dual-channel; i.e. csrow->nr_channels = 2
409 for (chan = 0; chan < csrow->nr_channels; chan++)
410 strncpy(csrow->channels[chan].label,
417 csrow->first_page = last_cumul_size;
418 csrow->last_page = cumul_size - 1;
419 csrow
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H A Di5000_edac.c955 * determine_mtr(pvt, csrow, channel)
957 * return the proper MTR register as determine by the csrow and channel desired
959 static int determine_mtr(struct i5000_pvt *pvt, int csrow, int channel) argument
964 mtr = pvt->b0_mtr[csrow >> 1];
966 mtr = pvt->b1_mtr[csrow >> 1];
991 static void handle_channel(struct i5000_pvt *pvt, int csrow, int channel, argument
998 mtr = determine_mtr(pvt, csrow, channel);
1003 if (amb_present_reg & (1 << (csrow >> 1))) {
1007 ((csrow & 0x1) == 0x1))) {
1035 int csrow, max_csrow local
1244 int csrow; local
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H A De7xxx_edac.c354 struct csrow_info *csrow; local
370 csrow = &mci->csrows[index];
380 csrow->first_page = last_cumul_size;
381 csrow->last_page = cumul_size - 1;
382 csrow->nr_pages = cumul_size - last_cumul_size;
384 csrow->grain = 1 << 12; /* 4KiB - resolution of CELOG */
385 csrow->mtype = MEM_RDDR; /* only one type supported */
386 csrow->dtype = mem_dev ? DEV_X4 : DEV_X8;
394 csrow->edac_mode = EDAC_S4ECD4ED;
397 csrow
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H A Di5400_edac.c864 * determine_mtr(pvt, csrow, channel)
866 * return the proper MTR register as determine by the csrow and desired channel
868 static int determine_mtr(struct i5400_pvt *pvt, int csrow, int channel) argument
876 n = csrow;
879 debugf0("ERROR: trying to access an invalid csrow: %d\n",
880 csrow);
916 static void handle_channel(struct i5400_pvt *pvt, int csrow, int channel, argument
923 mtr = determine_mtr(pvt, csrow, channel);
928 if (amb_present_reg & (1 << csrow)) {
957 int csrow, max_csrow local
1161 int csrow; local
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H A Damd64_edac.c331 * compute the CS base address of the @csrow on the DRAM controller @dct.
334 static void get_cs_base_and_mask(struct amd64_pvt *pvt, int csrow, u8 dct, argument
341 csbase = pvt->csels[dct].csbases[csrow];
342 csmask = pvt->csels[dct].csmasks[csrow];
347 csbase = pvt->csels[dct].csbases[csrow];
348 csmask = pvt->csels[dct].csmasks[csrow >> 1];
377 * csrow that input_addr maps to, or -1 on failure (no csrow claims input_addr).
382 int csrow; local
387 for_each_chip_select(csrow,
722 find_csrow_limits(struct mem_ctl_info *mci, int csrow, u64 *input_addr_min, u64 *input_addr_max) argument
755 int csrow; local
1058 int channel, csrow; local
1392 f10_process_possible_spare(struct amd64_pvt *pvt, u8 dct, int csrow) argument
1423 int csrow; local
1612 int nid, csrow, chan = 0; local
1937 int csrow; local
2186 struct csrow_info *csrow; local
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H A Dcpc925_edac.c331 struct csrow_info *csrow; local
349 csrow = &mci->csrows[index];
352 csrow->first_page = last_nr_pages;
353 csrow->nr_pages = row_size >> PAGE_SHIFT;
354 csrow->last_page = csrow->first_page + csrow->nr_pages - 1;
355 last_nr_pages = csrow->last_page + 1;
357 csrow->mtype = MEM_RDDR;
358 csrow
443 cpc925_mc_get_pfn(struct mem_ctl_info *mci, u32 mear, unsigned long *pfn, unsigned long *offset, int *csrow) argument
534 int csrow = 0, channel = 0; local
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H A Di3200_edac.c372 struct csrow_info *csrow = &mci->csrows[i]; local
379 csrow->mtype = MEM_EMPTY;
383 csrow->first_page = last_page + 1;
385 csrow->last_page = last_page;
386 csrow->nr_pages = nr_pages;
388 csrow->grain = nr_pages << PAGE_SHIFT;
389 csrow->mtype = MEM_DDR2;
390 csrow->dtype = DEV_UNKNOWN;
391 csrow->edac_mode = EDAC_UNKNOWN;
H A Di82875p_edac.c344 struct csrow_info *csrow; local
361 csrow = &mci->csrows[index];
370 csrow->first_page = last_cumul_size;
371 csrow->last_page = cumul_size - 1;
372 csrow->nr_pages = cumul_size - last_cumul_size;
374 csrow->grain = 1 << 12; /* I82875P_EAP has 4KiB reolution */
375 csrow->mtype = MEM_DDR;
376 csrow->dtype = DEV_UNKNOWN;
377 csrow->edac_mode = drc_ddim ? EDAC_SECDED : EDAC_NONE;
H A Di5100_edac.c397 /* convert csrow index into a rank (per channel -- 0..5) */
398 static int i5100_csrow_to_rank(const struct mem_ctl_info *mci, int csrow) argument
402 return csrow % priv->ranksperchan;
405 /* convert csrow index into a channel (0..1) */
406 static int i5100_csrow_to_chan(const struct mem_ctl_info *mci, int csrow) argument
410 return csrow / priv->ranksperchan;
430 const int csrow = i5100_rank_to_csrow(mci, chan, rank); local
434 "cas %u, ras %u, csrow %u, label \"%s\": %s\n",
436 csrow, mci->csrows[csrow]
452 const int csrow = i5100_rank_to_csrow(mci, chan, rank); local
643 i5100_npages(struct mem_ctl_info *mci, int csrow) argument
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H A Dmpc85xx_edac.c777 struct csrow_info *csrow; local
816 csrow = &mci->csrows[row_index];
817 if ((pfn >= csrow->first_page) && (pfn <= csrow->last_page))
885 struct csrow_info *csrow; local
931 csrow = &mci->csrows[index];
945 csrow->first_page = start;
946 csrow->last_page = end;
947 csrow->nr_pages = end + 1 - start;
948 csrow
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H A Dmv64x60_edac.c658 struct csrow_info *csrow; local
666 csrow = &mci->csrows[0];
667 csrow->first_page = 0;
668 csrow->nr_pages = pdata->total_mem >> PAGE_SHIFT;
669 csrow->last_page = csrow->first_page + csrow->nr_pages - 1;
670 csrow->grain = 8;
672 csrow->mtype = (ctl & MV64X60_SDRAM_REGISTERED) ? MEM_RDDR : MEM_DDR;
677 csrow
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H A De752x_edac.c1026 /* Remap csrow index numbers if map_type is "reverse"
1041 struct csrow_info *csrow; local
1068 csrow = &mci->csrows[remap_csrow_index(mci, index)];
1079 csrow->first_page = last_cumul_size;
1080 csrow->last_page = cumul_size - 1;
1081 csrow->nr_pages = cumul_size - last_cumul_size;
1083 csrow->grain = 1 << 12; /* 4KiB - resolution of CELOG */
1084 csrow->mtype = MEM_RDDR; /* only one type supported */
1085 csrow->dtype = mem_dev ? DEV_X4 : DEV_X8;
1093 csrow
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H A Dedac_core.h483 extern void edac_mc_handle_fbd_ue(struct mem_ctl_info *mci, unsigned int csrow,
486 extern void edac_mc_handle_fbd_ce(struct mem_ctl_info *mci, unsigned int csrow,
H A Di7core_edac.c532 * So, this driver is attributing one DIMM memory for one csrow.
601 int csrow = 0; local
717 csr = &mci->csrows[csrow];
725 csr->csrow_idx = csrow;
731 pvt->csrow_map[i][j] = csrow;
754 csrow++;
1758 int csrow; local
1828 csrow = pvt->csrow_map[channel][dimm];
1832 edac_mc_handle_fbd_ue(mci, csrow, 0,
1835 edac_mc_handle_fbd_ce(mci, csrow,
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