Searched refs:reg0 (Results 1 - 25 of 35) sorted by relevance

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/drivers/media/dvb/frontends/
H A Dves1820.c42 u8 reg0; member in struct:ves1820_state
93 static int ves1820_setup_reg0(struct ves1820_state *state, u8 reg0, fe_spectral_inversion_t inversion) argument
95 reg0 |= state->reg0 & 0x62;
98 if (!state->config->invert) reg0 |= 0x20;
99 else reg0 &= ~0x20;
101 if (!state->config->invert) reg0 &= ~0x20;
102 else reg0 |= 0x20;
105 ves1820_writereg(state, 0x00, reg0 & 0xfe);
106 ves1820_writereg(state, 0x00, reg0 |
[all...]
H A Dtua6100.c56 u8 reg0[] = { 0x00, 0x00 }; local
57 struct i2c_msg msg = { .addr = priv->i2c_address, .flags = 0, .buf = reg0, .len = 2 };
76 u8 reg0[] = { 0x00, 0x00 }; local
79 struct i2c_msg msg0 = { .addr = priv->i2c_address, .flags = 0, .buf = reg0, .len = 2 };
89 reg0[1] = 0x03;
91 reg0[1] = 0x07;
H A Dtda10021.c43 u8 reg0; member in struct:tda10021_state
132 static int tda10021_setup_reg0 (struct tda10021_state* state, u8 reg0, argument
135 reg0 |= state->reg0 & 0x63;
138 reg0 &= ~0x20;
140 reg0 |= 0x20;
142 _tda10021_writereg (state, 0x00, reg0 & 0xfe);
143 _tda10021_writereg (state, 0x00, reg0 | 0x01);
145 state->reg0 = reg0;
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H A Dtda10023.c50 u8 reg0; member in struct:tda10023_state
158 static int tda10023_setup_reg0 (struct tda10023_state* state, u8 reg0) argument
160 reg0 |= state->reg0 & 0x63;
162 tda10023_writereg (state, 0x00, reg0 & 0xfe);
163 tda10023_writereg (state, 0x00, reg0 | 0x01);
165 state->reg0 = reg0;
479 p->modulation = ((state->reg0 >> 2) & 7) + QAM_16;
542 state->reg0
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H A Dstv6110.c398 u8 reg0[] = { 0x00, 0x07, 0x11, 0xdc, 0x85, 0x17, 0x01, 0xe6, 0x1e }; local
404 .buf = reg0,
411 reg0[2] &= ~0xc0;
412 reg0[2] |= (config->clk_div << 6);
435 memcpy(&priv->regs, &reg0[1], 8);
H A Dm88rs2000.c225 u8 reg0, reg1; local
229 reg0 = m88rs2000_demod_read(state, 0xb1);
233 m88rs2000_demod_write(state, 0xb1, reg0);
242 u8 reg0, reg1; local
244 reg0 = m88rs2000_demod_read(state, 0xb1);
251 reg0 |= 0x4;
252 reg0 &= 0xbc;
261 m88rs2000_demod_write(state, 0xb1, reg0);
/drivers/sbus/char/
H A Djsflash.c466 struct linux_prom_registers reg0; local
472 (char *)&reg0, sizeof(reg0)) == -1) {
476 if (reg0.which_io != 0) {
478 reg0.which_io, reg0.phys_addr);
486 if ((reg0.phys_addr >> 24) != 0x20) {
488 reg0.which_io, reg0.phys_addr);
492 if ((int)reg0
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/drivers/gpu/drm/gma500/
H A Dintel_gmbus.c264 REG_WRITE(GMBUS0 + reg_offset, bus->reg0);
348 bus->reg0 & 0xff, bus->adapter.name);
352 bus->force_bit = intel_gpio_create(dev_priv, bus->reg0 & 0xff);
422 bus->reg0 = i | GMBUS_RATE_100KHZ;
452 bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | (speed << 8);
463 bus->reg0 & 0xff);
/drivers/net/tokenring/
H A Dmadgemc.c513 unsigned int reg0; local
515 reg0 = inb(dev->base_addr + MC_CONTROL_REG0);
516 if ((val == 0) && (reg0 & MC_CONTROL_REG0_SIFSEL)) {
517 outb(reg0 ^ MC_CONTROL_REG0_SIFSEL,
520 outb(reg0 | MC_CONTROL_REG0_SIFSEL,
523 reg0 = inb(dev->base_addr + MC_CONTROL_REG0);
621 unsigned char reg0, reg1, tmpreg0, i; local
625 reg0 = inb(ioaddr + MC_CONTROL_REG0);
629 tmpreg0 = reg0 & ~(MC_CONTROL_REG0_PAGE + MC_CONTROL_REG0_SIFSEL);
645 outb(reg0, ioadd
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/drivers/net/ethernet/8390/
H A Dsmc-ultra32.c265 /* Save RAM address in the unused reg0 to avoid excess inb's. */
266 ei_status.reg0 = inb(ioaddr + ULTRA32_CFG3) & 0xfc;
268 dev->mem_start = 0xc0000 + ((ei_status.reg0 & 0x7c) << 11);
368 outb(ei_status.reg0 | ((ring_page & 0x60) >> 5), RamReg);
400 outb(ei_status.reg0 | ((ring_offset & 0x6000) >> 13), RamReg);
404 outb(ei_status.reg0, RamReg);
421 outb(ei_status.reg0, RamReg);
H A Dwd.c258 int reg0 = inb(ioaddr); local
259 if (reg0 == 0xff || reg0 == 0) {
268 dev->mem_start = ((reg0&0x3f) << 13) + (high_addr_bits << 19);
374 ei_status.reg0 = ((dev->mem_start>>13) & 0x3f) | WD_MEMENB;
379 outb(ei_status.reg0, ioaddr); /* WD_CMDREG */
487 outb(ei_status.reg0 & ~WD_MEMENB, wd_cmdreg);
H A Dne2k-pci.c96 #define ne2k_flags reg0
225 int irq, reg0, chip_idx = ent->driver_data; local
257 reg0 = inb(ioaddr);
258 if (reg0 == 0xFF)
270 outb(reg0, ioaddr);
H A Dne-h8300.c218 int reg0, ret; local
226 reg0 = inb_p(ioaddr);
227 if (reg0 == 0xFF) {
241 outb_p(reg0, ioaddr + EI_SHIFT(0));
H A D8390.h96 unsigned char reg0; /* Register '0' in a WD8013 */ member in struct:ei_device
H A Dax88796.c119 int reg0; local
122 reg0 = ei_inb(ioaddr);
123 if (reg0 == 0xFF)
132 ei_outb(reg0, ioaddr);
H A Dne.c294 int reg0, ret; local
300 reg0 = inb_p(ioaddr);
301 if (reg0 == 0xFF) {
315 outb_p(reg0, ioaddr);
/drivers/staging/media/easycap/
H A Deasycap_low.c359 int write_saa(struct usb_device *p, u16 reg0, u16 set0) argument
364 SET(p, 0x204, reg0);
379 static int write_vt(struct usb_device *p, u16 reg0, u16 set0) argument
387 SET(p, 0x0504, reg0);
394 reg0, set0, ((got503 << 8) | got502));
399 SET(p, 0x0504, reg0);
416 static int read_vt(struct usb_device *p, u16 reg0) argument
423 SET(p, 0x0504, reg0);
430 reg0, ((got503 << 8) | got502));
541 int read_saa(struct usb_device *p, u16 reg0) argument
556 read_stk(struct usb_device *p, u32 reg0) argument
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/drivers/media/video/zoran/
H A Dzoran_procfs.c95 int i = 0, reg0, reg, val; local
99 reg = reg0 = btread(zr67[i].reg);
110 ZR_DEVNAME(zr), zr67[i].reg, reg0, reg,
/drivers/s390/crypto/
H A Dap_bus.c139 register unsigned long reg0 asm ("0") = AP_MKQID(0,0);
148 : "+d" (reg0), "+d" (reg1), "+d" (reg2) : : "cc" );
173 register unsigned long reg0 asm ("0") = qid;
178 : "+d" (reg0), "=d" (reg1), "+d" (reg2) : : "cc");
192 register unsigned long reg0 asm ("0") = qid | 0x01000000UL;
198 : "+d" (reg0), "=d" (reg1), "+d" (reg2) : : "cc");
213 register unsigned long reg0 asm ("0") = qid | 0x03000000UL;
219 : "+d" (reg0), "+d" (reg1_in), "=d" (reg1_out), "+d" (reg2)
230 register unsigned long reg0 asm ("0") = 0UL | qid | (1UL << 23);
238 : "+d" (reg0), "
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/drivers/gpu/drm/i915/
H A Dintel_i2c.c224 I915_WRITE(GMBUS0 + reg_offset, bus->reg0);
314 bus->reg0 & 0xff, bus->adapter.name);
388 bus->reg0 = i | GMBUS_RATE_100KHZ;
415 bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
/drivers/net/ethernet/adaptec/
H A Dstarfire.c1108 u16 reg0; local
1121 reg0 = mdio_read(dev, np->phys[0], MII_BMCR);
1124 reg0 |= BMCR_ANENABLE | BMCR_ANRESTART;
1126 reg0 &= ~(BMCR_ANENABLE | BMCR_ANRESTART);
1128 reg0 |= BMCR_SPEED100;
1130 reg0 |= BMCR_FULLDPLX;
1136 mdio_write(dev, np->phys[0], MII_BMCR, reg0);
1619 u16 reg0, reg1, reg4, reg5; local
1627 reg0 = mdio_read(dev, np->phys[0], MII_BMCR);
1632 if (reg0
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/drivers/gpu/drm/nouveau/
H A Dnouveau_state.c1101 uint32_t reg0 = ~0, strap; local
1130 reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
1131 if ((reg0 & 0x0f000000) > 0) {
1132 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
1162 if ((reg0 & 0xff00fff0) == 0x20004000) {
1163 if (reg0 & 0x00f00000)
1174 NV_ERROR(dev, "unsupported chipset 0x%08x\n", reg0);
1180 dev_priv->card_type, reg0);
/drivers/gpu/drm/r128/
H A Dr128_drv.h407 #define CCE_PACKET1(reg0, reg1) (R128_CCE_PACKET1 | \
408 (((reg1) >> 2) << 11) | ((reg0) >> 2))
/drivers/hwmon/
H A Dw83795.c307 u8 reg0, reg1; local
311 for (reg0 = 0; reg0 < ARRAY_SIZE(pwm_freq_cksel0) - 1; reg0++) {
312 if (val > (pwm_freq_cksel0[reg0] +
313 pwm_freq_cksel0[reg0 + 1]) / 2)
317 return reg0;
318 best0 = pwm_freq_cksel0[reg0];
330 return reg0;
/drivers/gpu/drm/mga/
H A Dmga_drv.h319 #define DMA_BLOCK(reg0, val0, reg1, val1, reg2, val2, reg3, val3) \
321 DMA_WRITE(0, ((DMAREG(reg0) << 0) | \

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