Searched refs:vco1 (Results 1 - 7 of 7) sorted by relevance

/drivers/gpu/drm/nouveau/
H A Dnv50_calc.c55 *P = pll->vco1.maxfreq / clk;
61 lM = (pll->refclk + pll->vco1.max_inputfreq) / pll->vco1.max_inputfreq;
62 lM = max(lM, (int)pll->vco1.min_m);
63 hM = (pll->refclk + pll->vco1.min_inputfreq) / pll->vco1.min_inputfreq;
64 hM = min(hM, (int)pll->vco1.max_m);
73 if (N < pll->vco1.min_n)
75 if (N > pll->vco1.max_n)
H A Dnouveau_calc.c278 int minvco = pll_lim->vco1.minfreq, maxvco = pll_lim->vco1.maxfreq;
279 int minM = pll_lim->vco1.min_m, maxM = pll_lim->vco1.max_m;
280 int minN = pll_lim->vco1.min_n, maxN = pll_lim->vco1.max_n;
281 int minU = pll_lim->vco1.min_inputfreq;
282 int maxU = pll_lim->vco1.max_inputfreq;
377 int minvco1 = pll_lim->vco1.minfreq, maxvco1 = pll_lim->vco1
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H A Dnouveau_bios.c4714 pll_lim->vco1.minfreq = ROM32(pll_rec[0]);
4715 pll_lim->vco1.maxfreq = ROM32(pll_rec[4]);
4718 pll_lim->vco1.min_inputfreq = ROM32(pll_rec[16]);
4720 pll_lim->vco1.max_inputfreq = pll_lim->vco2.max_inputfreq = INT_MAX;
4723 pll_lim->vco1.min_n = 0x1;
4725 pll_lim->vco1.min_n = 0x5;
4726 pll_lim->vco1.max_n = 0xff;
4727 pll_lim->vco1.min_m = 0x1;
4728 pll_lim->vco1.max_m = 0xd;
4780 pll_lim->vco1
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H A Dnouveau_hw.c528 if (pv.M1 >= pll_lim.vco1.min_m && pv.M1 <= pll_lim.vco1.max_m &&
529 pv.N1 >= pll_lim.vco1.min_n && pv.N1 <= pll_lim.vco1.max_n &&
536 pv.M1 = pll_lim.vco1.max_m;
537 pv.N1 = pll_lim.vco1.min_n;
H A Dnouveau_bios.h189 } vco1, vco2; member in struct:pll_lims
H A Dnv40_pm.c119 if (clk < pll->vco1.maxfreq)
H A Dnv04_crtc.c122 * assumed the threshold is given by vco1 maxfreq/2
129 if (dev_priv->chipset > 0x40 && dot_clock <= (pll_lim.vco1.maxfreq / 2))

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