1/* 2 * Ethernet driver for the Atmel AT91RM9200 (Thunder) 3 * 4 * Copyright (C) 2003 SAN People (Pty) Ltd 5 * 6 * Based on an earlier Atmel EMAC macrocell driver by Atmel and Lineo Inc. 7 * Initial version by Rick Bronson 01/11/2003 8 * 9 * Intel LXT971A PHY support by Christopher Bahns & David Knickerbocker 10 * (Polaroid Corporation) 11 * 12 * Realtek RTL8201(B)L PHY support by Roman Avramenko <roman@imsystems.ru> 13 * 14 * This program is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License 16 * as published by the Free Software Foundation; either version 17 * 2 of the License, or (at your option) any later version. 18 */ 19 20#include <linux/module.h> 21#include <linux/init.h> 22#include <linux/interrupt.h> 23#include <linux/mii.h> 24#include <linux/netdevice.h> 25#include <linux/etherdevice.h> 26#include <linux/skbuff.h> 27#include <linux/dma-mapping.h> 28#include <linux/ethtool.h> 29#include <linux/platform_data/macb.h> 30#include <linux/platform_device.h> 31#include <linux/clk.h> 32#include <linux/gfp.h> 33 34#include <asm/io.h> 35#include <asm/uaccess.h> 36#include <asm/mach-types.h> 37 38#include <mach/at91rm9200_emac.h> 39#include <asm/gpio.h> 40#include <mach/board.h> 41 42#include "at91_ether.h" 43 44#define DRV_NAME "at91_ether" 45#define DRV_VERSION "1.0" 46 47#define LINK_POLL_INTERVAL (HZ) 48 49/* ..................................................................... */ 50 51/* 52 * Read from a EMAC register. 53 */ 54static inline unsigned long at91_emac_read(unsigned int reg) 55{ 56 void __iomem *emac_base = (void __iomem *)AT91_VA_BASE_EMAC; 57 58 return __raw_readl(emac_base + reg); 59} 60 61/* 62 * Write to a EMAC register. 63 */ 64static inline void at91_emac_write(unsigned int reg, unsigned long value) 65{ 66 void __iomem *emac_base = (void __iomem *)AT91_VA_BASE_EMAC; 67 68 __raw_writel(value, emac_base + reg); 69} 70 71/* ........................... PHY INTERFACE ........................... */ 72 73/* 74 * Enable the MDIO bit in MAC control register 75 * When not called from an interrupt-handler, access to the PHY must be 76 * protected by a spinlock. 77 */ 78static void enable_mdi(void) 79{ 80 unsigned long ctl; 81 82 ctl = at91_emac_read(AT91_EMAC_CTL); 83 at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_MPE); /* enable management port */ 84} 85 86/* 87 * Disable the MDIO bit in the MAC control register 88 */ 89static void disable_mdi(void) 90{ 91 unsigned long ctl; 92 93 ctl = at91_emac_read(AT91_EMAC_CTL); 94 at91_emac_write(AT91_EMAC_CTL, ctl & ~AT91_EMAC_MPE); /* disable management port */ 95} 96 97/* 98 * Wait until the PHY operation is complete. 99 */ 100static inline void at91_phy_wait(void) { 101 unsigned long timeout = jiffies + 2; 102 103 while (!(at91_emac_read(AT91_EMAC_SR) & AT91_EMAC_SR_IDLE)) { 104 if (time_after(jiffies, timeout)) { 105 printk("at91_ether: MIO timeout\n"); 106 break; 107 } 108 cpu_relax(); 109 } 110} 111 112/* 113 * Write value to the a PHY register 114 * Note: MDI interface is assumed to already have been enabled. 115 */ 116static void write_phy(unsigned char phy_addr, unsigned char address, unsigned int value) 117{ 118 at91_emac_write(AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_W 119 | ((phy_addr & 0x1f) << 23) | (address << 18) | (value & AT91_EMAC_DATA)); 120 121 /* Wait until IDLE bit in Network Status register is cleared */ 122 at91_phy_wait(); 123} 124 125/* 126 * Read value stored in a PHY register. 127 * Note: MDI interface is assumed to already have been enabled. 128 */ 129static void read_phy(unsigned char phy_addr, unsigned char address, unsigned int *value) 130{ 131 at91_emac_write(AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_R 132 | ((phy_addr & 0x1f) << 23) | (address << 18)); 133 134 /* Wait until IDLE bit in Network Status register is cleared */ 135 at91_phy_wait(); 136 137 *value = at91_emac_read(AT91_EMAC_MAN) & AT91_EMAC_DATA; 138} 139 140/* ........................... PHY MANAGEMENT .......................... */ 141 142/* 143 * Access the PHY to determine the current link speed and mode, and update the 144 * MAC accordingly. 145 * If no link or auto-negotiation is busy, then no changes are made. 146 */ 147static void update_linkspeed(struct net_device *dev, int silent) 148{ 149 struct at91_private *lp = netdev_priv(dev); 150 unsigned int bmsr, bmcr, lpa, mac_cfg; 151 unsigned int speed, duplex; 152 153 if (!mii_link_ok(&lp->mii)) { /* no link */ 154 netif_carrier_off(dev); 155 if (!silent) 156 printk(KERN_INFO "%s: Link down.\n", dev->name); 157 return; 158 } 159 160 /* Link up, or auto-negotiation still in progress */ 161 read_phy(lp->phy_address, MII_BMSR, &bmsr); 162 read_phy(lp->phy_address, MII_BMCR, &bmcr); 163 if (bmcr & BMCR_ANENABLE) { /* AutoNegotiation is enabled */ 164 if (!(bmsr & BMSR_ANEGCOMPLETE)) 165 return; /* Do nothing - another interrupt generated when negotiation complete */ 166 167 read_phy(lp->phy_address, MII_LPA, &lpa); 168 if ((lpa & LPA_100FULL) || (lpa & LPA_100HALF)) speed = SPEED_100; 169 else speed = SPEED_10; 170 if ((lpa & LPA_100FULL) || (lpa & LPA_10FULL)) duplex = DUPLEX_FULL; 171 else duplex = DUPLEX_HALF; 172 } else { 173 speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10; 174 duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF; 175 } 176 177 /* Update the MAC */ 178 mac_cfg = at91_emac_read(AT91_EMAC_CFG) & ~(AT91_EMAC_SPD | AT91_EMAC_FD); 179 if (speed == SPEED_100) { 180 if (duplex == DUPLEX_FULL) /* 100 Full Duplex */ 181 mac_cfg |= AT91_EMAC_SPD | AT91_EMAC_FD; 182 else /* 100 Half Duplex */ 183 mac_cfg |= AT91_EMAC_SPD; 184 } else { 185 if (duplex == DUPLEX_FULL) /* 10 Full Duplex */ 186 mac_cfg |= AT91_EMAC_FD; 187 else {} /* 10 Half Duplex */ 188 } 189 at91_emac_write(AT91_EMAC_CFG, mac_cfg); 190 191 if (!silent) 192 printk(KERN_INFO "%s: Link now %i-%s\n", dev->name, speed, (duplex == DUPLEX_FULL) ? "FullDuplex" : "HalfDuplex"); 193 netif_carrier_on(dev); 194} 195 196/* 197 * Handle interrupts from the PHY 198 */ 199static irqreturn_t at91ether_phy_interrupt(int irq, void *dev_id) 200{ 201 struct net_device *dev = (struct net_device *) dev_id; 202 struct at91_private *lp = netdev_priv(dev); 203 unsigned int phy; 204 205 /* 206 * This hander is triggered on both edges, but the PHY chips expect 207 * level-triggering. We therefore have to check if the PHY actually has 208 * an IRQ pending. 209 */ 210 enable_mdi(); 211 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { 212 read_phy(lp->phy_address, MII_DSINTR_REG, &phy); /* ack interrupt in Davicom PHY */ 213 if (!(phy & (1 << 0))) 214 goto done; 215 } 216 else if (lp->phy_type == MII_LXT971A_ID) { 217 read_phy(lp->phy_address, MII_ISINTS_REG, &phy); /* ack interrupt in Intel PHY */ 218 if (!(phy & (1 << 2))) 219 goto done; 220 } 221 else if (lp->phy_type == MII_BCM5221_ID) { 222 read_phy(lp->phy_address, MII_BCMINTR_REG, &phy); /* ack interrupt in Broadcom PHY */ 223 if (!(phy & (1 << 0))) 224 goto done; 225 } 226 else if (lp->phy_type == MII_KS8721_ID) { 227 read_phy(lp->phy_address, MII_TPISTATUS, &phy); /* ack interrupt in Micrel PHY */ 228 if (!(phy & ((1 << 2) | 1))) 229 goto done; 230 } 231 else if (lp->phy_type == MII_T78Q21x3_ID) { /* ack interrupt in Teridian PHY */ 232 read_phy(lp->phy_address, MII_T78Q21INT_REG, &phy); 233 if (!(phy & ((1 << 2) | 1))) 234 goto done; 235 } 236 else if (lp->phy_type == MII_DP83848_ID) { 237 read_phy(lp->phy_address, MII_DPPHYSTS_REG, &phy); /* ack interrupt in DP83848 PHY */ 238 if (!(phy & (1 << 7))) 239 goto done; 240 } 241 242 update_linkspeed(dev, 0); 243 244done: 245 disable_mdi(); 246 247 return IRQ_HANDLED; 248} 249 250/* 251 * Initialize and enable the PHY interrupt for link-state changes 252 */ 253static void enable_phyirq(struct net_device *dev) 254{ 255 struct at91_private *lp = netdev_priv(dev); 256 unsigned int dsintr, irq_number; 257 int status; 258 259 if (!gpio_is_valid(lp->board_data.phy_irq_pin)) { 260 /* 261 * PHY doesn't have an IRQ pin (RTL8201, DP83847, AC101L), 262 * or board does not have it connected. 263 */ 264 mod_timer(&lp->check_timer, jiffies + LINK_POLL_INTERVAL); 265 return; 266 } 267 268 irq_number = lp->board_data.phy_irq_pin; 269 status = request_irq(irq_number, at91ether_phy_interrupt, 0, dev->name, dev); 270 if (status) { 271 printk(KERN_ERR "at91_ether: PHY IRQ %d request failed - status %d!\n", irq_number, status); 272 return; 273 } 274 275 spin_lock_irq(&lp->lock); 276 enable_mdi(); 277 278 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */ 279 read_phy(lp->phy_address, MII_DSINTR_REG, &dsintr); 280 dsintr = dsintr & ~0xf00; /* clear bits 8..11 */ 281 write_phy(lp->phy_address, MII_DSINTR_REG, dsintr); 282 } 283 else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */ 284 read_phy(lp->phy_address, MII_ISINTE_REG, &dsintr); 285 dsintr = dsintr | 0xf2; /* set bits 1, 4..7 */ 286 write_phy(lp->phy_address, MII_ISINTE_REG, dsintr); 287 } 288 else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */ 289 dsintr = (1 << 15) | ( 1 << 14); 290 write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr); 291 } 292 else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */ 293 dsintr = (1 << 10) | ( 1 << 8); 294 write_phy(lp->phy_address, MII_TPISTATUS, dsintr); 295 } 296 else if (lp->phy_type == MII_T78Q21x3_ID) { /* for Teridian PHY */ 297 read_phy(lp->phy_address, MII_T78Q21INT_REG, &dsintr); 298 dsintr = dsintr | 0x500; /* set bits 8, 10 */ 299 write_phy(lp->phy_address, MII_T78Q21INT_REG, dsintr); 300 } 301 else if (lp->phy_type == MII_DP83848_ID) { /* National Semiconductor DP83848 PHY */ 302 read_phy(lp->phy_address, MII_DPMISR_REG, &dsintr); 303 dsintr = dsintr | 0x3c; /* set bits 2..5 */ 304 write_phy(lp->phy_address, MII_DPMISR_REG, dsintr); 305 read_phy(lp->phy_address, MII_DPMICR_REG, &dsintr); 306 dsintr = dsintr | 0x3; /* set bits 0,1 */ 307 write_phy(lp->phy_address, MII_DPMICR_REG, dsintr); 308 } 309 310 disable_mdi(); 311 spin_unlock_irq(&lp->lock); 312} 313 314/* 315 * Disable the PHY interrupt 316 */ 317static void disable_phyirq(struct net_device *dev) 318{ 319 struct at91_private *lp = netdev_priv(dev); 320 unsigned int dsintr; 321 unsigned int irq_number; 322 323 if (!gpio_is_valid(lp->board_data.phy_irq_pin)) { 324 del_timer_sync(&lp->check_timer); 325 return; 326 } 327 328 spin_lock_irq(&lp->lock); 329 enable_mdi(); 330 331 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */ 332 read_phy(lp->phy_address, MII_DSINTR_REG, &dsintr); 333 dsintr = dsintr | 0xf00; /* set bits 8..11 */ 334 write_phy(lp->phy_address, MII_DSINTR_REG, dsintr); 335 } 336 else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */ 337 read_phy(lp->phy_address, MII_ISINTE_REG, &dsintr); 338 dsintr = dsintr & ~0xf2; /* clear bits 1, 4..7 */ 339 write_phy(lp->phy_address, MII_ISINTE_REG, dsintr); 340 } 341 else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */ 342 read_phy(lp->phy_address, MII_BCMINTR_REG, &dsintr); 343 dsintr = ~(1 << 14); 344 write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr); 345 } 346 else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */ 347 read_phy(lp->phy_address, MII_TPISTATUS, &dsintr); 348 dsintr = ~((1 << 10) | (1 << 8)); 349 write_phy(lp->phy_address, MII_TPISTATUS, dsintr); 350 } 351 else if (lp->phy_type == MII_T78Q21x3_ID) { /* for Teridian PHY */ 352 read_phy(lp->phy_address, MII_T78Q21INT_REG, &dsintr); 353 dsintr = dsintr & ~0x500; /* clear bits 8, 10 */ 354 write_phy(lp->phy_address, MII_T78Q21INT_REG, dsintr); 355 } 356 else if (lp->phy_type == MII_DP83848_ID) { /* National Semiconductor DP83848 PHY */ 357 read_phy(lp->phy_address, MII_DPMICR_REG, &dsintr); 358 dsintr = dsintr & ~0x3; /* clear bits 0, 1 */ 359 write_phy(lp->phy_address, MII_DPMICR_REG, dsintr); 360 read_phy(lp->phy_address, MII_DPMISR_REG, &dsintr); 361 dsintr = dsintr & ~0x3c; /* clear bits 2..5 */ 362 write_phy(lp->phy_address, MII_DPMISR_REG, dsintr); 363 } 364 365 disable_mdi(); 366 spin_unlock_irq(&lp->lock); 367 368 irq_number = lp->board_data.phy_irq_pin; 369 free_irq(irq_number, dev); /* Free interrupt handler */ 370} 371 372/* 373 * Perform a software reset of the PHY. 374 */ 375#if 0 376static void reset_phy(struct net_device *dev) 377{ 378 struct at91_private *lp = netdev_priv(dev); 379 unsigned int bmcr; 380 381 spin_lock_irq(&lp->lock); 382 enable_mdi(); 383 384 /* Perform PHY reset */ 385 write_phy(lp->phy_address, MII_BMCR, BMCR_RESET); 386 387 /* Wait until PHY reset is complete */ 388 do { 389 read_phy(lp->phy_address, MII_BMCR, &bmcr); 390 } while (!(bmcr & BMCR_RESET)); 391 392 disable_mdi(); 393 spin_unlock_irq(&lp->lock); 394} 395#endif 396 397static void at91ether_check_link(unsigned long dev_id) 398{ 399 struct net_device *dev = (struct net_device *) dev_id; 400 struct at91_private *lp = netdev_priv(dev); 401 402 enable_mdi(); 403 update_linkspeed(dev, 1); 404 disable_mdi(); 405 406 mod_timer(&lp->check_timer, jiffies + LINK_POLL_INTERVAL); 407} 408 409/* ......................... ADDRESS MANAGEMENT ........................ */ 410 411/* 412 * NOTE: Your bootloader must always set the MAC address correctly before 413 * booting into Linux. 414 * 415 * - It must always set the MAC address after reset, even if it doesn't 416 * happen to access the Ethernet while it's booting. Some versions of 417 * U-Boot on the AT91RM9200-DK do not do this. 418 * 419 * - Likewise it must store the addresses in the correct byte order. 420 * MicroMonitor (uMon) on the CSB337 does this incorrectly (and 421 * continues to do so, for bug-compatibility). 422 */ 423 424static short __init unpack_mac_address(struct net_device *dev, unsigned int hi, unsigned int lo) 425{ 426 char addr[6]; 427 428 if (machine_is_csb337()) { 429 addr[5] = (lo & 0xff); /* The CSB337 bootloader stores the MAC the wrong-way around */ 430 addr[4] = (lo & 0xff00) >> 8; 431 addr[3] = (lo & 0xff0000) >> 16; 432 addr[2] = (lo & 0xff000000) >> 24; 433 addr[1] = (hi & 0xff); 434 addr[0] = (hi & 0xff00) >> 8; 435 } 436 else { 437 addr[0] = (lo & 0xff); 438 addr[1] = (lo & 0xff00) >> 8; 439 addr[2] = (lo & 0xff0000) >> 16; 440 addr[3] = (lo & 0xff000000) >> 24; 441 addr[4] = (hi & 0xff); 442 addr[5] = (hi & 0xff00) >> 8; 443 } 444 445 if (is_valid_ether_addr(addr)) { 446 memcpy(dev->dev_addr, &addr, 6); 447 return 1; 448 } 449 return 0; 450} 451 452/* 453 * Set the ethernet MAC address in dev->dev_addr 454 */ 455static void __init get_mac_address(struct net_device *dev) 456{ 457 /* Check Specific-Address 1 */ 458 if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA1H), at91_emac_read(AT91_EMAC_SA1L))) 459 return; 460 /* Check Specific-Address 2 */ 461 if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA2H), at91_emac_read(AT91_EMAC_SA2L))) 462 return; 463 /* Check Specific-Address 3 */ 464 if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA3H), at91_emac_read(AT91_EMAC_SA3L))) 465 return; 466 /* Check Specific-Address 4 */ 467 if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA4H), at91_emac_read(AT91_EMAC_SA4L))) 468 return; 469 470 printk(KERN_ERR "at91_ether: Your bootloader did not configure a MAC address.\n"); 471} 472 473/* 474 * Program the hardware MAC address from dev->dev_addr. 475 */ 476static void update_mac_address(struct net_device *dev) 477{ 478 at91_emac_write(AT91_EMAC_SA1L, (dev->dev_addr[3] << 24) | (dev->dev_addr[2] << 16) | (dev->dev_addr[1] << 8) | (dev->dev_addr[0])); 479 at91_emac_write(AT91_EMAC_SA1H, (dev->dev_addr[5] << 8) | (dev->dev_addr[4])); 480 481 at91_emac_write(AT91_EMAC_SA2L, 0); 482 at91_emac_write(AT91_EMAC_SA2H, 0); 483} 484 485/* 486 * Store the new hardware address in dev->dev_addr, and update the MAC. 487 */ 488static int set_mac_address(struct net_device *dev, void* addr) 489{ 490 struct sockaddr *address = addr; 491 492 if (!is_valid_ether_addr(address->sa_data)) 493 return -EADDRNOTAVAIL; 494 495 memcpy(dev->dev_addr, address->sa_data, dev->addr_len); 496 update_mac_address(dev); 497 498 printk("%s: Setting MAC address to %pM\n", dev->name, 499 dev->dev_addr); 500 501 return 0; 502} 503 504static int inline hash_bit_value(int bitnr, __u8 *addr) 505{ 506 if (addr[bitnr / 8] & (1 << (bitnr % 8))) 507 return 1; 508 return 0; 509} 510 511/* 512 * The hash address register is 64 bits long and takes up two locations in the memory map. 513 * The least significant bits are stored in EMAC_HSL and the most significant 514 * bits in EMAC_HSH. 515 * 516 * The unicast hash enable and the multicast hash enable bits in the network configuration 517 * register enable the reception of hash matched frames. The destination address is 518 * reduced to a 6 bit index into the 64 bit hash register using the following hash function. 519 * The hash function is an exclusive or of every sixth bit of the destination address. 520 * hash_index[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47] 521 * hash_index[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46] 522 * hash_index[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45] 523 * hash_index[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44] 524 * hash_index[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43] 525 * hash_index[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42] 526 * da[0] represents the least significant bit of the first byte received, that is, the multicast/ 527 * unicast indicator, and da[47] represents the most significant bit of the last byte 528 * received. 529 * If the hash index points to a bit that is set in the hash register then the frame will be 530 * matched according to whether the frame is multicast or unicast. 531 * A multicast match will be signalled if the multicast hash enable bit is set, da[0] is 1 and 532 * the hash index points to a bit set in the hash register. 533 * A unicast match will be signalled if the unicast hash enable bit is set, da[0] is 0 and the 534 * hash index points to a bit set in the hash register. 535 * To receive all multicast frames, the hash register should be set with all ones and the 536 * multicast hash enable bit should be set in the network configuration register. 537 */ 538 539/* 540 * Return the hash index value for the specified address. 541 */ 542static int hash_get_index(__u8 *addr) 543{ 544 int i, j, bitval; 545 int hash_index = 0; 546 547 for (j = 0; j < 6; j++) { 548 for (i = 0, bitval = 0; i < 8; i++) 549 bitval ^= hash_bit_value(i*6 + j, addr); 550 551 hash_index |= (bitval << j); 552 } 553 554 return hash_index; 555} 556 557/* 558 * Add multicast addresses to the internal multicast-hash table. 559 */ 560static void at91ether_sethashtable(struct net_device *dev) 561{ 562 struct netdev_hw_addr *ha; 563 unsigned long mc_filter[2]; 564 unsigned int bitnr; 565 566 mc_filter[0] = mc_filter[1] = 0; 567 568 netdev_for_each_mc_addr(ha, dev) { 569 bitnr = hash_get_index(ha->addr); 570 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31); 571 } 572 573 at91_emac_write(AT91_EMAC_HSL, mc_filter[0]); 574 at91_emac_write(AT91_EMAC_HSH, mc_filter[1]); 575} 576 577/* 578 * Enable/Disable promiscuous and multicast modes. 579 */ 580static void at91ether_set_multicast_list(struct net_device *dev) 581{ 582 unsigned long cfg; 583 584 cfg = at91_emac_read(AT91_EMAC_CFG); 585 586 if (dev->flags & IFF_PROMISC) /* Enable promiscuous mode */ 587 cfg |= AT91_EMAC_CAF; 588 else if (dev->flags & (~IFF_PROMISC)) /* Disable promiscuous mode */ 589 cfg &= ~AT91_EMAC_CAF; 590 591 if (dev->flags & IFF_ALLMULTI) { /* Enable all multicast mode */ 592 at91_emac_write(AT91_EMAC_HSH, -1); 593 at91_emac_write(AT91_EMAC_HSL, -1); 594 cfg |= AT91_EMAC_MTI; 595 } else if (!netdev_mc_empty(dev)) { /* Enable specific multicasts */ 596 at91ether_sethashtable(dev); 597 cfg |= AT91_EMAC_MTI; 598 } else if (dev->flags & (~IFF_ALLMULTI)) { /* Disable all multicast mode */ 599 at91_emac_write(AT91_EMAC_HSH, 0); 600 at91_emac_write(AT91_EMAC_HSL, 0); 601 cfg &= ~AT91_EMAC_MTI; 602 } 603 604 at91_emac_write(AT91_EMAC_CFG, cfg); 605} 606 607/* ......................... ETHTOOL SUPPORT ........................... */ 608 609static int mdio_read(struct net_device *dev, int phy_id, int location) 610{ 611 unsigned int value; 612 613 read_phy(phy_id, location, &value); 614 return value; 615} 616 617static void mdio_write(struct net_device *dev, int phy_id, int location, int value) 618{ 619 write_phy(phy_id, location, value); 620} 621 622static int at91ether_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 623{ 624 struct at91_private *lp = netdev_priv(dev); 625 int ret; 626 627 spin_lock_irq(&lp->lock); 628 enable_mdi(); 629 630 ret = mii_ethtool_gset(&lp->mii, cmd); 631 632 disable_mdi(); 633 spin_unlock_irq(&lp->lock); 634 635 if (lp->phy_media == PORT_FIBRE) { /* override media type since mii.c doesn't know */ 636 cmd->supported = SUPPORTED_FIBRE; 637 cmd->port = PORT_FIBRE; 638 } 639 640 return ret; 641} 642 643static int at91ether_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 644{ 645 struct at91_private *lp = netdev_priv(dev); 646 int ret; 647 648 spin_lock_irq(&lp->lock); 649 enable_mdi(); 650 651 ret = mii_ethtool_sset(&lp->mii, cmd); 652 653 disable_mdi(); 654 spin_unlock_irq(&lp->lock); 655 656 return ret; 657} 658 659static int at91ether_nwayreset(struct net_device *dev) 660{ 661 struct at91_private *lp = netdev_priv(dev); 662 int ret; 663 664 spin_lock_irq(&lp->lock); 665 enable_mdi(); 666 667 ret = mii_nway_restart(&lp->mii); 668 669 disable_mdi(); 670 spin_unlock_irq(&lp->lock); 671 672 return ret; 673} 674 675static void at91ether_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 676{ 677 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 678 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 679 strlcpy(info->bus_info, dev_name(dev->dev.parent), sizeof(info->bus_info)); 680} 681 682static const struct ethtool_ops at91ether_ethtool_ops = { 683 .get_settings = at91ether_get_settings, 684 .set_settings = at91ether_set_settings, 685 .get_drvinfo = at91ether_get_drvinfo, 686 .nway_reset = at91ether_nwayreset, 687 .get_link = ethtool_op_get_link, 688}; 689 690static int at91ether_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 691{ 692 struct at91_private *lp = netdev_priv(dev); 693 int res; 694 695 if (!netif_running(dev)) 696 return -EINVAL; 697 698 spin_lock_irq(&lp->lock); 699 enable_mdi(); 700 res = generic_mii_ioctl(&lp->mii, if_mii(rq), cmd, NULL); 701 disable_mdi(); 702 spin_unlock_irq(&lp->lock); 703 704 return res; 705} 706 707/* ................................ MAC ................................ */ 708 709/* 710 * Initialize and start the Receiver and Transmit subsystems 711 */ 712static void at91ether_start(struct net_device *dev) 713{ 714 struct at91_private *lp = netdev_priv(dev); 715 struct recv_desc_bufs *dlist, *dlist_phys; 716 int i; 717 unsigned long ctl; 718 719 dlist = lp->dlist; 720 dlist_phys = lp->dlist_phys; 721 722 for (i = 0; i < MAX_RX_DESCR; i++) { 723 dlist->descriptors[i].addr = (unsigned int) &dlist_phys->recv_buf[i][0]; 724 dlist->descriptors[i].size = 0; 725 } 726 727 /* Set the Wrap bit on the last descriptor */ 728 dlist->descriptors[i-1].addr |= EMAC_DESC_WRAP; 729 730 /* Reset buffer index */ 731 lp->rxBuffIndex = 0; 732 733 /* Program address of descriptor list in Rx Buffer Queue register */ 734 at91_emac_write(AT91_EMAC_RBQP, (unsigned long) dlist_phys); 735 736 /* Enable Receive and Transmit */ 737 ctl = at91_emac_read(AT91_EMAC_CTL); 738 at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_RE | AT91_EMAC_TE); 739} 740 741/* 742 * Open the ethernet interface 743 */ 744static int at91ether_open(struct net_device *dev) 745{ 746 struct at91_private *lp = netdev_priv(dev); 747 unsigned long ctl; 748 749 if (!is_valid_ether_addr(dev->dev_addr)) 750 return -EADDRNOTAVAIL; 751 752 clk_enable(lp->ether_clk); /* Re-enable Peripheral clock */ 753 754 /* Clear internal statistics */ 755 ctl = at91_emac_read(AT91_EMAC_CTL); 756 at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_CSR); 757 758 /* Update the MAC address (incase user has changed it) */ 759 update_mac_address(dev); 760 761 /* Enable PHY interrupt */ 762 enable_phyirq(dev); 763 764 /* Enable MAC interrupts */ 765 at91_emac_write(AT91_EMAC_IER, AT91_EMAC_RCOM | AT91_EMAC_RBNA 766 | AT91_EMAC_TUND | AT91_EMAC_RTRY | AT91_EMAC_TCOM 767 | AT91_EMAC_ROVR | AT91_EMAC_ABT); 768 769 /* Determine current link speed */ 770 spin_lock_irq(&lp->lock); 771 enable_mdi(); 772 update_linkspeed(dev, 0); 773 disable_mdi(); 774 spin_unlock_irq(&lp->lock); 775 776 at91ether_start(dev); 777 netif_start_queue(dev); 778 return 0; 779} 780 781/* 782 * Close the interface 783 */ 784static int at91ether_close(struct net_device *dev) 785{ 786 struct at91_private *lp = netdev_priv(dev); 787 unsigned long ctl; 788 789 /* Disable Receiver and Transmitter */ 790 ctl = at91_emac_read(AT91_EMAC_CTL); 791 at91_emac_write(AT91_EMAC_CTL, ctl & ~(AT91_EMAC_TE | AT91_EMAC_RE)); 792 793 /* Disable PHY interrupt */ 794 disable_phyirq(dev); 795 796 /* Disable MAC interrupts */ 797 at91_emac_write(AT91_EMAC_IDR, AT91_EMAC_RCOM | AT91_EMAC_RBNA 798 | AT91_EMAC_TUND | AT91_EMAC_RTRY | AT91_EMAC_TCOM 799 | AT91_EMAC_ROVR | AT91_EMAC_ABT); 800 801 netif_stop_queue(dev); 802 803 clk_disable(lp->ether_clk); /* Disable Peripheral clock */ 804 805 return 0; 806} 807 808/* 809 * Transmit packet. 810 */ 811static int at91ether_start_xmit(struct sk_buff *skb, struct net_device *dev) 812{ 813 struct at91_private *lp = netdev_priv(dev); 814 815 if (at91_emac_read(AT91_EMAC_TSR) & AT91_EMAC_TSR_BNQ) { 816 netif_stop_queue(dev); 817 818 /* Store packet information (to free when Tx completed) */ 819 lp->skb = skb; 820 lp->skb_length = skb->len; 821 lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE); 822 dev->stats.tx_bytes += skb->len; 823 824 /* Set address of the data in the Transmit Address register */ 825 at91_emac_write(AT91_EMAC_TAR, lp->skb_physaddr); 826 /* Set length of the packet in the Transmit Control register */ 827 at91_emac_write(AT91_EMAC_TCR, skb->len); 828 829 } else { 830 printk(KERN_ERR "at91_ether.c: at91ether_start_xmit() called, but device is busy!\n"); 831 return NETDEV_TX_BUSY; /* if we return anything but zero, dev.c:1055 calls kfree_skb(skb) 832 on this skb, he also reports -ENETDOWN and printk's, so either 833 we free and return(0) or don't free and return 1 */ 834 } 835 836 return NETDEV_TX_OK; 837} 838 839/* 840 * Update the current statistics from the internal statistics registers. 841 */ 842static struct net_device_stats *at91ether_stats(struct net_device *dev) 843{ 844 int ale, lenerr, seqe, lcol, ecol; 845 846 if (netif_running(dev)) { 847 dev->stats.rx_packets += at91_emac_read(AT91_EMAC_OK); /* Good frames received */ 848 ale = at91_emac_read(AT91_EMAC_ALE); 849 dev->stats.rx_frame_errors += ale; /* Alignment errors */ 850 lenerr = at91_emac_read(AT91_EMAC_ELR) + at91_emac_read(AT91_EMAC_USF); 851 dev->stats.rx_length_errors += lenerr; /* Excessive Length or Undersize Frame error */ 852 seqe = at91_emac_read(AT91_EMAC_SEQE); 853 dev->stats.rx_crc_errors += seqe; /* CRC error */ 854 dev->stats.rx_fifo_errors += at91_emac_read(AT91_EMAC_DRFC); /* Receive buffer not available */ 855 dev->stats.rx_errors += (ale + lenerr + seqe 856 + at91_emac_read(AT91_EMAC_CDE) + at91_emac_read(AT91_EMAC_RJB)); 857 858 dev->stats.tx_packets += at91_emac_read(AT91_EMAC_FRA); /* Frames successfully transmitted */ 859 dev->stats.tx_fifo_errors += at91_emac_read(AT91_EMAC_TUE); /* Transmit FIFO underruns */ 860 dev->stats.tx_carrier_errors += at91_emac_read(AT91_EMAC_CSE); /* Carrier Sense errors */ 861 dev->stats.tx_heartbeat_errors += at91_emac_read(AT91_EMAC_SQEE);/* Heartbeat error */ 862 863 lcol = at91_emac_read(AT91_EMAC_LCOL); 864 ecol = at91_emac_read(AT91_EMAC_ECOL); 865 dev->stats.tx_window_errors += lcol; /* Late collisions */ 866 dev->stats.tx_aborted_errors += ecol; /* 16 collisions */ 867 868 dev->stats.collisions += (at91_emac_read(AT91_EMAC_SCOL) + at91_emac_read(AT91_EMAC_MCOL) + lcol + ecol); 869 } 870 return &dev->stats; 871} 872 873/* 874 * Extract received frame from buffer descriptors and sent to upper layers. 875 * (Called from interrupt context) 876 */ 877static void at91ether_rx(struct net_device *dev) 878{ 879 struct at91_private *lp = netdev_priv(dev); 880 struct recv_desc_bufs *dlist; 881 unsigned char *p_recv; 882 struct sk_buff *skb; 883 unsigned int pktlen; 884 885 dlist = lp->dlist; 886 while (dlist->descriptors[lp->rxBuffIndex].addr & EMAC_DESC_DONE) { 887 p_recv = dlist->recv_buf[lp->rxBuffIndex]; 888 pktlen = dlist->descriptors[lp->rxBuffIndex].size & 0x7ff; /* Length of frame including FCS */ 889 skb = netdev_alloc_skb(dev, pktlen + 2); 890 if (skb != NULL) { 891 skb_reserve(skb, 2); 892 memcpy(skb_put(skb, pktlen), p_recv, pktlen); 893 894 skb->protocol = eth_type_trans(skb, dev); 895 dev->stats.rx_bytes += pktlen; 896 netif_rx(skb); 897 } 898 else { 899 dev->stats.rx_dropped += 1; 900 printk(KERN_NOTICE "%s: Memory squeeze, dropping packet.\n", dev->name); 901 } 902 903 if (dlist->descriptors[lp->rxBuffIndex].size & EMAC_MULTICAST) 904 dev->stats.multicast++; 905 906 dlist->descriptors[lp->rxBuffIndex].addr &= ~EMAC_DESC_DONE; /* reset ownership bit */ 907 if (lp->rxBuffIndex == MAX_RX_DESCR-1) /* wrap after last buffer */ 908 lp->rxBuffIndex = 0; 909 else 910 lp->rxBuffIndex++; 911 } 912} 913 914/* 915 * MAC interrupt handler 916 */ 917static irqreturn_t at91ether_interrupt(int irq, void *dev_id) 918{ 919 struct net_device *dev = (struct net_device *) dev_id; 920 struct at91_private *lp = netdev_priv(dev); 921 unsigned long intstatus, ctl; 922 923 /* MAC Interrupt Status register indicates what interrupts are pending. 924 It is automatically cleared once read. */ 925 intstatus = at91_emac_read(AT91_EMAC_ISR); 926 927 if (intstatus & AT91_EMAC_RCOM) /* Receive complete */ 928 at91ether_rx(dev); 929 930 if (intstatus & AT91_EMAC_TCOM) { /* Transmit complete */ 931 /* The TCOM bit is set even if the transmission failed. */ 932 if (intstatus & (AT91_EMAC_TUND | AT91_EMAC_RTRY)) 933 dev->stats.tx_errors += 1; 934 935 if (lp->skb) { 936 dev_kfree_skb_irq(lp->skb); 937 lp->skb = NULL; 938 dma_unmap_single(NULL, lp->skb_physaddr, lp->skb_length, DMA_TO_DEVICE); 939 } 940 netif_wake_queue(dev); 941 } 942 943 /* Work-around for Errata #11 */ 944 if (intstatus & AT91_EMAC_RBNA) { 945 ctl = at91_emac_read(AT91_EMAC_CTL); 946 at91_emac_write(AT91_EMAC_CTL, ctl & ~AT91_EMAC_RE); 947 at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_RE); 948 } 949 950 if (intstatus & AT91_EMAC_ROVR) 951 printk("%s: ROVR error\n", dev->name); 952 953 return IRQ_HANDLED; 954} 955 956#ifdef CONFIG_NET_POLL_CONTROLLER 957static void at91ether_poll_controller(struct net_device *dev) 958{ 959 unsigned long flags; 960 961 local_irq_save(flags); 962 at91ether_interrupt(dev->irq, dev); 963 local_irq_restore(flags); 964} 965#endif 966 967static const struct net_device_ops at91ether_netdev_ops = { 968 .ndo_open = at91ether_open, 969 .ndo_stop = at91ether_close, 970 .ndo_start_xmit = at91ether_start_xmit, 971 .ndo_get_stats = at91ether_stats, 972 .ndo_set_rx_mode = at91ether_set_multicast_list, 973 .ndo_set_mac_address = set_mac_address, 974 .ndo_do_ioctl = at91ether_ioctl, 975 .ndo_validate_addr = eth_validate_addr, 976 .ndo_change_mtu = eth_change_mtu, 977#ifdef CONFIG_NET_POLL_CONTROLLER 978 .ndo_poll_controller = at91ether_poll_controller, 979#endif 980}; 981 982/* 983 * Initialize the ethernet interface 984 */ 985static int __init at91ether_setup(unsigned long phy_type, unsigned short phy_address, 986 struct platform_device *pdev, struct clk *ether_clk) 987{ 988 struct macb_platform_data *board_data = pdev->dev.platform_data; 989 struct net_device *dev; 990 struct at91_private *lp; 991 unsigned int val; 992 int res; 993 994 dev = alloc_etherdev(sizeof(struct at91_private)); 995 if (!dev) 996 return -ENOMEM; 997 998 dev->base_addr = AT91_VA_BASE_EMAC; 999 dev->irq = AT91RM9200_ID_EMAC; 1000 1001 /* Install the interrupt handler */ 1002 if (request_irq(dev->irq, at91ether_interrupt, 0, dev->name, dev)) { 1003 free_netdev(dev); 1004 return -EBUSY; 1005 } 1006 1007 /* Allocate memory for DMA Receive descriptors */ 1008 lp = netdev_priv(dev); 1009 lp->dlist = (struct recv_desc_bufs *) dma_alloc_coherent(NULL, sizeof(struct recv_desc_bufs), (dma_addr_t *) &lp->dlist_phys, GFP_KERNEL); 1010 if (lp->dlist == NULL) { 1011 free_irq(dev->irq, dev); 1012 free_netdev(dev); 1013 return -ENOMEM; 1014 } 1015 lp->board_data = *board_data; 1016 lp->ether_clk = ether_clk; 1017 platform_set_drvdata(pdev, dev); 1018 1019 spin_lock_init(&lp->lock); 1020 1021 ether_setup(dev); 1022 dev->netdev_ops = &at91ether_netdev_ops; 1023 dev->ethtool_ops = &at91ether_ethtool_ops; 1024 1025 SET_NETDEV_DEV(dev, &pdev->dev); 1026 1027 get_mac_address(dev); /* Get ethernet address and store it in dev->dev_addr */ 1028 update_mac_address(dev); /* Program ethernet address into MAC */ 1029 1030 at91_emac_write(AT91_EMAC_CTL, 0); 1031 1032 if (lp->board_data.is_rmii) 1033 at91_emac_write(AT91_EMAC_CFG, AT91_EMAC_CLK_DIV32 | AT91_EMAC_BIG | AT91_EMAC_RMII); 1034 else 1035 at91_emac_write(AT91_EMAC_CFG, AT91_EMAC_CLK_DIV32 | AT91_EMAC_BIG); 1036 1037 /* Perform PHY-specific initialization */ 1038 spin_lock_irq(&lp->lock); 1039 enable_mdi(); 1040 if ((phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { 1041 read_phy(phy_address, MII_DSCR_REG, &val); 1042 if ((val & (1 << 10)) == 0) /* DSCR bit 10 is 0 -- fiber mode */ 1043 lp->phy_media = PORT_FIBRE; 1044 } else if (machine_is_csb337()) { 1045 /* mix link activity status into LED2 link state */ 1046 write_phy(phy_address, MII_LEDCTRL_REG, 0x0d22); 1047 } else if (machine_is_ecbat91()) 1048 write_phy(phy_address, MII_LEDCTRL_REG, 0x156A); 1049 1050 disable_mdi(); 1051 spin_unlock_irq(&lp->lock); 1052 1053 lp->mii.dev = dev; /* Support for ethtool */ 1054 lp->mii.mdio_read = mdio_read; 1055 lp->mii.mdio_write = mdio_write; 1056 lp->mii.phy_id = phy_address; 1057 lp->mii.phy_id_mask = 0x1f; 1058 lp->mii.reg_num_mask = 0x1f; 1059 1060 lp->phy_type = phy_type; /* Type of PHY connected */ 1061 lp->phy_address = phy_address; /* MDI address of PHY */ 1062 1063 /* Register the network interface */ 1064 res = register_netdev(dev); 1065 if (res) { 1066 free_irq(dev->irq, dev); 1067 free_netdev(dev); 1068 dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys); 1069 return res; 1070 } 1071 1072 /* Determine current link speed */ 1073 spin_lock_irq(&lp->lock); 1074 enable_mdi(); 1075 update_linkspeed(dev, 0); 1076 disable_mdi(); 1077 spin_unlock_irq(&lp->lock); 1078 netif_carrier_off(dev); /* will be enabled in open() */ 1079 1080 /* If board has no PHY IRQ, use a timer to poll the PHY */ 1081 if (!gpio_is_valid(lp->board_data.phy_irq_pin)) { 1082 init_timer(&lp->check_timer); 1083 lp->check_timer.data = (unsigned long)dev; 1084 lp->check_timer.function = at91ether_check_link; 1085 } else if (lp->board_data.phy_irq_pin >= 32) 1086 gpio_request(lp->board_data.phy_irq_pin, "ethernet_phy"); 1087 1088 /* Display ethernet banner */ 1089 printk(KERN_INFO "%s: AT91 ethernet at 0x%08x int=%d %s%s (%pM)\n", 1090 dev->name, (uint) dev->base_addr, dev->irq, 1091 at91_emac_read(AT91_EMAC_CFG) & AT91_EMAC_SPD ? "100-" : "10-", 1092 at91_emac_read(AT91_EMAC_CFG) & AT91_EMAC_FD ? "FullDuplex" : "HalfDuplex", 1093 dev->dev_addr); 1094 if ((phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) 1095 printk(KERN_INFO "%s: Davicom 9161 PHY %s\n", dev->name, (lp->phy_media == PORT_FIBRE) ? "(Fiber)" : "(Copper)"); 1096 else if (phy_type == MII_LXT971A_ID) 1097 printk(KERN_INFO "%s: Intel LXT971A PHY\n", dev->name); 1098 else if (phy_type == MII_RTL8201_ID) 1099 printk(KERN_INFO "%s: Realtek RTL8201(B)L PHY\n", dev->name); 1100 else if (phy_type == MII_BCM5221_ID) 1101 printk(KERN_INFO "%s: Broadcom BCM5221 PHY\n", dev->name); 1102 else if (phy_type == MII_DP83847_ID) 1103 printk(KERN_INFO "%s: National Semiconductor DP83847 PHY\n", dev->name); 1104 else if (phy_type == MII_DP83848_ID) 1105 printk(KERN_INFO "%s: National Semiconductor DP83848 PHY\n", dev->name); 1106 else if (phy_type == MII_AC101L_ID) 1107 printk(KERN_INFO "%s: Altima AC101L PHY\n", dev->name); 1108 else if (phy_type == MII_KS8721_ID) 1109 printk(KERN_INFO "%s: Micrel KS8721 PHY\n", dev->name); 1110 else if (phy_type == MII_T78Q21x3_ID) 1111 printk(KERN_INFO "%s: Teridian 78Q21x3 PHY\n", dev->name); 1112 else if (phy_type == MII_LAN83C185_ID) 1113 printk(KERN_INFO "%s: SMSC LAN83C185 PHY\n", dev->name); 1114 1115 return 0; 1116} 1117 1118/* 1119 * Detect MAC and PHY and perform initialization 1120 */ 1121static int __init at91ether_probe(struct platform_device *pdev) 1122{ 1123 unsigned int phyid1, phyid2; 1124 int detected = -1; 1125 unsigned long phy_id; 1126 unsigned short phy_address = 0; 1127 struct clk *ether_clk; 1128 1129 ether_clk = clk_get(&pdev->dev, "ether_clk"); 1130 if (IS_ERR(ether_clk)) { 1131 printk(KERN_ERR "at91_ether: no clock defined\n"); 1132 return -ENODEV; 1133 } 1134 clk_enable(ether_clk); /* Enable Peripheral clock */ 1135 1136 while ((detected != 0) && (phy_address < 32)) { 1137 /* Read the PHY ID registers */ 1138 enable_mdi(); 1139 read_phy(phy_address, MII_PHYSID1, &phyid1); 1140 read_phy(phy_address, MII_PHYSID2, &phyid2); 1141 disable_mdi(); 1142 1143 phy_id = (phyid1 << 16) | (phyid2 & 0xfff0); 1144 switch (phy_id) { 1145 case MII_DM9161_ID: /* Davicom 9161: PHY_ID1 = 0x181, PHY_ID2 = B881 */ 1146 case MII_DM9161A_ID: /* Davicom 9161A: PHY_ID1 = 0x181, PHY_ID2 = B8A0 */ 1147 case MII_LXT971A_ID: /* Intel LXT971A: PHY_ID1 = 0x13, PHY_ID2 = 78E0 */ 1148 case MII_RTL8201_ID: /* Realtek RTL8201: PHY_ID1 = 0, PHY_ID2 = 0x8201 */ 1149 case MII_BCM5221_ID: /* Broadcom BCM5221: PHY_ID1 = 0x40, PHY_ID2 = 0x61e0 */ 1150 case MII_DP83847_ID: /* National Semiconductor DP83847: */ 1151 case MII_DP83848_ID: /* National Semiconductor DP83848: */ 1152 case MII_AC101L_ID: /* Altima AC101L: PHY_ID1 = 0x22, PHY_ID2 = 0x5520 */ 1153 case MII_KS8721_ID: /* Micrel KS8721: PHY_ID1 = 0x22, PHY_ID2 = 0x1610 */ 1154 case MII_T78Q21x3_ID: /* Teridian 78Q21x3: PHY_ID1 = 0x0E, PHY_ID2 = 7237 */ 1155 case MII_LAN83C185_ID: /* SMSC LAN83C185: PHY_ID1 = 0x0007, PHY_ID2 = 0xC0A1 */ 1156 detected = at91ether_setup(phy_id, phy_address, pdev, ether_clk); 1157 break; 1158 } 1159 1160 phy_address++; 1161 } 1162 1163 clk_disable(ether_clk); /* Disable Peripheral clock */ 1164 1165 return detected; 1166} 1167 1168static int __devexit at91ether_remove(struct platform_device *pdev) 1169{ 1170 struct net_device *dev = platform_get_drvdata(pdev); 1171 struct at91_private *lp = netdev_priv(dev); 1172 1173 if (gpio_is_valid(lp->board_data.phy_irq_pin) && 1174 lp->board_data.phy_irq_pin >= 32) 1175 gpio_free(lp->board_data.phy_irq_pin); 1176 1177 unregister_netdev(dev); 1178 free_irq(dev->irq, dev); 1179 dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys); 1180 clk_put(lp->ether_clk); 1181 1182 platform_set_drvdata(pdev, NULL); 1183 free_netdev(dev); 1184 return 0; 1185} 1186 1187#ifdef CONFIG_PM 1188 1189static int at91ether_suspend(struct platform_device *pdev, pm_message_t mesg) 1190{ 1191 struct net_device *net_dev = platform_get_drvdata(pdev); 1192 struct at91_private *lp = netdev_priv(net_dev); 1193 1194 if (netif_running(net_dev)) { 1195 if (gpio_is_valid(lp->board_data.phy_irq_pin)) { 1196 int phy_irq = lp->board_data.phy_irq_pin; 1197 disable_irq(phy_irq); 1198 } 1199 1200 netif_stop_queue(net_dev); 1201 netif_device_detach(net_dev); 1202 1203 clk_disable(lp->ether_clk); 1204 } 1205 return 0; 1206} 1207 1208static int at91ether_resume(struct platform_device *pdev) 1209{ 1210 struct net_device *net_dev = platform_get_drvdata(pdev); 1211 struct at91_private *lp = netdev_priv(net_dev); 1212 1213 if (netif_running(net_dev)) { 1214 clk_enable(lp->ether_clk); 1215 1216 netif_device_attach(net_dev); 1217 netif_start_queue(net_dev); 1218 1219 if (gpio_is_valid(lp->board_data.phy_irq_pin)) { 1220 int phy_irq = lp->board_data.phy_irq_pin; 1221 enable_irq(phy_irq); 1222 } 1223 } 1224 return 0; 1225} 1226 1227#else 1228#define at91ether_suspend NULL 1229#define at91ether_resume NULL 1230#endif 1231 1232static struct platform_driver at91ether_driver = { 1233 .remove = __devexit_p(at91ether_remove), 1234 .suspend = at91ether_suspend, 1235 .resume = at91ether_resume, 1236 .driver = { 1237 .name = DRV_NAME, 1238 .owner = THIS_MODULE, 1239 }, 1240}; 1241 1242static int __init at91ether_init(void) 1243{ 1244 return platform_driver_probe(&at91ether_driver, at91ether_probe); 1245} 1246 1247static void __exit at91ether_exit(void) 1248{ 1249 platform_driver_unregister(&at91ether_driver); 1250} 1251 1252module_init(at91ether_init) 1253module_exit(at91ether_exit) 1254 1255MODULE_LICENSE("GPL"); 1256MODULE_DESCRIPTION("AT91RM9200 EMAC Ethernet driver"); 1257MODULE_AUTHOR("Andrew Victor"); 1258MODULE_ALIAS("platform:" DRV_NAME); 1259