1d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* 2d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * Ethernet driver for the Atmel AT91RM9200 (Thunder) 3d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * 4d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * Copyright (C) 2003 SAN People (Pty) Ltd 5d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * 6d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * Based on an earlier Atmel EMAC macrocell driver by Atmel and Lineo Inc. 7d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * Initial version by Rick Bronson 01/11/2003 8d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * 9d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * Intel LXT971A PHY support by Christopher Bahns & David Knickerbocker 10d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * (Polaroid Corporation) 11d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * 12d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * Realtek RTL8201(B)L PHY support by Roman Avramenko <roman@imsystems.ru> 13d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * 14d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * This program is free software; you can redistribute it and/or 15d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * modify it under the terms of the GNU General Public License 16d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * as published by the Free Software Foundation; either version 17d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * 2 of the License, or (at your option) any later version. 18d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor */ 19d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 20d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor#include <linux/module.h> 21d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor#include <linux/init.h> 22a6b7a407865aab9f849dd99a71072b7cd1175116Alexey Dobriyan#include <linux/interrupt.h> 23d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor#include <linux/mii.h> 24d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor#include <linux/netdevice.h> 25d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor#include <linux/etherdevice.h> 26d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor#include <linux/skbuff.h> 27d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor#include <linux/dma-mapping.h> 28d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor#include <linux/ethtool.h> 2984e0cdb0a262483a3618091c43dae33d36226430Jamie Iles#include <linux/platform_data/macb.h> 30d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor#include <linux/platform_device.h> 31d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor#include <linux/clk.h> 325a0e3ad6af8660be21ca98a971cd00f331318c05Tejun Heo#include <linux/gfp.h> 33d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 34d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor#include <asm/io.h> 35d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor#include <asm/uaccess.h> 36d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor#include <asm/mach-types.h> 37d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 38a09e64fbc0094e3073dbb09c3b4bfe4ab669244bRussell King#include <mach/at91rm9200_emac.h> 3960e8972dc7e1df843d7132fb572e74f10502a4b7Russell King#include <asm/gpio.h> 40a09e64fbc0094e3073dbb09c3b4bfe4ab669244bRussell King#include <mach/board.h> 41d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 42d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor#include "at91_ether.h" 43d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 44d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor#define DRV_NAME "at91_ether" 45d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor#define DRV_VERSION "1.0" 46d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 47775637df0caccc204628ebacca2b07f35c88b96bAndrew Victor#define LINK_POLL_INTERVAL (HZ) 48775637df0caccc204628ebacca2b07f35c88b96bAndrew Victor 49d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* ..................................................................... */ 50d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 51d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* 52d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * Read from a EMAC register. 53d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor */ 54d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victorstatic inline unsigned long at91_emac_read(unsigned int reg) 55d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor{ 56d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor void __iomem *emac_base = (void __iomem *)AT91_VA_BASE_EMAC; 57d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 58d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor return __raw_readl(emac_base + reg); 59d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor} 60d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 61d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* 62d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * Write to a EMAC register. 63d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor */ 64d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victorstatic inline void at91_emac_write(unsigned int reg, unsigned long value) 65d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor{ 66d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor void __iomem *emac_base = (void __iomem *)AT91_VA_BASE_EMAC; 67d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 68d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor __raw_writel(value, emac_base + reg); 69d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor} 70d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 71d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* ........................... PHY INTERFACE ........................... */ 72d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 73d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* 74d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * Enable the MDIO bit in MAC control register 75d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * When not called from an interrupt-handler, access to the PHY must be 76d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * protected by a spinlock. 77d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor */ 78d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victorstatic void enable_mdi(void) 79d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor{ 80d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor unsigned long ctl; 81d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 82d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor ctl = at91_emac_read(AT91_EMAC_CTL); 83d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_MPE); /* enable management port */ 84d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor} 85d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 86d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* 87d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * Disable the MDIO bit in the MAC control register 88d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor */ 89d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victorstatic void disable_mdi(void) 90d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor{ 91d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor unsigned long ctl; 92d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 93d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor ctl = at91_emac_read(AT91_EMAC_CTL); 94d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor at91_emac_write(AT91_EMAC_CTL, ctl & ~AT91_EMAC_MPE); /* disable management port */ 95d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor} 96d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 97d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* 98d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * Wait until the PHY operation is complete. 99d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor */ 100d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victorstatic inline void at91_phy_wait(void) { 101d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor unsigned long timeout = jiffies + 2; 102d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 103d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor while (!(at91_emac_read(AT91_EMAC_SR) & AT91_EMAC_SR_IDLE)) { 104d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if (time_after(jiffies, timeout)) { 105d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor printk("at91_ether: MIO timeout\n"); 106d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor break; 107d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } 108d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor cpu_relax(); 109d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } 110d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor} 111d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 112d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* 113d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * Write value to the a PHY register 114d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * Note: MDI interface is assumed to already have been enabled. 115d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor */ 116d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victorstatic void write_phy(unsigned char phy_addr, unsigned char address, unsigned int value) 117d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor{ 118d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor at91_emac_write(AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_W 119d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor | ((phy_addr & 0x1f) << 23) | (address << 18) | (value & AT91_EMAC_DATA)); 120d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 121d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor /* Wait until IDLE bit in Network Status register is cleared */ 122d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor at91_phy_wait(); 123d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor} 124d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 125d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* 126d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * Read value stored in a PHY register. 127d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * Note: MDI interface is assumed to already have been enabled. 128d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor */ 129d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victorstatic void read_phy(unsigned char phy_addr, unsigned char address, unsigned int *value) 130d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor{ 131d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor at91_emac_write(AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_R 132d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor | ((phy_addr & 0x1f) << 23) | (address << 18)); 133d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 134d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor /* Wait until IDLE bit in Network Status register is cleared */ 135d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor at91_phy_wait(); 136d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 137d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor *value = at91_emac_read(AT91_EMAC_MAN) & AT91_EMAC_DATA; 138d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor} 139d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 140d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* ........................... PHY MANAGEMENT .......................... */ 141d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 142d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* 143d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * Access the PHY to determine the current link speed and mode, and update the 144d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * MAC accordingly. 145d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * If no link or auto-negotiation is busy, then no changes are made. 146d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor */ 147775637df0caccc204628ebacca2b07f35c88b96bAndrew Victorstatic void update_linkspeed(struct net_device *dev, int silent) 148d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor{ 149c57ee096b6caf8f7e17abe46185d24f2b649b9f9Andrew Victor struct at91_private *lp = netdev_priv(dev); 150d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor unsigned int bmsr, bmcr, lpa, mac_cfg; 151d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor unsigned int speed, duplex; 152d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 153d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if (!mii_link_ok(&lp->mii)) { /* no link */ 154d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor netif_carrier_off(dev); 155775637df0caccc204628ebacca2b07f35c88b96bAndrew Victor if (!silent) 156775637df0caccc204628ebacca2b07f35c88b96bAndrew Victor printk(KERN_INFO "%s: Link down.\n", dev->name); 157d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor return; 158d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } 159d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 160d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor /* Link up, or auto-negotiation still in progress */ 161d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor read_phy(lp->phy_address, MII_BMSR, &bmsr); 162d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor read_phy(lp->phy_address, MII_BMCR, &bmcr); 163d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if (bmcr & BMCR_ANENABLE) { /* AutoNegotiation is enabled */ 164d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if (!(bmsr & BMSR_ANEGCOMPLETE)) 165d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor return; /* Do nothing - another interrupt generated when negotiation complete */ 166d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 167d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor read_phy(lp->phy_address, MII_LPA, &lpa); 168d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if ((lpa & LPA_100FULL) || (lpa & LPA_100HALF)) speed = SPEED_100; 169d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor else speed = SPEED_10; 170d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if ((lpa & LPA_100FULL) || (lpa & LPA_10FULL)) duplex = DUPLEX_FULL; 171d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor else duplex = DUPLEX_HALF; 172d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } else { 173d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10; 174d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF; 175d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } 176d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 177d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor /* Update the MAC */ 178d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor mac_cfg = at91_emac_read(AT91_EMAC_CFG) & ~(AT91_EMAC_SPD | AT91_EMAC_FD); 179d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if (speed == SPEED_100) { 180d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if (duplex == DUPLEX_FULL) /* 100 Full Duplex */ 181d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor mac_cfg |= AT91_EMAC_SPD | AT91_EMAC_FD; 182d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor else /* 100 Half Duplex */ 183d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor mac_cfg |= AT91_EMAC_SPD; 184d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } else { 185d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if (duplex == DUPLEX_FULL) /* 10 Full Duplex */ 186d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor mac_cfg |= AT91_EMAC_FD; 187d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor else {} /* 10 Half Duplex */ 188d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } 189d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor at91_emac_write(AT91_EMAC_CFG, mac_cfg); 190d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 191775637df0caccc204628ebacca2b07f35c88b96bAndrew Victor if (!silent) 192775637df0caccc204628ebacca2b07f35c88b96bAndrew Victor printk(KERN_INFO "%s: Link now %i-%s\n", dev->name, speed, (duplex == DUPLEX_FULL) ? "FullDuplex" : "HalfDuplex"); 193d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor netif_carrier_on(dev); 194d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor} 195d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 196d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* 197d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * Handle interrupts from the PHY 198d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor */ 1997d12e780e003f93433d49ce78cfedf4b4c52adc5David Howellsstatic irqreturn_t at91ether_phy_interrupt(int irq, void *dev_id) 200d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor{ 201d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor struct net_device *dev = (struct net_device *) dev_id; 202c57ee096b6caf8f7e17abe46185d24f2b649b9f9Andrew Victor struct at91_private *lp = netdev_priv(dev); 203d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor unsigned int phy; 204d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 205d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor /* 206d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * This hander is triggered on both edges, but the PHY chips expect 207d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * level-triggering. We therefore have to check if the PHY actually has 208d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * an IRQ pending. 209d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor */ 210d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor enable_mdi(); 211d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { 212d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor read_phy(lp->phy_address, MII_DSINTR_REG, &phy); /* ack interrupt in Davicom PHY */ 213d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if (!(phy & (1 << 0))) 214d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor goto done; 215d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } 216d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor else if (lp->phy_type == MII_LXT971A_ID) { 217d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor read_phy(lp->phy_address, MII_ISINTS_REG, &phy); /* ack interrupt in Intel PHY */ 218d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if (!(phy & (1 << 2))) 219d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor goto done; 220d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } 221d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor else if (lp->phy_type == MII_BCM5221_ID) { 222d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor read_phy(lp->phy_address, MII_BCMINTR_REG, &phy); /* ack interrupt in Broadcom PHY */ 223d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if (!(phy & (1 << 0))) 224d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor goto done; 225d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } 226d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor else if (lp->phy_type == MII_KS8721_ID) { 227d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor read_phy(lp->phy_address, MII_TPISTATUS, &phy); /* ack interrupt in Micrel PHY */ 228d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if (!(phy & ((1 << 2) | 1))) 229d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor goto done; 230d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } 2316b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor else if (lp->phy_type == MII_T78Q21x3_ID) { /* ack interrupt in Teridian PHY */ 2326b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor read_phy(lp->phy_address, MII_T78Q21INT_REG, &phy); 2336b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor if (!(phy & ((1 << 2) | 1))) 2346b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor goto done; 2356b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor } 2366b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor else if (lp->phy_type == MII_DP83848_ID) { 2376b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor read_phy(lp->phy_address, MII_DPPHYSTS_REG, &phy); /* ack interrupt in DP83848 PHY */ 2386b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor if (!(phy & (1 << 7))) 2396b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor goto done; 2406b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor } 241d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 242775637df0caccc204628ebacca2b07f35c88b96bAndrew Victor update_linkspeed(dev, 0); 243d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 244d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victordone: 245d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor disable_mdi(); 246d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 247d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor return IRQ_HANDLED; 248d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor} 249d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 250d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* 251d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * Initialize and enable the PHY interrupt for link-state changes 252d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor */ 253d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victorstatic void enable_phyirq(struct net_device *dev) 254d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor{ 255c57ee096b6caf8f7e17abe46185d24f2b649b9f9Andrew Victor struct at91_private *lp = netdev_priv(dev); 256d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor unsigned int dsintr, irq_number; 257d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor int status; 258d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 2592839038bb1a72ed7ef3c39521e0ca981c9cb1534Nicolas Ferre if (!gpio_is_valid(lp->board_data.phy_irq_pin)) { 260775637df0caccc204628ebacca2b07f35c88b96bAndrew Victor /* 261775637df0caccc204628ebacca2b07f35c88b96bAndrew Victor * PHY doesn't have an IRQ pin (RTL8201, DP83847, AC101L), 262775637df0caccc204628ebacca2b07f35c88b96bAndrew Victor * or board does not have it connected. 263775637df0caccc204628ebacca2b07f35c88b96bAndrew Victor */ 264cf42553ab43e102bc98eca05523d2390a1eedde9Andrew Victor mod_timer(&lp->check_timer, jiffies + LINK_POLL_INTERVAL); 265d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor return; 266775637df0caccc204628ebacca2b07f35c88b96bAndrew Victor } 267d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 2682839038bb1a72ed7ef3c39521e0ca981c9cb1534Nicolas Ferre irq_number = lp->board_data.phy_irq_pin; 269d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor status = request_irq(irq_number, at91ether_phy_interrupt, 0, dev->name, dev); 270d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if (status) { 271d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor printk(KERN_ERR "at91_ether: PHY IRQ %d request failed - status %d!\n", irq_number, status); 272d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor return; 273d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } 274d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 275d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor spin_lock_irq(&lp->lock); 276d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor enable_mdi(); 277d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 278d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */ 279d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor read_phy(lp->phy_address, MII_DSINTR_REG, &dsintr); 280d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor dsintr = dsintr & ~0xf00; /* clear bits 8..11 */ 281d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor write_phy(lp->phy_address, MII_DSINTR_REG, dsintr); 282d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } 283d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */ 284d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor read_phy(lp->phy_address, MII_ISINTE_REG, &dsintr); 285d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor dsintr = dsintr | 0xf2; /* set bits 1, 4..7 */ 286d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor write_phy(lp->phy_address, MII_ISINTE_REG, dsintr); 287d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } 288d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */ 289d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor dsintr = (1 << 15) | ( 1 << 14); 290d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr); 291d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } 292d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */ 293d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor dsintr = (1 << 10) | ( 1 << 8); 294d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor write_phy(lp->phy_address, MII_TPISTATUS, dsintr); 295d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } 2966b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor else if (lp->phy_type == MII_T78Q21x3_ID) { /* for Teridian PHY */ 2976b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor read_phy(lp->phy_address, MII_T78Q21INT_REG, &dsintr); 2986b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor dsintr = dsintr | 0x500; /* set bits 8, 10 */ 2996b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor write_phy(lp->phy_address, MII_T78Q21INT_REG, dsintr); 3006b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor } 3016b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor else if (lp->phy_type == MII_DP83848_ID) { /* National Semiconductor DP83848 PHY */ 3026b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor read_phy(lp->phy_address, MII_DPMISR_REG, &dsintr); 3036b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor dsintr = dsintr | 0x3c; /* set bits 2..5 */ 3046b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor write_phy(lp->phy_address, MII_DPMISR_REG, dsintr); 3056b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor read_phy(lp->phy_address, MII_DPMICR_REG, &dsintr); 3066b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor dsintr = dsintr | 0x3; /* set bits 0,1 */ 3076b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor write_phy(lp->phy_address, MII_DPMICR_REG, dsintr); 3086b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor } 309d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 310d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor disable_mdi(); 311d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor spin_unlock_irq(&lp->lock); 312d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor} 313d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 314d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* 315d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * Disable the PHY interrupt 316d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor */ 317d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victorstatic void disable_phyirq(struct net_device *dev) 318d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor{ 319c57ee096b6caf8f7e17abe46185d24f2b649b9f9Andrew Victor struct at91_private *lp = netdev_priv(dev); 320d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor unsigned int dsintr; 321d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor unsigned int irq_number; 322d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 3232839038bb1a72ed7ef3c39521e0ca981c9cb1534Nicolas Ferre if (!gpio_is_valid(lp->board_data.phy_irq_pin)) { 324cf42553ab43e102bc98eca05523d2390a1eedde9Andrew Victor del_timer_sync(&lp->check_timer); 325d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor return; 326775637df0caccc204628ebacca2b07f35c88b96bAndrew Victor } 327d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 328d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor spin_lock_irq(&lp->lock); 329d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor enable_mdi(); 330d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 331d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */ 332d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor read_phy(lp->phy_address, MII_DSINTR_REG, &dsintr); 333d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor dsintr = dsintr | 0xf00; /* set bits 8..11 */ 334d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor write_phy(lp->phy_address, MII_DSINTR_REG, dsintr); 335d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } 336d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */ 337d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor read_phy(lp->phy_address, MII_ISINTE_REG, &dsintr); 338d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor dsintr = dsintr & ~0xf2; /* clear bits 1, 4..7 */ 339d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor write_phy(lp->phy_address, MII_ISINTE_REG, dsintr); 340d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } 341d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */ 342d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor read_phy(lp->phy_address, MII_BCMINTR_REG, &dsintr); 343d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor dsintr = ~(1 << 14); 344d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr); 345d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } 346d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */ 347d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor read_phy(lp->phy_address, MII_TPISTATUS, &dsintr); 348d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor dsintr = ~((1 << 10) | (1 << 8)); 349d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor write_phy(lp->phy_address, MII_TPISTATUS, dsintr); 350d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } 3516b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor else if (lp->phy_type == MII_T78Q21x3_ID) { /* for Teridian PHY */ 3526b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor read_phy(lp->phy_address, MII_T78Q21INT_REG, &dsintr); 3536b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor dsintr = dsintr & ~0x500; /* clear bits 8, 10 */ 3546b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor write_phy(lp->phy_address, MII_T78Q21INT_REG, dsintr); 3556b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor } 3566b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor else if (lp->phy_type == MII_DP83848_ID) { /* National Semiconductor DP83848 PHY */ 3576b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor read_phy(lp->phy_address, MII_DPMICR_REG, &dsintr); 3586b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor dsintr = dsintr & ~0x3; /* clear bits 0, 1 */ 3596b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor write_phy(lp->phy_address, MII_DPMICR_REG, dsintr); 3606b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor read_phy(lp->phy_address, MII_DPMISR_REG, &dsintr); 3616b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor dsintr = dsintr & ~0x3c; /* clear bits 2..5 */ 3626b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor write_phy(lp->phy_address, MII_DPMISR_REG, dsintr); 3636b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor } 364d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 365d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor disable_mdi(); 366d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor spin_unlock_irq(&lp->lock); 367d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 3682839038bb1a72ed7ef3c39521e0ca981c9cb1534Nicolas Ferre irq_number = lp->board_data.phy_irq_pin; 369d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor free_irq(irq_number, dev); /* Free interrupt handler */ 370d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor} 371d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 372d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* 373d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * Perform a software reset of the PHY. 374d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor */ 375d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor#if 0 376d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victorstatic void reset_phy(struct net_device *dev) 377d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor{ 378c57ee096b6caf8f7e17abe46185d24f2b649b9f9Andrew Victor struct at91_private *lp = netdev_priv(dev); 379d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor unsigned int bmcr; 380d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 381d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor spin_lock_irq(&lp->lock); 382d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor enable_mdi(); 383d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 384d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor /* Perform PHY reset */ 385d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor write_phy(lp->phy_address, MII_BMCR, BMCR_RESET); 386d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 387d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor /* Wait until PHY reset is complete */ 388d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor do { 389d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor read_phy(lp->phy_address, MII_BMCR, &bmcr); 39010a5a80b3c69d65d66c4d9f4f796725f09bbc8cbRoel Kluin } while (!(bmcr & BMCR_RESET)); 391d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 392d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor disable_mdi(); 393d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor spin_unlock_irq(&lp->lock); 394d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor} 395d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor#endif 396d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 397775637df0caccc204628ebacca2b07f35c88b96bAndrew Victorstatic void at91ether_check_link(unsigned long dev_id) 398775637df0caccc204628ebacca2b07f35c88b96bAndrew Victor{ 399775637df0caccc204628ebacca2b07f35c88b96bAndrew Victor struct net_device *dev = (struct net_device *) dev_id; 400cf42553ab43e102bc98eca05523d2390a1eedde9Andrew Victor struct at91_private *lp = netdev_priv(dev); 401775637df0caccc204628ebacca2b07f35c88b96bAndrew Victor 402775637df0caccc204628ebacca2b07f35c88b96bAndrew Victor enable_mdi(); 403775637df0caccc204628ebacca2b07f35c88b96bAndrew Victor update_linkspeed(dev, 1); 404775637df0caccc204628ebacca2b07f35c88b96bAndrew Victor disable_mdi(); 405775637df0caccc204628ebacca2b07f35c88b96bAndrew Victor 406cf42553ab43e102bc98eca05523d2390a1eedde9Andrew Victor mod_timer(&lp->check_timer, jiffies + LINK_POLL_INTERVAL); 407775637df0caccc204628ebacca2b07f35c88b96bAndrew Victor} 408775637df0caccc204628ebacca2b07f35c88b96bAndrew Victor 409d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* ......................... ADDRESS MANAGEMENT ........................ */ 410d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 411d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* 412d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * NOTE: Your bootloader must always set the MAC address correctly before 413d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * booting into Linux. 414d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * 415d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * - It must always set the MAC address after reset, even if it doesn't 416d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * happen to access the Ethernet while it's booting. Some versions of 417d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * U-Boot on the AT91RM9200-DK do not do this. 418d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * 419d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * - Likewise it must store the addresses in the correct byte order. 420d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * MicroMonitor (uMon) on the CSB337 does this incorrectly (and 421d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * continues to do so, for bug-compatibility). 422d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor */ 423d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 424d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victorstatic short __init unpack_mac_address(struct net_device *dev, unsigned int hi, unsigned int lo) 425d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor{ 426d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor char addr[6]; 427d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 428d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if (machine_is_csb337()) { 429d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor addr[5] = (lo & 0xff); /* The CSB337 bootloader stores the MAC the wrong-way around */ 430d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor addr[4] = (lo & 0xff00) >> 8; 431d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor addr[3] = (lo & 0xff0000) >> 16; 432d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor addr[2] = (lo & 0xff000000) >> 24; 433d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor addr[1] = (hi & 0xff); 434d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor addr[0] = (hi & 0xff00) >> 8; 435d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } 436d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor else { 437d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor addr[0] = (lo & 0xff); 438d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor addr[1] = (lo & 0xff00) >> 8; 439d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor addr[2] = (lo & 0xff0000) >> 16; 440d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor addr[3] = (lo & 0xff000000) >> 24; 441d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor addr[4] = (hi & 0xff); 442d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor addr[5] = (hi & 0xff00) >> 8; 443d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } 444d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 445d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if (is_valid_ether_addr(addr)) { 446d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor memcpy(dev->dev_addr, &addr, 6); 447d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor return 1; 448d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } 449d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor return 0; 450d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor} 451d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 452d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* 453d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * Set the ethernet MAC address in dev->dev_addr 454d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor */ 455d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victorstatic void __init get_mac_address(struct net_device *dev) 456d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor{ 457d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor /* Check Specific-Address 1 */ 458d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA1H), at91_emac_read(AT91_EMAC_SA1L))) 459d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor return; 460d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor /* Check Specific-Address 2 */ 461d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA2H), at91_emac_read(AT91_EMAC_SA2L))) 462d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor return; 463d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor /* Check Specific-Address 3 */ 464d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA3H), at91_emac_read(AT91_EMAC_SA3L))) 465d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor return; 466d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor /* Check Specific-Address 4 */ 467d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA4H), at91_emac_read(AT91_EMAC_SA4L))) 468d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor return; 469d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 470d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor printk(KERN_ERR "at91_ether: Your bootloader did not configure a MAC address.\n"); 471d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor} 472d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 473d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* 474d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * Program the hardware MAC address from dev->dev_addr. 475d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor */ 476d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victorstatic void update_mac_address(struct net_device *dev) 477d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor{ 478d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor at91_emac_write(AT91_EMAC_SA1L, (dev->dev_addr[3] << 24) | (dev->dev_addr[2] << 16) | (dev->dev_addr[1] << 8) | (dev->dev_addr[0])); 479d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor at91_emac_write(AT91_EMAC_SA1H, (dev->dev_addr[5] << 8) | (dev->dev_addr[4])); 480d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 481d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor at91_emac_write(AT91_EMAC_SA2L, 0); 482d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor at91_emac_write(AT91_EMAC_SA2H, 0); 483d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor} 484d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 485d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* 486d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * Store the new hardware address in dev->dev_addr, and update the MAC. 487d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor */ 488d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victorstatic int set_mac_address(struct net_device *dev, void* addr) 489d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor{ 490d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor struct sockaddr *address = addr; 491d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 492d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if (!is_valid_ether_addr(address->sa_data)) 493d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor return -EADDRNOTAVAIL; 494d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 495d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor memcpy(dev->dev_addr, address->sa_data, dev->addr_len); 496d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor update_mac_address(dev); 497d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 498e174961ca1a0b28f7abf0be47973ad57cb74e5f0Johannes Berg printk("%s: Setting MAC address to %pM\n", dev->name, 499e174961ca1a0b28f7abf0be47973ad57cb74e5f0Johannes Berg dev->dev_addr); 500d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 501d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor return 0; 502d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor} 503d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 504d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victorstatic int inline hash_bit_value(int bitnr, __u8 *addr) 505d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor{ 506d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if (addr[bitnr / 8] & (1 << (bitnr % 8))) 507d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor return 1; 508d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor return 0; 509d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor} 510d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 511d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* 512d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * The hash address register is 64 bits long and takes up two locations in the memory map. 513d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * The least significant bits are stored in EMAC_HSL and the most significant 514d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * bits in EMAC_HSH. 515d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * 516d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * The unicast hash enable and the multicast hash enable bits in the network configuration 517d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * register enable the reception of hash matched frames. The destination address is 518d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * reduced to a 6 bit index into the 64 bit hash register using the following hash function. 519d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * The hash function is an exclusive or of every sixth bit of the destination address. 520d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * hash_index[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47] 521d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * hash_index[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46] 522d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * hash_index[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45] 523d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * hash_index[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44] 524d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * hash_index[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43] 525d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * hash_index[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42] 526d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * da[0] represents the least significant bit of the first byte received, that is, the multicast/ 527d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * unicast indicator, and da[47] represents the most significant bit of the last byte 528d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * received. 529d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * If the hash index points to a bit that is set in the hash register then the frame will be 530d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * matched according to whether the frame is multicast or unicast. 531d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * A multicast match will be signalled if the multicast hash enable bit is set, da[0] is 1 and 532d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * the hash index points to a bit set in the hash register. 533d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * A unicast match will be signalled if the unicast hash enable bit is set, da[0] is 0 and the 534d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * hash index points to a bit set in the hash register. 535d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * To receive all multicast frames, the hash register should be set with all ones and the 536d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * multicast hash enable bit should be set in the network configuration register. 537d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor */ 538d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 539d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* 540d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * Return the hash index value for the specified address. 541d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor */ 542d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victorstatic int hash_get_index(__u8 *addr) 543d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor{ 544d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor int i, j, bitval; 545d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor int hash_index = 0; 546d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 547d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor for (j = 0; j < 6; j++) { 548d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor for (i = 0, bitval = 0; i < 8; i++) 549d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor bitval ^= hash_bit_value(i*6 + j, addr); 550d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 551d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor hash_index |= (bitval << j); 552d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } 553d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 554427d269f17fd02d192e9ae3bd93bdc07790fa02cAndrew Victor return hash_index; 555d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor} 556d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 557d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* 558d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * Add multicast addresses to the internal multicast-hash table. 559d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor */ 560d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victorstatic void at91ether_sethashtable(struct net_device *dev) 561d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor{ 56222bedad3ce112d5ca1eaf043d4990fa2ed698c87Jiri Pirko struct netdev_hw_addr *ha; 563d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor unsigned long mc_filter[2]; 5643b9a7728d878a3e7adc79fb89c3bb9ebc23760d7Jiri Pirko unsigned int bitnr; 565d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 566d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor mc_filter[0] = mc_filter[1] = 0; 567d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 56822bedad3ce112d5ca1eaf043d4990fa2ed698c87Jiri Pirko netdev_for_each_mc_addr(ha, dev) { 56922bedad3ce112d5ca1eaf043d4990fa2ed698c87Jiri Pirko bitnr = hash_get_index(ha->addr); 570d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor mc_filter[bitnr >> 5] |= 1 << (bitnr & 31); 571d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } 572d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 5738bc354730bc877ebdf35c692460b01e624934aeaAndrew Victor at91_emac_write(AT91_EMAC_HSL, mc_filter[0]); 5748bc354730bc877ebdf35c692460b01e624934aeaAndrew Victor at91_emac_write(AT91_EMAC_HSH, mc_filter[1]); 575d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor} 576d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 577d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* 578d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * Enable/Disable promiscuous and multicast modes. 579d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor */ 580531c6804a4299663c7fa798ebfa9dbf843e91e0eAlexander Beregalovstatic void at91ether_set_multicast_list(struct net_device *dev) 581d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor{ 582d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor unsigned long cfg; 583d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 584d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor cfg = at91_emac_read(AT91_EMAC_CFG); 585d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 586d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if (dev->flags & IFF_PROMISC) /* Enable promiscuous mode */ 587d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor cfg |= AT91_EMAC_CAF; 588d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor else if (dev->flags & (~IFF_PROMISC)) /* Disable promiscuous mode */ 589d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor cfg &= ~AT91_EMAC_CAF; 590d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 591d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if (dev->flags & IFF_ALLMULTI) { /* Enable all multicast mode */ 592d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor at91_emac_write(AT91_EMAC_HSH, -1); 593d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor at91_emac_write(AT91_EMAC_HSL, -1); 594d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor cfg |= AT91_EMAC_MTI; 5954cd24eaf0c6ee7f0242e34ee77ec899f255e66b5Jiri Pirko } else if (!netdev_mc_empty(dev)) { /* Enable specific multicasts */ 596d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor at91ether_sethashtable(dev); 597d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor cfg |= AT91_EMAC_MTI; 598d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } else if (dev->flags & (~IFF_ALLMULTI)) { /* Disable all multicast mode */ 599d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor at91_emac_write(AT91_EMAC_HSH, 0); 600d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor at91_emac_write(AT91_EMAC_HSL, 0); 601d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor cfg &= ~AT91_EMAC_MTI; 602d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } 603d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 604d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor at91_emac_write(AT91_EMAC_CFG, cfg); 605d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor} 606d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 607d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* ......................... ETHTOOL SUPPORT ........................... */ 608d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 609d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victorstatic int mdio_read(struct net_device *dev, int phy_id, int location) 610d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor{ 611d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor unsigned int value; 612d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 613d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor read_phy(phy_id, location, &value); 614d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor return value; 615d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor} 616d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 617d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victorstatic void mdio_write(struct net_device *dev, int phy_id, int location, int value) 618d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor{ 619d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor write_phy(phy_id, location, value); 620d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor} 621d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 622d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victorstatic int at91ether_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 623d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor{ 624c57ee096b6caf8f7e17abe46185d24f2b649b9f9Andrew Victor struct at91_private *lp = netdev_priv(dev); 625d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor int ret; 626d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 627d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor spin_lock_irq(&lp->lock); 628d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor enable_mdi(); 629d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 630d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor ret = mii_ethtool_gset(&lp->mii, cmd); 631d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 632d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor disable_mdi(); 633d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor spin_unlock_irq(&lp->lock); 634d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 635d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if (lp->phy_media == PORT_FIBRE) { /* override media type since mii.c doesn't know */ 636d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor cmd->supported = SUPPORTED_FIBRE; 637d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor cmd->port = PORT_FIBRE; 638d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } 639d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 640d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor return ret; 641d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor} 642d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 643d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victorstatic int at91ether_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 644d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor{ 645c57ee096b6caf8f7e17abe46185d24f2b649b9f9Andrew Victor struct at91_private *lp = netdev_priv(dev); 646d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor int ret; 647d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 648d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor spin_lock_irq(&lp->lock); 649d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor enable_mdi(); 650d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 651d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor ret = mii_ethtool_sset(&lp->mii, cmd); 652d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 653d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor disable_mdi(); 654d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor spin_unlock_irq(&lp->lock); 655d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 656d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor return ret; 657d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor} 658d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 659d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victorstatic int at91ether_nwayreset(struct net_device *dev) 660d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor{ 661c57ee096b6caf8f7e17abe46185d24f2b649b9f9Andrew Victor struct at91_private *lp = netdev_priv(dev); 662d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor int ret; 663d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 664d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor spin_lock_irq(&lp->lock); 665d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor enable_mdi(); 666d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 667d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor ret = mii_nway_restart(&lp->mii); 668d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 669d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor disable_mdi(); 670d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor spin_unlock_irq(&lp->lock); 671d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 672d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor return ret; 673d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor} 674d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 675d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victorstatic void at91ether_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 676d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor{ 677d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 678d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 6793f9787046ea37a26170dc4439efa21f8d23a9978Kay Sievers strlcpy(info->bus_info, dev_name(dev->dev.parent), sizeof(info->bus_info)); 680d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor} 681d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 6827282d491ecaee9883233a0e27283c4c79486279aJeff Garzikstatic const struct ethtool_ops at91ether_ethtool_ops = { 683d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor .get_settings = at91ether_get_settings, 684d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor .set_settings = at91ether_set_settings, 685d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor .get_drvinfo = at91ether_get_drvinfo, 686d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor .nway_reset = at91ether_nwayreset, 687d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor .get_link = ethtool_op_get_link, 688d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor}; 689d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 690ca5585ed248dc01ce918002ee9a9c9c41ae4f7c0Andrew Victorstatic int at91ether_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 691ca5585ed248dc01ce918002ee9a9c9c41ae4f7c0Andrew Victor{ 692c57ee096b6caf8f7e17abe46185d24f2b649b9f9Andrew Victor struct at91_private *lp = netdev_priv(dev); 693ca5585ed248dc01ce918002ee9a9c9c41ae4f7c0Andrew Victor int res; 694ca5585ed248dc01ce918002ee9a9c9c41ae4f7c0Andrew Victor 695ca5585ed248dc01ce918002ee9a9c9c41ae4f7c0Andrew Victor if (!netif_running(dev)) 696ca5585ed248dc01ce918002ee9a9c9c41ae4f7c0Andrew Victor return -EINVAL; 697ca5585ed248dc01ce918002ee9a9c9c41ae4f7c0Andrew Victor 698ca5585ed248dc01ce918002ee9a9c9c41ae4f7c0Andrew Victor spin_lock_irq(&lp->lock); 699ca5585ed248dc01ce918002ee9a9c9c41ae4f7c0Andrew Victor enable_mdi(); 700ca5585ed248dc01ce918002ee9a9c9c41ae4f7c0Andrew Victor res = generic_mii_ioctl(&lp->mii, if_mii(rq), cmd, NULL); 701ca5585ed248dc01ce918002ee9a9c9c41ae4f7c0Andrew Victor disable_mdi(); 702ca5585ed248dc01ce918002ee9a9c9c41ae4f7c0Andrew Victor spin_unlock_irq(&lp->lock); 703ca5585ed248dc01ce918002ee9a9c9c41ae4f7c0Andrew Victor 704ca5585ed248dc01ce918002ee9a9c9c41ae4f7c0Andrew Victor return res; 705ca5585ed248dc01ce918002ee9a9c9c41ae4f7c0Andrew Victor} 706d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 707d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* ................................ MAC ................................ */ 708d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 709d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* 710d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * Initialize and start the Receiver and Transmit subsystems 711d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor */ 712d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victorstatic void at91ether_start(struct net_device *dev) 713d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor{ 714c57ee096b6caf8f7e17abe46185d24f2b649b9f9Andrew Victor struct at91_private *lp = netdev_priv(dev); 715d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor struct recv_desc_bufs *dlist, *dlist_phys; 716d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor int i; 717d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor unsigned long ctl; 718d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 719d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor dlist = lp->dlist; 720d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor dlist_phys = lp->dlist_phys; 721d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 722d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor for (i = 0; i < MAX_RX_DESCR; i++) { 723d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor dlist->descriptors[i].addr = (unsigned int) &dlist_phys->recv_buf[i][0]; 724d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor dlist->descriptors[i].size = 0; 725d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } 726d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 727d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor /* Set the Wrap bit on the last descriptor */ 728d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor dlist->descriptors[i-1].addr |= EMAC_DESC_WRAP; 729d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 730d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor /* Reset buffer index */ 731d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor lp->rxBuffIndex = 0; 732d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 733d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor /* Program address of descriptor list in Rx Buffer Queue register */ 734d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor at91_emac_write(AT91_EMAC_RBQP, (unsigned long) dlist_phys); 735d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 736d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor /* Enable Receive and Transmit */ 737d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor ctl = at91_emac_read(AT91_EMAC_CTL); 738d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_RE | AT91_EMAC_TE); 739d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor} 740d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 741d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* 742d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * Open the ethernet interface 743d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor */ 744d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victorstatic int at91ether_open(struct net_device *dev) 745d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor{ 746c57ee096b6caf8f7e17abe46185d24f2b649b9f9Andrew Victor struct at91_private *lp = netdev_priv(dev); 747d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor unsigned long ctl; 748d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 749427d269f17fd02d192e9ae3bd93bdc07790fa02cAndrew Victor if (!is_valid_ether_addr(dev->dev_addr)) 750427d269f17fd02d192e9ae3bd93bdc07790fa02cAndrew Victor return -EADDRNOTAVAIL; 751d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 752427d269f17fd02d192e9ae3bd93bdc07790fa02cAndrew Victor clk_enable(lp->ether_clk); /* Re-enable Peripheral clock */ 753d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 754d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor /* Clear internal statistics */ 755d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor ctl = at91_emac_read(AT91_EMAC_CTL); 756d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_CSR); 757d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 758d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor /* Update the MAC address (incase user has changed it) */ 759d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor update_mac_address(dev); 760d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 761d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor /* Enable PHY interrupt */ 762d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor enable_phyirq(dev); 763d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 764d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor /* Enable MAC interrupts */ 765d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor at91_emac_write(AT91_EMAC_IER, AT91_EMAC_RCOM | AT91_EMAC_RBNA 766d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor | AT91_EMAC_TUND | AT91_EMAC_RTRY | AT91_EMAC_TCOM 767d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor | AT91_EMAC_ROVR | AT91_EMAC_ABT); 768d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 769d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor /* Determine current link speed */ 770d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor spin_lock_irq(&lp->lock); 771d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor enable_mdi(); 772775637df0caccc204628ebacca2b07f35c88b96bAndrew Victor update_linkspeed(dev, 0); 773d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor disable_mdi(); 774d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor spin_unlock_irq(&lp->lock); 775d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 776d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor at91ether_start(dev); 777d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor netif_start_queue(dev); 778d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor return 0; 779d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor} 780d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 781d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* 782d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * Close the interface 783d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor */ 784d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victorstatic int at91ether_close(struct net_device *dev) 785d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor{ 786c57ee096b6caf8f7e17abe46185d24f2b649b9f9Andrew Victor struct at91_private *lp = netdev_priv(dev); 787d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor unsigned long ctl; 788d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 789d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor /* Disable Receiver and Transmitter */ 790d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor ctl = at91_emac_read(AT91_EMAC_CTL); 791d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor at91_emac_write(AT91_EMAC_CTL, ctl & ~(AT91_EMAC_TE | AT91_EMAC_RE)); 792d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 793d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor /* Disable PHY interrupt */ 794d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor disable_phyirq(dev); 795d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 796d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor /* Disable MAC interrupts */ 797d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor at91_emac_write(AT91_EMAC_IDR, AT91_EMAC_RCOM | AT91_EMAC_RBNA 798d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor | AT91_EMAC_TUND | AT91_EMAC_RTRY | AT91_EMAC_TCOM 799d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor | AT91_EMAC_ROVR | AT91_EMAC_ABT); 800d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 801d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor netif_stop_queue(dev); 802d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 803427d269f17fd02d192e9ae3bd93bdc07790fa02cAndrew Victor clk_disable(lp->ether_clk); /* Disable Peripheral clock */ 804d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 805d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor return 0; 806d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor} 807d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 808d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* 809d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * Transmit packet. 810d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor */ 811531c6804a4299663c7fa798ebfa9dbf843e91e0eAlexander Beregalovstatic int at91ether_start_xmit(struct sk_buff *skb, struct net_device *dev) 812d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor{ 813c57ee096b6caf8f7e17abe46185d24f2b649b9f9Andrew Victor struct at91_private *lp = netdev_priv(dev); 814d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 815d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if (at91_emac_read(AT91_EMAC_TSR) & AT91_EMAC_TSR_BNQ) { 816d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor netif_stop_queue(dev); 817d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 818d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor /* Store packet information (to free when Tx completed) */ 819d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor lp->skb = skb; 820d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor lp->skb_length = skb->len; 821d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE); 8227a2f53ee0b56ff7e1c0c24404575cb62935d37d9Paulius Zaleckas dev->stats.tx_bytes += skb->len; 823d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 824d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor /* Set address of the data in the Transmit Address register */ 825d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor at91_emac_write(AT91_EMAC_TAR, lp->skb_physaddr); 826d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor /* Set length of the packet in the Transmit Control register */ 827d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor at91_emac_write(AT91_EMAC_TCR, skb->len); 828d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 829d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } else { 830531c6804a4299663c7fa798ebfa9dbf843e91e0eAlexander Beregalov printk(KERN_ERR "at91_ether.c: at91ether_start_xmit() called, but device is busy!\n"); 8315b548140225c6bbbbd560551dd1048b2c0ce58bePatrick McHardy return NETDEV_TX_BUSY; /* if we return anything but zero, dev.c:1055 calls kfree_skb(skb) 832d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor on this skb, he also reports -ENETDOWN and printk's, so either 833d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor we free and return(0) or don't free and return 1 */ 834d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } 835d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 8366ed106549d17474ca17a16057f4c0ed4eba5a7caPatrick McHardy return NETDEV_TX_OK; 837d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor} 838d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 839d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* 840d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * Update the current statistics from the internal statistics registers. 841d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor */ 842d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victorstatic struct net_device_stats *at91ether_stats(struct net_device *dev) 843d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor{ 844d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor int ale, lenerr, seqe, lcol, ecol; 845d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 846d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if (netif_running(dev)) { 8477a2f53ee0b56ff7e1c0c24404575cb62935d37d9Paulius Zaleckas dev->stats.rx_packets += at91_emac_read(AT91_EMAC_OK); /* Good frames received */ 848d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor ale = at91_emac_read(AT91_EMAC_ALE); 8497a2f53ee0b56ff7e1c0c24404575cb62935d37d9Paulius Zaleckas dev->stats.rx_frame_errors += ale; /* Alignment errors */ 850d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor lenerr = at91_emac_read(AT91_EMAC_ELR) + at91_emac_read(AT91_EMAC_USF); 8517a2f53ee0b56ff7e1c0c24404575cb62935d37d9Paulius Zaleckas dev->stats.rx_length_errors += lenerr; /* Excessive Length or Undersize Frame error */ 852d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor seqe = at91_emac_read(AT91_EMAC_SEQE); 8537a2f53ee0b56ff7e1c0c24404575cb62935d37d9Paulius Zaleckas dev->stats.rx_crc_errors += seqe; /* CRC error */ 8547a2f53ee0b56ff7e1c0c24404575cb62935d37d9Paulius Zaleckas dev->stats.rx_fifo_errors += at91_emac_read(AT91_EMAC_DRFC); /* Receive buffer not available */ 8557a2f53ee0b56ff7e1c0c24404575cb62935d37d9Paulius Zaleckas dev->stats.rx_errors += (ale + lenerr + seqe 856d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor + at91_emac_read(AT91_EMAC_CDE) + at91_emac_read(AT91_EMAC_RJB)); 857d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 8587a2f53ee0b56ff7e1c0c24404575cb62935d37d9Paulius Zaleckas dev->stats.tx_packets += at91_emac_read(AT91_EMAC_FRA); /* Frames successfully transmitted */ 8597a2f53ee0b56ff7e1c0c24404575cb62935d37d9Paulius Zaleckas dev->stats.tx_fifo_errors += at91_emac_read(AT91_EMAC_TUE); /* Transmit FIFO underruns */ 8607a2f53ee0b56ff7e1c0c24404575cb62935d37d9Paulius Zaleckas dev->stats.tx_carrier_errors += at91_emac_read(AT91_EMAC_CSE); /* Carrier Sense errors */ 8617a2f53ee0b56ff7e1c0c24404575cb62935d37d9Paulius Zaleckas dev->stats.tx_heartbeat_errors += at91_emac_read(AT91_EMAC_SQEE);/* Heartbeat error */ 862d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 863d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor lcol = at91_emac_read(AT91_EMAC_LCOL); 864d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor ecol = at91_emac_read(AT91_EMAC_ECOL); 8657a2f53ee0b56ff7e1c0c24404575cb62935d37d9Paulius Zaleckas dev->stats.tx_window_errors += lcol; /* Late collisions */ 8667a2f53ee0b56ff7e1c0c24404575cb62935d37d9Paulius Zaleckas dev->stats.tx_aborted_errors += ecol; /* 16 collisions */ 867d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 8687a2f53ee0b56ff7e1c0c24404575cb62935d37d9Paulius Zaleckas dev->stats.collisions += (at91_emac_read(AT91_EMAC_SCOL) + at91_emac_read(AT91_EMAC_MCOL) + lcol + ecol); 869d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } 8707a2f53ee0b56ff7e1c0c24404575cb62935d37d9Paulius Zaleckas return &dev->stats; 871d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor} 872d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 873d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* 874d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * Extract received frame from buffer descriptors and sent to upper layers. 875d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * (Called from interrupt context) 876d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor */ 877d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victorstatic void at91ether_rx(struct net_device *dev) 878d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor{ 879c57ee096b6caf8f7e17abe46185d24f2b649b9f9Andrew Victor struct at91_private *lp = netdev_priv(dev); 880d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor struct recv_desc_bufs *dlist; 881d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor unsigned char *p_recv; 882d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor struct sk_buff *skb; 883d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor unsigned int pktlen; 884d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 885d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor dlist = lp->dlist; 886d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor while (dlist->descriptors[lp->rxBuffIndex].addr & EMAC_DESC_DONE) { 887d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor p_recv = dlist->recv_buf[lp->rxBuffIndex]; 888d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor pktlen = dlist->descriptors[lp->rxBuffIndex].size & 0x7ff; /* Length of frame including FCS */ 8891d266430546acf01438ae42d0a7370db4817e2adPradeep A Dalvi skb = netdev_alloc_skb(dev, pktlen + 2); 890d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if (skb != NULL) { 891d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor skb_reserve(skb, 2); 892d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor memcpy(skb_put(skb, pktlen), p_recv, pktlen); 893d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 894d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor skb->protocol = eth_type_trans(skb, dev); 8957a2f53ee0b56ff7e1c0c24404575cb62935d37d9Paulius Zaleckas dev->stats.rx_bytes += pktlen; 896d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor netif_rx(skb); 897d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } 898d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor else { 8997a2f53ee0b56ff7e1c0c24404575cb62935d37d9Paulius Zaleckas dev->stats.rx_dropped += 1; 900d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor printk(KERN_NOTICE "%s: Memory squeeze, dropping packet.\n", dev->name); 901d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } 902d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 903d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if (dlist->descriptors[lp->rxBuffIndex].size & EMAC_MULTICAST) 9047a2f53ee0b56ff7e1c0c24404575cb62935d37d9Paulius Zaleckas dev->stats.multicast++; 905d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 906d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor dlist->descriptors[lp->rxBuffIndex].addr &= ~EMAC_DESC_DONE; /* reset ownership bit */ 907d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if (lp->rxBuffIndex == MAX_RX_DESCR-1) /* wrap after last buffer */ 908d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor lp->rxBuffIndex = 0; 909d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor else 910d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor lp->rxBuffIndex++; 911d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } 912d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor} 913d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 914d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* 915d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * MAC interrupt handler 916d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor */ 9177d12e780e003f93433d49ce78cfedf4b4c52adc5David Howellsstatic irqreturn_t at91ether_interrupt(int irq, void *dev_id) 918d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor{ 919d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor struct net_device *dev = (struct net_device *) dev_id; 920c57ee096b6caf8f7e17abe46185d24f2b649b9f9Andrew Victor struct at91_private *lp = netdev_priv(dev); 921d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor unsigned long intstatus, ctl; 922d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 923d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor /* MAC Interrupt Status register indicates what interrupts are pending. 924d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor It is automatically cleared once read. */ 925d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor intstatus = at91_emac_read(AT91_EMAC_ISR); 926d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 927d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if (intstatus & AT91_EMAC_RCOM) /* Receive complete */ 928d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor at91ether_rx(dev); 929d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 930427d269f17fd02d192e9ae3bd93bdc07790fa02cAndrew Victor if (intstatus & AT91_EMAC_TCOM) { /* Transmit complete */ 931d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor /* The TCOM bit is set even if the transmission failed. */ 932d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if (intstatus & (AT91_EMAC_TUND | AT91_EMAC_RTRY)) 9337a2f53ee0b56ff7e1c0c24404575cb62935d37d9Paulius Zaleckas dev->stats.tx_errors += 1; 934d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 935d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if (lp->skb) { 936d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor dev_kfree_skb_irq(lp->skb); 937d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor lp->skb = NULL; 938d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor dma_unmap_single(NULL, lp->skb_physaddr, lp->skb_length, DMA_TO_DEVICE); 939d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } 940d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor netif_wake_queue(dev); 941d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } 942d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 943d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor /* Work-around for Errata #11 */ 944d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if (intstatus & AT91_EMAC_RBNA) { 945d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor ctl = at91_emac_read(AT91_EMAC_CTL); 946d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor at91_emac_write(AT91_EMAC_CTL, ctl & ~AT91_EMAC_RE); 947d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_RE); 948d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } 949d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 950d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if (intstatus & AT91_EMAC_ROVR) 951d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor printk("%s: ROVR error\n", dev->name); 952d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 953d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor return IRQ_HANDLED; 954d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor} 955d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 95651cc21045714cc9f48eb6901d95eb4e552ef2ca4Andrew Victor#ifdef CONFIG_NET_POLL_CONTROLLER 95751cc21045714cc9f48eb6901d95eb4e552ef2ca4Andrew Victorstatic void at91ether_poll_controller(struct net_device *dev) 95851cc21045714cc9f48eb6901d95eb4e552ef2ca4Andrew Victor{ 95951cc21045714cc9f48eb6901d95eb4e552ef2ca4Andrew Victor unsigned long flags; 96051cc21045714cc9f48eb6901d95eb4e552ef2ca4Andrew Victor 96151cc21045714cc9f48eb6901d95eb4e552ef2ca4Andrew Victor local_irq_save(flags); 96251cc21045714cc9f48eb6901d95eb4e552ef2ca4Andrew Victor at91ether_interrupt(dev->irq, dev); 96351cc21045714cc9f48eb6901d95eb4e552ef2ca4Andrew Victor local_irq_restore(flags); 96451cc21045714cc9f48eb6901d95eb4e552ef2ca4Andrew Victor} 96551cc21045714cc9f48eb6901d95eb4e552ef2ca4Andrew Victor#endif 96651cc21045714cc9f48eb6901d95eb4e552ef2ca4Andrew Victor 967531c6804a4299663c7fa798ebfa9dbf843e91e0eAlexander Beregalovstatic const struct net_device_ops at91ether_netdev_ops = { 968531c6804a4299663c7fa798ebfa9dbf843e91e0eAlexander Beregalov .ndo_open = at91ether_open, 969531c6804a4299663c7fa798ebfa9dbf843e91e0eAlexander Beregalov .ndo_stop = at91ether_close, 970531c6804a4299663c7fa798ebfa9dbf843e91e0eAlexander Beregalov .ndo_start_xmit = at91ether_start_xmit, 971531c6804a4299663c7fa798ebfa9dbf843e91e0eAlexander Beregalov .ndo_get_stats = at91ether_stats, 972afc4b13df143122f99a0eb10bfefb216c2806de0Jiri Pirko .ndo_set_rx_mode = at91ether_set_multicast_list, 973531c6804a4299663c7fa798ebfa9dbf843e91e0eAlexander Beregalov .ndo_set_mac_address = set_mac_address, 974531c6804a4299663c7fa798ebfa9dbf843e91e0eAlexander Beregalov .ndo_do_ioctl = at91ether_ioctl, 975531c6804a4299663c7fa798ebfa9dbf843e91e0eAlexander Beregalov .ndo_validate_addr = eth_validate_addr, 976531c6804a4299663c7fa798ebfa9dbf843e91e0eAlexander Beregalov .ndo_change_mtu = eth_change_mtu, 977531c6804a4299663c7fa798ebfa9dbf843e91e0eAlexander Beregalov#ifdef CONFIG_NET_POLL_CONTROLLER 978531c6804a4299663c7fa798ebfa9dbf843e91e0eAlexander Beregalov .ndo_poll_controller = at91ether_poll_controller, 979531c6804a4299663c7fa798ebfa9dbf843e91e0eAlexander Beregalov#endif 980531c6804a4299663c7fa798ebfa9dbf843e91e0eAlexander Beregalov}; 981531c6804a4299663c7fa798ebfa9dbf843e91e0eAlexander Beregalov 982d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* 983d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * Initialize the ethernet interface 984d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor */ 985427d269f17fd02d192e9ae3bd93bdc07790fa02cAndrew Victorstatic int __init at91ether_setup(unsigned long phy_type, unsigned short phy_address, 986427d269f17fd02d192e9ae3bd93bdc07790fa02cAndrew Victor struct platform_device *pdev, struct clk *ether_clk) 987d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor{ 98884e0cdb0a262483a3618091c43dae33d36226430Jamie Iles struct macb_platform_data *board_data = pdev->dev.platform_data; 989d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor struct net_device *dev; 990d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor struct at91_private *lp; 991d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor unsigned int val; 992d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor int res; 993d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 994d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor dev = alloc_etherdev(sizeof(struct at91_private)); 995d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if (!dev) 996d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor return -ENOMEM; 997d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 998d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor dev->base_addr = AT91_VA_BASE_EMAC; 99972729910c38ca5b4736032c15dc3f9d48fe4f68aAndrew Victor dev->irq = AT91RM9200_ID_EMAC; 1000d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 1001d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor /* Install the interrupt handler */ 1002d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if (request_irq(dev->irq, at91ether_interrupt, 0, dev->name, dev)) { 1003d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor free_netdev(dev); 1004d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor return -EBUSY; 1005d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } 1006d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 1007d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor /* Allocate memory for DMA Receive descriptors */ 1008c57ee096b6caf8f7e17abe46185d24f2b649b9f9Andrew Victor lp = netdev_priv(dev); 1009d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor lp->dlist = (struct recv_desc_bufs *) dma_alloc_coherent(NULL, sizeof(struct recv_desc_bufs), (dma_addr_t *) &lp->dlist_phys, GFP_KERNEL); 1010d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if (lp->dlist == NULL) { 1011d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor free_irq(dev->irq, dev); 1012d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor free_netdev(dev); 1013d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor return -ENOMEM; 1014d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } 1015d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor lp->board_data = *board_data; 1016427d269f17fd02d192e9ae3bd93bdc07790fa02cAndrew Victor lp->ether_clk = ether_clk; 1017d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor platform_set_drvdata(pdev, dev); 1018d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 1019d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor spin_lock_init(&lp->lock); 1020d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 1021d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor ether_setup(dev); 1022531c6804a4299663c7fa798ebfa9dbf843e91e0eAlexander Beregalov dev->netdev_ops = &at91ether_netdev_ops; 1023d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor dev->ethtool_ops = &at91ether_ethtool_ops; 1024d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 1025d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor SET_NETDEV_DEV(dev, &pdev->dev); 1026d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 1027d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor get_mac_address(dev); /* Get ethernet address and store it in dev->dev_addr */ 1028d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor update_mac_address(dev); /* Program ethernet address into MAC */ 1029d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 1030d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor at91_emac_write(AT91_EMAC_CTL, 0); 1031d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 1032d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if (lp->board_data.is_rmii) 1033d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor at91_emac_write(AT91_EMAC_CFG, AT91_EMAC_CLK_DIV32 | AT91_EMAC_BIG | AT91_EMAC_RMII); 1034d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor else 1035d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor at91_emac_write(AT91_EMAC_CFG, AT91_EMAC_CLK_DIV32 | AT91_EMAC_BIG); 1036d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 1037d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor /* Perform PHY-specific initialization */ 1038d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor spin_lock_irq(&lp->lock); 1039d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor enable_mdi(); 1040d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if ((phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { 1041d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor read_phy(phy_address, MII_DSCR_REG, &val); 1042d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if ((val & (1 << 10)) == 0) /* DSCR bit 10 is 0 -- fiber mode */ 1043d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor lp->phy_media = PORT_FIBRE; 1044d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } else if (machine_is_csb337()) { 1045d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor /* mix link activity status into LED2 link state */ 1046d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor write_phy(phy_address, MII_LEDCTRL_REG, 0x0d22); 10472f036ac63ebfa3fc618a1f22324ef9297c5b7d05Andrew Victor } else if (machine_is_ecbat91()) 10482f036ac63ebfa3fc618a1f22324ef9297c5b7d05Andrew Victor write_phy(phy_address, MII_LEDCTRL_REG, 0x156A); 10492f036ac63ebfa3fc618a1f22324ef9297c5b7d05Andrew Victor 1050d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor disable_mdi(); 1051d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor spin_unlock_irq(&lp->lock); 1052d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 1053d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor lp->mii.dev = dev; /* Support for ethtool */ 1054d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor lp->mii.mdio_read = mdio_read; 1055d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor lp->mii.mdio_write = mdio_write; 1056ca5585ed248dc01ce918002ee9a9c9c41ae4f7c0Andrew Victor lp->mii.phy_id = phy_address; 1057ca5585ed248dc01ce918002ee9a9c9c41ae4f7c0Andrew Victor lp->mii.phy_id_mask = 0x1f; 1058ca5585ed248dc01ce918002ee9a9c9c41ae4f7c0Andrew Victor lp->mii.reg_num_mask = 0x1f; 1059d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 1060d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor lp->phy_type = phy_type; /* Type of PHY connected */ 1061d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor lp->phy_address = phy_address; /* MDI address of PHY */ 1062d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 1063d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor /* Register the network interface */ 1064d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor res = register_netdev(dev); 1065d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if (res) { 1066d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor free_irq(dev->irq, dev); 1067d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor free_netdev(dev); 1068d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys); 1069d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor return res; 1070d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } 1071d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 1072d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor /* Determine current link speed */ 1073d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor spin_lock_irq(&lp->lock); 1074d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor enable_mdi(); 1075775637df0caccc204628ebacca2b07f35c88b96bAndrew Victor update_linkspeed(dev, 0); 1076d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor disable_mdi(); 1077d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor spin_unlock_irq(&lp->lock); 1078d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor netif_carrier_off(dev); /* will be enabled in open() */ 1079d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 1080775637df0caccc204628ebacca2b07f35c88b96bAndrew Victor /* If board has no PHY IRQ, use a timer to poll the PHY */ 10812839038bb1a72ed7ef3c39521e0ca981c9cb1534Nicolas Ferre if (!gpio_is_valid(lp->board_data.phy_irq_pin)) { 1082cf42553ab43e102bc98eca05523d2390a1eedde9Andrew Victor init_timer(&lp->check_timer); 1083cf42553ab43e102bc98eca05523d2390a1eedde9Andrew Victor lp->check_timer.data = (unsigned long)dev; 1084cf42553ab43e102bc98eca05523d2390a1eedde9Andrew Victor lp->check_timer.function = at91ether_check_link; 108571527ef484426f2a4fb868da379b46f4408e80d6David Brownell } else if (lp->board_data.phy_irq_pin >= 32) 108671527ef484426f2a4fb868da379b46f4408e80d6David Brownell gpio_request(lp->board_data.phy_irq_pin, "ethernet_phy"); 1087775637df0caccc204628ebacca2b07f35c88b96bAndrew Victor 1088d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor /* Display ethernet banner */ 1089e174961ca1a0b28f7abf0be47973ad57cb74e5f0Johannes Berg printk(KERN_INFO "%s: AT91 ethernet at 0x%08x int=%d %s%s (%pM)\n", 10900795af5729b18218767fab27c44b1384f72dc9adJoe Perches dev->name, (uint) dev->base_addr, dev->irq, 10910795af5729b18218767fab27c44b1384f72dc9adJoe Perches at91_emac_read(AT91_EMAC_CFG) & AT91_EMAC_SPD ? "100-" : "10-", 10920795af5729b18218767fab27c44b1384f72dc9adJoe Perches at91_emac_read(AT91_EMAC_CFG) & AT91_EMAC_FD ? "FullDuplex" : "HalfDuplex", 1093e174961ca1a0b28f7abf0be47973ad57cb74e5f0Johannes Berg dev->dev_addr); 1094d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor if ((phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) 1095427d269f17fd02d192e9ae3bd93bdc07790fa02cAndrew Victor printk(KERN_INFO "%s: Davicom 9161 PHY %s\n", dev->name, (lp->phy_media == PORT_FIBRE) ? "(Fiber)" : "(Copper)"); 1096d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor else if (phy_type == MII_LXT971A_ID) 1097d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor printk(KERN_INFO "%s: Intel LXT971A PHY\n", dev->name); 1098d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor else if (phy_type == MII_RTL8201_ID) 1099d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor printk(KERN_INFO "%s: Realtek RTL8201(B)L PHY\n", dev->name); 1100d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor else if (phy_type == MII_BCM5221_ID) 1101d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor printk(KERN_INFO "%s: Broadcom BCM5221 PHY\n", dev->name); 1102d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor else if (phy_type == MII_DP83847_ID) 1103d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor printk(KERN_INFO "%s: National Semiconductor DP83847 PHY\n", dev->name); 11046b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor else if (phy_type == MII_DP83848_ID) 11056b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor printk(KERN_INFO "%s: National Semiconductor DP83848 PHY\n", dev->name); 1106d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor else if (phy_type == MII_AC101L_ID) 1107d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor printk(KERN_INFO "%s: Altima AC101L PHY\n", dev->name); 1108d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor else if (phy_type == MII_KS8721_ID) 1109d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor printk(KERN_INFO "%s: Micrel KS8721 PHY\n", dev->name); 11106b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor else if (phy_type == MII_T78Q21x3_ID) 11116b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor printk(KERN_INFO "%s: Teridian 78Q21x3 PHY\n", dev->name); 11126b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor else if (phy_type == MII_LAN83C185_ID) 11136b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor printk(KERN_INFO "%s: SMSC LAN83C185 PHY\n", dev->name); 1114d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 1115d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor return 0; 1116d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor} 1117d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 1118d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* 1119d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * Detect MAC and PHY and perform initialization 1120d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor */ 1121d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victorstatic int __init at91ether_probe(struct platform_device *pdev) 1122d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor{ 1123d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor unsigned int phyid1, phyid2; 1124d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor int detected = -1; 1125d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor unsigned long phy_id; 1126d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor unsigned short phy_address = 0; 1127427d269f17fd02d192e9ae3bd93bdc07790fa02cAndrew Victor struct clk *ether_clk; 1128d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 1129d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor ether_clk = clk_get(&pdev->dev, "ether_clk"); 1130427d269f17fd02d192e9ae3bd93bdc07790fa02cAndrew Victor if (IS_ERR(ether_clk)) { 1131d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor printk(KERN_ERR "at91_ether: no clock defined\n"); 1132d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor return -ENODEV; 1133d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } 1134d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor clk_enable(ether_clk); /* Enable Peripheral clock */ 1135d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 1136d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor while ((detected != 0) && (phy_address < 32)) { 1137d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor /* Read the PHY ID registers */ 1138d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor enable_mdi(); 1139d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor read_phy(phy_address, MII_PHYSID1, &phyid1); 1140d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor read_phy(phy_address, MII_PHYSID2, &phyid2); 1141d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor disable_mdi(); 1142d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 1143d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor phy_id = (phyid1 << 16) | (phyid2 & 0xfff0); 1144d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor switch (phy_id) { 1145d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor case MII_DM9161_ID: /* Davicom 9161: PHY_ID1 = 0x181, PHY_ID2 = B881 */ 1146d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor case MII_DM9161A_ID: /* Davicom 9161A: PHY_ID1 = 0x181, PHY_ID2 = B8A0 */ 1147d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor case MII_LXT971A_ID: /* Intel LXT971A: PHY_ID1 = 0x13, PHY_ID2 = 78E0 */ 1148d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor case MII_RTL8201_ID: /* Realtek RTL8201: PHY_ID1 = 0, PHY_ID2 = 0x8201 */ 1149d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor case MII_BCM5221_ID: /* Broadcom BCM5221: PHY_ID1 = 0x40, PHY_ID2 = 0x61e0 */ 1150d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor case MII_DP83847_ID: /* National Semiconductor DP83847: */ 11516b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor case MII_DP83848_ID: /* National Semiconductor DP83848: */ 1152d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor case MII_AC101L_ID: /* Altima AC101L: PHY_ID1 = 0x22, PHY_ID2 = 0x5520 */ 1153d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor case MII_KS8721_ID: /* Micrel KS8721: PHY_ID1 = 0x22, PHY_ID2 = 0x1610 */ 11546b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor case MII_T78Q21x3_ID: /* Teridian 78Q21x3: PHY_ID1 = 0x0E, PHY_ID2 = 7237 */ 11556b4aea7352bed6e2fdb59a3fe24ce2b42b31c35aAndrew Victor case MII_LAN83C185_ID: /* SMSC LAN83C185: PHY_ID1 = 0x0007, PHY_ID2 = 0xC0A1 */ 1156427d269f17fd02d192e9ae3bd93bdc07790fa02cAndrew Victor detected = at91ether_setup(phy_id, phy_address, pdev, ether_clk); 1157d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor break; 1158d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } 1159d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 1160d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor phy_address++; 1161d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor } 1162d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 1163d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor clk_disable(ether_clk); /* Disable Peripheral clock */ 1164d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 1165d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor return detected; 1166d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor} 1167d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 1168d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victorstatic int __devexit at91ether_remove(struct platform_device *pdev) 1169d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor{ 1170c57ee096b6caf8f7e17abe46185d24f2b649b9f9Andrew Victor struct net_device *dev = platform_get_drvdata(pdev); 1171c57ee096b6caf8f7e17abe46185d24f2b649b9f9Andrew Victor struct at91_private *lp = netdev_priv(dev); 1172d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 11732839038bb1a72ed7ef3c39521e0ca981c9cb1534Nicolas Ferre if (gpio_is_valid(lp->board_data.phy_irq_pin) && 11742839038bb1a72ed7ef3c39521e0ca981c9cb1534Nicolas Ferre lp->board_data.phy_irq_pin >= 32) 117571527ef484426f2a4fb868da379b46f4408e80d6David Brownell gpio_free(lp->board_data.phy_irq_pin); 117671527ef484426f2a4fb868da379b46f4408e80d6David Brownell 1177c57ee096b6caf8f7e17abe46185d24f2b649b9f9Andrew Victor unregister_netdev(dev); 1178c57ee096b6caf8f7e17abe46185d24f2b649b9f9Andrew Victor free_irq(dev->irq, dev); 1179d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys); 1180427d269f17fd02d192e9ae3bd93bdc07790fa02cAndrew Victor clk_put(lp->ether_clk); 1181d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 1182c57ee096b6caf8f7e17abe46185d24f2b649b9f9Andrew Victor platform_set_drvdata(pdev, NULL); 1183c57ee096b6caf8f7e17abe46185d24f2b649b9f9Andrew Victor free_netdev(dev); 1184d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor return 0; 1185d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor} 1186d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 118700e5edcbfdb7030f6cbb8d5d89fdc2848133a182Andrew Victor#ifdef CONFIG_PM 118800e5edcbfdb7030f6cbb8d5d89fdc2848133a182Andrew Victor 118900e5edcbfdb7030f6cbb8d5d89fdc2848133a182Andrew Victorstatic int at91ether_suspend(struct platform_device *pdev, pm_message_t mesg) 119000e5edcbfdb7030f6cbb8d5d89fdc2848133a182Andrew Victor{ 119100e5edcbfdb7030f6cbb8d5d89fdc2848133a182Andrew Victor struct net_device *net_dev = platform_get_drvdata(pdev); 1192c57ee096b6caf8f7e17abe46185d24f2b649b9f9Andrew Victor struct at91_private *lp = netdev_priv(net_dev); 119300e5edcbfdb7030f6cbb8d5d89fdc2848133a182Andrew Victor 119400e5edcbfdb7030f6cbb8d5d89fdc2848133a182Andrew Victor if (netif_running(net_dev)) { 11952839038bb1a72ed7ef3c39521e0ca981c9cb1534Nicolas Ferre if (gpio_is_valid(lp->board_data.phy_irq_pin)) { 11962839038bb1a72ed7ef3c39521e0ca981c9cb1534Nicolas Ferre int phy_irq = lp->board_data.phy_irq_pin; 119700e5edcbfdb7030f6cbb8d5d89fdc2848133a182Andrew Victor disable_irq(phy_irq); 11982839038bb1a72ed7ef3c39521e0ca981c9cb1534Nicolas Ferre } 119900e5edcbfdb7030f6cbb8d5d89fdc2848133a182Andrew Victor 120000e5edcbfdb7030f6cbb8d5d89fdc2848133a182Andrew Victor netif_stop_queue(net_dev); 120100e5edcbfdb7030f6cbb8d5d89fdc2848133a182Andrew Victor netif_device_detach(net_dev); 120200e5edcbfdb7030f6cbb8d5d89fdc2848133a182Andrew Victor 120300e5edcbfdb7030f6cbb8d5d89fdc2848133a182Andrew Victor clk_disable(lp->ether_clk); 120400e5edcbfdb7030f6cbb8d5d89fdc2848133a182Andrew Victor } 120500e5edcbfdb7030f6cbb8d5d89fdc2848133a182Andrew Victor return 0; 120600e5edcbfdb7030f6cbb8d5d89fdc2848133a182Andrew Victor} 120700e5edcbfdb7030f6cbb8d5d89fdc2848133a182Andrew Victor 120800e5edcbfdb7030f6cbb8d5d89fdc2848133a182Andrew Victorstatic int at91ether_resume(struct platform_device *pdev) 120900e5edcbfdb7030f6cbb8d5d89fdc2848133a182Andrew Victor{ 121000e5edcbfdb7030f6cbb8d5d89fdc2848133a182Andrew Victor struct net_device *net_dev = platform_get_drvdata(pdev); 1211c57ee096b6caf8f7e17abe46185d24f2b649b9f9Andrew Victor struct at91_private *lp = netdev_priv(net_dev); 121200e5edcbfdb7030f6cbb8d5d89fdc2848133a182Andrew Victor 121300e5edcbfdb7030f6cbb8d5d89fdc2848133a182Andrew Victor if (netif_running(net_dev)) { 121400e5edcbfdb7030f6cbb8d5d89fdc2848133a182Andrew Victor clk_enable(lp->ether_clk); 121500e5edcbfdb7030f6cbb8d5d89fdc2848133a182Andrew Victor 121600e5edcbfdb7030f6cbb8d5d89fdc2848133a182Andrew Victor netif_device_attach(net_dev); 121700e5edcbfdb7030f6cbb8d5d89fdc2848133a182Andrew Victor netif_start_queue(net_dev); 121800e5edcbfdb7030f6cbb8d5d89fdc2848133a182Andrew Victor 12192839038bb1a72ed7ef3c39521e0ca981c9cb1534Nicolas Ferre if (gpio_is_valid(lp->board_data.phy_irq_pin)) { 12202839038bb1a72ed7ef3c39521e0ca981c9cb1534Nicolas Ferre int phy_irq = lp->board_data.phy_irq_pin; 122100e5edcbfdb7030f6cbb8d5d89fdc2848133a182Andrew Victor enable_irq(phy_irq); 12222839038bb1a72ed7ef3c39521e0ca981c9cb1534Nicolas Ferre } 122300e5edcbfdb7030f6cbb8d5d89fdc2848133a182Andrew Victor } 122400e5edcbfdb7030f6cbb8d5d89fdc2848133a182Andrew Victor return 0; 122500e5edcbfdb7030f6cbb8d5d89fdc2848133a182Andrew Victor} 122600e5edcbfdb7030f6cbb8d5d89fdc2848133a182Andrew Victor 122700e5edcbfdb7030f6cbb8d5d89fdc2848133a182Andrew Victor#else 122800e5edcbfdb7030f6cbb8d5d89fdc2848133a182Andrew Victor#define at91ether_suspend NULL 122900e5edcbfdb7030f6cbb8d5d89fdc2848133a182Andrew Victor#define at91ether_resume NULL 123000e5edcbfdb7030f6cbb8d5d89fdc2848133a182Andrew Victor#endif 123100e5edcbfdb7030f6cbb8d5d89fdc2848133a182Andrew Victor 1232d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victorstatic struct platform_driver at91ether_driver = { 1233d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor .remove = __devexit_p(at91ether_remove), 123400e5edcbfdb7030f6cbb8d5d89fdc2848133a182Andrew Victor .suspend = at91ether_suspend, 123500e5edcbfdb7030f6cbb8d5d89fdc2848133a182Andrew Victor .resume = at91ether_resume, 1236d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor .driver = { 1237d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor .name = DRV_NAME, 1238d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor .owner = THIS_MODULE, 1239d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor }, 1240d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor}; 1241d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 1242d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victorstatic int __init at91ether_init(void) 1243d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor{ 124478a9c9c97455d0f8d2d2098b2252eb4bf65be799Uwe Kleine-König return platform_driver_probe(&at91ether_driver, at91ether_probe); 1245d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor} 1246d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 1247d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victorstatic void __exit at91ether_exit(void) 1248d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor{ 1249d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor platform_driver_unregister(&at91ether_driver); 1250d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor} 1251d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 1252d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victormodule_init(at91ether_init) 1253d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victormodule_exit(at91ether_exit) 1254d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 1255d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew VictorMODULE_LICENSE("GPL"); 1256d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew VictorMODULE_DESCRIPTION("AT91RM9200 EMAC Ethernet driver"); 1257d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew VictorMODULE_AUTHOR("Andrew Victor"); 125872abb46101fb5c47a9592914adb221b430ff26bdKay SieversMODULE_ALIAS("platform:" DRV_NAME); 1259