at91_ether.c revision 9f2f381f813858755f5b6ef7af316feda0726ef3
1/* 2 * Ethernet driver for the Atmel AT91RM9200 (Thunder) 3 * 4 * Copyright (C) 2003 SAN People (Pty) Ltd 5 * 6 * Based on an earlier Atmel EMAC macrocell driver by Atmel and Lineo Inc. 7 * Initial version by Rick Bronson 01/11/2003 8 * 9 * Intel LXT971A PHY support by Christopher Bahns & David Knickerbocker 10 * (Polaroid Corporation) 11 * 12 * Realtek RTL8201(B)L PHY support by Roman Avramenko <roman@imsystems.ru> 13 * 14 * This program is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License 16 * as published by the Free Software Foundation; either version 17 * 2 of the License, or (at your option) any later version. 18 */ 19 20#include <linux/module.h> 21#include <linux/init.h> 22#include <linux/interrupt.h> 23#include <linux/mii.h> 24#include <linux/netdevice.h> 25#include <linux/etherdevice.h> 26#include <linux/skbuff.h> 27#include <linux/dma-mapping.h> 28#include <linux/ethtool.h> 29#include <linux/platform_device.h> 30#include <linux/clk.h> 31#include <linux/gfp.h> 32 33#include <asm/io.h> 34#include <asm/uaccess.h> 35#include <asm/mach-types.h> 36 37#include <mach/at91rm9200_emac.h> 38#include <mach/gpio.h> 39#include <mach/board.h> 40 41#include "at91_ether.h" 42 43#define DRV_NAME "at91_ether" 44#define DRV_VERSION "1.0" 45 46#define LINK_POLL_INTERVAL (HZ) 47 48/* ..................................................................... */ 49 50/* 51 * Read from a EMAC register. 52 */ 53static inline unsigned long at91_emac_read(unsigned int reg) 54{ 55 void __iomem *emac_base = (void __iomem *)AT91_VA_BASE_EMAC; 56 57 return __raw_readl(emac_base + reg); 58} 59 60/* 61 * Write to a EMAC register. 62 */ 63static inline void at91_emac_write(unsigned int reg, unsigned long value) 64{ 65 void __iomem *emac_base = (void __iomem *)AT91_VA_BASE_EMAC; 66 67 __raw_writel(value, emac_base + reg); 68} 69 70/* ........................... PHY INTERFACE ........................... */ 71 72/* 73 * Enable the MDIO bit in MAC control register 74 * When not called from an interrupt-handler, access to the PHY must be 75 * protected by a spinlock. 76 */ 77static void enable_mdi(void) 78{ 79 unsigned long ctl; 80 81 ctl = at91_emac_read(AT91_EMAC_CTL); 82 at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_MPE); /* enable management port */ 83} 84 85/* 86 * Disable the MDIO bit in the MAC control register 87 */ 88static void disable_mdi(void) 89{ 90 unsigned long ctl; 91 92 ctl = at91_emac_read(AT91_EMAC_CTL); 93 at91_emac_write(AT91_EMAC_CTL, ctl & ~AT91_EMAC_MPE); /* disable management port */ 94} 95 96/* 97 * Wait until the PHY operation is complete. 98 */ 99static inline void at91_phy_wait(void) { 100 unsigned long timeout = jiffies + 2; 101 102 while (!(at91_emac_read(AT91_EMAC_SR) & AT91_EMAC_SR_IDLE)) { 103 if (time_after(jiffies, timeout)) { 104 printk("at91_ether: MIO timeout\n"); 105 break; 106 } 107 cpu_relax(); 108 } 109} 110 111/* 112 * Write value to the a PHY register 113 * Note: MDI interface is assumed to already have been enabled. 114 */ 115static void write_phy(unsigned char phy_addr, unsigned char address, unsigned int value) 116{ 117 at91_emac_write(AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_W 118 | ((phy_addr & 0x1f) << 23) | (address << 18) | (value & AT91_EMAC_DATA)); 119 120 /* Wait until IDLE bit in Network Status register is cleared */ 121 at91_phy_wait(); 122} 123 124/* 125 * Read value stored in a PHY register. 126 * Note: MDI interface is assumed to already have been enabled. 127 */ 128static void read_phy(unsigned char phy_addr, unsigned char address, unsigned int *value) 129{ 130 at91_emac_write(AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_R 131 | ((phy_addr & 0x1f) << 23) | (address << 18)); 132 133 /* Wait until IDLE bit in Network Status register is cleared */ 134 at91_phy_wait(); 135 136 *value = at91_emac_read(AT91_EMAC_MAN) & AT91_EMAC_DATA; 137} 138 139/* ........................... PHY MANAGEMENT .......................... */ 140 141/* 142 * Access the PHY to determine the current link speed and mode, and update the 143 * MAC accordingly. 144 * If no link or auto-negotiation is busy, then no changes are made. 145 */ 146static void update_linkspeed(struct net_device *dev, int silent) 147{ 148 struct at91_private *lp = netdev_priv(dev); 149 unsigned int bmsr, bmcr, lpa, mac_cfg; 150 unsigned int speed, duplex; 151 152 if (!mii_link_ok(&lp->mii)) { /* no link */ 153 netif_carrier_off(dev); 154 if (!silent) 155 printk(KERN_INFO "%s: Link down.\n", dev->name); 156 return; 157 } 158 159 /* Link up, or auto-negotiation still in progress */ 160 read_phy(lp->phy_address, MII_BMSR, &bmsr); 161 read_phy(lp->phy_address, MII_BMCR, &bmcr); 162 if (bmcr & BMCR_ANENABLE) { /* AutoNegotiation is enabled */ 163 if (!(bmsr & BMSR_ANEGCOMPLETE)) 164 return; /* Do nothing - another interrupt generated when negotiation complete */ 165 166 read_phy(lp->phy_address, MII_LPA, &lpa); 167 if ((lpa & LPA_100FULL) || (lpa & LPA_100HALF)) speed = SPEED_100; 168 else speed = SPEED_10; 169 if ((lpa & LPA_100FULL) || (lpa & LPA_10FULL)) duplex = DUPLEX_FULL; 170 else duplex = DUPLEX_HALF; 171 } else { 172 speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10; 173 duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF; 174 } 175 176 /* Update the MAC */ 177 mac_cfg = at91_emac_read(AT91_EMAC_CFG) & ~(AT91_EMAC_SPD | AT91_EMAC_FD); 178 if (speed == SPEED_100) { 179 if (duplex == DUPLEX_FULL) /* 100 Full Duplex */ 180 mac_cfg |= AT91_EMAC_SPD | AT91_EMAC_FD; 181 else /* 100 Half Duplex */ 182 mac_cfg |= AT91_EMAC_SPD; 183 } else { 184 if (duplex == DUPLEX_FULL) /* 10 Full Duplex */ 185 mac_cfg |= AT91_EMAC_FD; 186 else {} /* 10 Half Duplex */ 187 } 188 at91_emac_write(AT91_EMAC_CFG, mac_cfg); 189 190 if (!silent) 191 printk(KERN_INFO "%s: Link now %i-%s\n", dev->name, speed, (duplex == DUPLEX_FULL) ? "FullDuplex" : "HalfDuplex"); 192 netif_carrier_on(dev); 193} 194 195/* 196 * Handle interrupts from the PHY 197 */ 198static irqreturn_t at91ether_phy_interrupt(int irq, void *dev_id) 199{ 200 struct net_device *dev = (struct net_device *) dev_id; 201 struct at91_private *lp = netdev_priv(dev); 202 unsigned int phy; 203 204 /* 205 * This hander is triggered on both edges, but the PHY chips expect 206 * level-triggering. We therefore have to check if the PHY actually has 207 * an IRQ pending. 208 */ 209 enable_mdi(); 210 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { 211 read_phy(lp->phy_address, MII_DSINTR_REG, &phy); /* ack interrupt in Davicom PHY */ 212 if (!(phy & (1 << 0))) 213 goto done; 214 } 215 else if (lp->phy_type == MII_LXT971A_ID) { 216 read_phy(lp->phy_address, MII_ISINTS_REG, &phy); /* ack interrupt in Intel PHY */ 217 if (!(phy & (1 << 2))) 218 goto done; 219 } 220 else if (lp->phy_type == MII_BCM5221_ID) { 221 read_phy(lp->phy_address, MII_BCMINTR_REG, &phy); /* ack interrupt in Broadcom PHY */ 222 if (!(phy & (1 << 0))) 223 goto done; 224 } 225 else if (lp->phy_type == MII_KS8721_ID) { 226 read_phy(lp->phy_address, MII_TPISTATUS, &phy); /* ack interrupt in Micrel PHY */ 227 if (!(phy & ((1 << 2) | 1))) 228 goto done; 229 } 230 else if (lp->phy_type == MII_T78Q21x3_ID) { /* ack interrupt in Teridian PHY */ 231 read_phy(lp->phy_address, MII_T78Q21INT_REG, &phy); 232 if (!(phy & ((1 << 2) | 1))) 233 goto done; 234 } 235 else if (lp->phy_type == MII_DP83848_ID) { 236 read_phy(lp->phy_address, MII_DPPHYSTS_REG, &phy); /* ack interrupt in DP83848 PHY */ 237 if (!(phy & (1 << 7))) 238 goto done; 239 } 240 241 update_linkspeed(dev, 0); 242 243done: 244 disable_mdi(); 245 246 return IRQ_HANDLED; 247} 248 249/* 250 * Initialize and enable the PHY interrupt for link-state changes 251 */ 252static void enable_phyirq(struct net_device *dev) 253{ 254 struct at91_private *lp = netdev_priv(dev); 255 unsigned int dsintr, irq_number; 256 int status; 257 258 irq_number = lp->board_data.phy_irq_pin; 259 if (!irq_number) { 260 /* 261 * PHY doesn't have an IRQ pin (RTL8201, DP83847, AC101L), 262 * or board does not have it connected. 263 */ 264 mod_timer(&lp->check_timer, jiffies + LINK_POLL_INTERVAL); 265 return; 266 } 267 268 status = request_irq(irq_number, at91ether_phy_interrupt, 0, dev->name, dev); 269 if (status) { 270 printk(KERN_ERR "at91_ether: PHY IRQ %d request failed - status %d!\n", irq_number, status); 271 return; 272 } 273 274 spin_lock_irq(&lp->lock); 275 enable_mdi(); 276 277 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */ 278 read_phy(lp->phy_address, MII_DSINTR_REG, &dsintr); 279 dsintr = dsintr & ~0xf00; /* clear bits 8..11 */ 280 write_phy(lp->phy_address, MII_DSINTR_REG, dsintr); 281 } 282 else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */ 283 read_phy(lp->phy_address, MII_ISINTE_REG, &dsintr); 284 dsintr = dsintr | 0xf2; /* set bits 1, 4..7 */ 285 write_phy(lp->phy_address, MII_ISINTE_REG, dsintr); 286 } 287 else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */ 288 dsintr = (1 << 15) | ( 1 << 14); 289 write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr); 290 } 291 else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */ 292 dsintr = (1 << 10) | ( 1 << 8); 293 write_phy(lp->phy_address, MII_TPISTATUS, dsintr); 294 } 295 else if (lp->phy_type == MII_T78Q21x3_ID) { /* for Teridian PHY */ 296 read_phy(lp->phy_address, MII_T78Q21INT_REG, &dsintr); 297 dsintr = dsintr | 0x500; /* set bits 8, 10 */ 298 write_phy(lp->phy_address, MII_T78Q21INT_REG, dsintr); 299 } 300 else if (lp->phy_type == MII_DP83848_ID) { /* National Semiconductor DP83848 PHY */ 301 read_phy(lp->phy_address, MII_DPMISR_REG, &dsintr); 302 dsintr = dsintr | 0x3c; /* set bits 2..5 */ 303 write_phy(lp->phy_address, MII_DPMISR_REG, dsintr); 304 read_phy(lp->phy_address, MII_DPMICR_REG, &dsintr); 305 dsintr = dsintr | 0x3; /* set bits 0,1 */ 306 write_phy(lp->phy_address, MII_DPMICR_REG, dsintr); 307 } 308 309 disable_mdi(); 310 spin_unlock_irq(&lp->lock); 311} 312 313/* 314 * Disable the PHY interrupt 315 */ 316static void disable_phyirq(struct net_device *dev) 317{ 318 struct at91_private *lp = netdev_priv(dev); 319 unsigned int dsintr; 320 unsigned int irq_number; 321 322 irq_number = lp->board_data.phy_irq_pin; 323 if (!irq_number) { 324 del_timer_sync(&lp->check_timer); 325 return; 326 } 327 328 spin_lock_irq(&lp->lock); 329 enable_mdi(); 330 331 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */ 332 read_phy(lp->phy_address, MII_DSINTR_REG, &dsintr); 333 dsintr = dsintr | 0xf00; /* set bits 8..11 */ 334 write_phy(lp->phy_address, MII_DSINTR_REG, dsintr); 335 } 336 else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */ 337 read_phy(lp->phy_address, MII_ISINTE_REG, &dsintr); 338 dsintr = dsintr & ~0xf2; /* clear bits 1, 4..7 */ 339 write_phy(lp->phy_address, MII_ISINTE_REG, dsintr); 340 } 341 else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */ 342 read_phy(lp->phy_address, MII_BCMINTR_REG, &dsintr); 343 dsintr = ~(1 << 14); 344 write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr); 345 } 346 else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */ 347 read_phy(lp->phy_address, MII_TPISTATUS, &dsintr); 348 dsintr = ~((1 << 10) | (1 << 8)); 349 write_phy(lp->phy_address, MII_TPISTATUS, dsintr); 350 } 351 else if (lp->phy_type == MII_T78Q21x3_ID) { /* for Teridian PHY */ 352 read_phy(lp->phy_address, MII_T78Q21INT_REG, &dsintr); 353 dsintr = dsintr & ~0x500; /* clear bits 8, 10 */ 354 write_phy(lp->phy_address, MII_T78Q21INT_REG, dsintr); 355 } 356 else if (lp->phy_type == MII_DP83848_ID) { /* National Semiconductor DP83848 PHY */ 357 read_phy(lp->phy_address, MII_DPMICR_REG, &dsintr); 358 dsintr = dsintr & ~0x3; /* clear bits 0, 1 */ 359 write_phy(lp->phy_address, MII_DPMICR_REG, dsintr); 360 read_phy(lp->phy_address, MII_DPMISR_REG, &dsintr); 361 dsintr = dsintr & ~0x3c; /* clear bits 2..5 */ 362 write_phy(lp->phy_address, MII_DPMISR_REG, dsintr); 363 } 364 365 disable_mdi(); 366 spin_unlock_irq(&lp->lock); 367 368 free_irq(irq_number, dev); /* Free interrupt handler */ 369} 370 371/* 372 * Perform a software reset of the PHY. 373 */ 374#if 0 375static void reset_phy(struct net_device *dev) 376{ 377 struct at91_private *lp = netdev_priv(dev); 378 unsigned int bmcr; 379 380 spin_lock_irq(&lp->lock); 381 enable_mdi(); 382 383 /* Perform PHY reset */ 384 write_phy(lp->phy_address, MII_BMCR, BMCR_RESET); 385 386 /* Wait until PHY reset is complete */ 387 do { 388 read_phy(lp->phy_address, MII_BMCR, &bmcr); 389 } while (!(bmcr & BMCR_RESET)); 390 391 disable_mdi(); 392 spin_unlock_irq(&lp->lock); 393} 394#endif 395 396static void at91ether_check_link(unsigned long dev_id) 397{ 398 struct net_device *dev = (struct net_device *) dev_id; 399 struct at91_private *lp = netdev_priv(dev); 400 401 enable_mdi(); 402 update_linkspeed(dev, 1); 403 disable_mdi(); 404 405 mod_timer(&lp->check_timer, jiffies + LINK_POLL_INTERVAL); 406} 407 408/* ......................... ADDRESS MANAGEMENT ........................ */ 409 410/* 411 * NOTE: Your bootloader must always set the MAC address correctly before 412 * booting into Linux. 413 * 414 * - It must always set the MAC address after reset, even if it doesn't 415 * happen to access the Ethernet while it's booting. Some versions of 416 * U-Boot on the AT91RM9200-DK do not do this. 417 * 418 * - Likewise it must store the addresses in the correct byte order. 419 * MicroMonitor (uMon) on the CSB337 does this incorrectly (and 420 * continues to do so, for bug-compatibility). 421 */ 422 423static short __init unpack_mac_address(struct net_device *dev, unsigned int hi, unsigned int lo) 424{ 425 char addr[6]; 426 427 if (machine_is_csb337()) { 428 addr[5] = (lo & 0xff); /* The CSB337 bootloader stores the MAC the wrong-way around */ 429 addr[4] = (lo & 0xff00) >> 8; 430 addr[3] = (lo & 0xff0000) >> 16; 431 addr[2] = (lo & 0xff000000) >> 24; 432 addr[1] = (hi & 0xff); 433 addr[0] = (hi & 0xff00) >> 8; 434 } 435 else { 436 addr[0] = (lo & 0xff); 437 addr[1] = (lo & 0xff00) >> 8; 438 addr[2] = (lo & 0xff0000) >> 16; 439 addr[3] = (lo & 0xff000000) >> 24; 440 addr[4] = (hi & 0xff); 441 addr[5] = (hi & 0xff00) >> 8; 442 } 443 444 if (is_valid_ether_addr(addr)) { 445 memcpy(dev->dev_addr, &addr, 6); 446 return 1; 447 } 448 return 0; 449} 450 451/* 452 * Set the ethernet MAC address in dev->dev_addr 453 */ 454static void __init get_mac_address(struct net_device *dev) 455{ 456 /* Check Specific-Address 1 */ 457 if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA1H), at91_emac_read(AT91_EMAC_SA1L))) 458 return; 459 /* Check Specific-Address 2 */ 460 if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA2H), at91_emac_read(AT91_EMAC_SA2L))) 461 return; 462 /* Check Specific-Address 3 */ 463 if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA3H), at91_emac_read(AT91_EMAC_SA3L))) 464 return; 465 /* Check Specific-Address 4 */ 466 if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA4H), at91_emac_read(AT91_EMAC_SA4L))) 467 return; 468 469 printk(KERN_ERR "at91_ether: Your bootloader did not configure a MAC address.\n"); 470} 471 472/* 473 * Program the hardware MAC address from dev->dev_addr. 474 */ 475static void update_mac_address(struct net_device *dev) 476{ 477 at91_emac_write(AT91_EMAC_SA1L, (dev->dev_addr[3] << 24) | (dev->dev_addr[2] << 16) | (dev->dev_addr[1] << 8) | (dev->dev_addr[0])); 478 at91_emac_write(AT91_EMAC_SA1H, (dev->dev_addr[5] << 8) | (dev->dev_addr[4])); 479 480 at91_emac_write(AT91_EMAC_SA2L, 0); 481 at91_emac_write(AT91_EMAC_SA2H, 0); 482} 483 484/* 485 * Store the new hardware address in dev->dev_addr, and update the MAC. 486 */ 487static int set_mac_address(struct net_device *dev, void* addr) 488{ 489 struct sockaddr *address = addr; 490 491 if (!is_valid_ether_addr(address->sa_data)) 492 return -EADDRNOTAVAIL; 493 494 memcpy(dev->dev_addr, address->sa_data, dev->addr_len); 495 update_mac_address(dev); 496 497 printk("%s: Setting MAC address to %pM\n", dev->name, 498 dev->dev_addr); 499 500 return 0; 501} 502 503static int inline hash_bit_value(int bitnr, __u8 *addr) 504{ 505 if (addr[bitnr / 8] & (1 << (bitnr % 8))) 506 return 1; 507 return 0; 508} 509 510/* 511 * The hash address register is 64 bits long and takes up two locations in the memory map. 512 * The least significant bits are stored in EMAC_HSL and the most significant 513 * bits in EMAC_HSH. 514 * 515 * The unicast hash enable and the multicast hash enable bits in the network configuration 516 * register enable the reception of hash matched frames. The destination address is 517 * reduced to a 6 bit index into the 64 bit hash register using the following hash function. 518 * The hash function is an exclusive or of every sixth bit of the destination address. 519 * hash_index[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47] 520 * hash_index[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46] 521 * hash_index[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45] 522 * hash_index[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44] 523 * hash_index[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43] 524 * hash_index[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42] 525 * da[0] represents the least significant bit of the first byte received, that is, the multicast/ 526 * unicast indicator, and da[47] represents the most significant bit of the last byte 527 * received. 528 * If the hash index points to a bit that is set in the hash register then the frame will be 529 * matched according to whether the frame is multicast or unicast. 530 * A multicast match will be signalled if the multicast hash enable bit is set, da[0] is 1 and 531 * the hash index points to a bit set in the hash register. 532 * A unicast match will be signalled if the unicast hash enable bit is set, da[0] is 0 and the 533 * hash index points to a bit set in the hash register. 534 * To receive all multicast frames, the hash register should be set with all ones and the 535 * multicast hash enable bit should be set in the network configuration register. 536 */ 537 538/* 539 * Return the hash index value for the specified address. 540 */ 541static int hash_get_index(__u8 *addr) 542{ 543 int i, j, bitval; 544 int hash_index = 0; 545 546 for (j = 0; j < 6; j++) { 547 for (i = 0, bitval = 0; i < 8; i++) 548 bitval ^= hash_bit_value(i*6 + j, addr); 549 550 hash_index |= (bitval << j); 551 } 552 553 return hash_index; 554} 555 556/* 557 * Add multicast addresses to the internal multicast-hash table. 558 */ 559static void at91ether_sethashtable(struct net_device *dev) 560{ 561 struct netdev_hw_addr *ha; 562 unsigned long mc_filter[2]; 563 unsigned int bitnr; 564 565 mc_filter[0] = mc_filter[1] = 0; 566 567 netdev_for_each_mc_addr(ha, dev) { 568 bitnr = hash_get_index(ha->addr); 569 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31); 570 } 571 572 at91_emac_write(AT91_EMAC_HSL, mc_filter[0]); 573 at91_emac_write(AT91_EMAC_HSH, mc_filter[1]); 574} 575 576/* 577 * Enable/Disable promiscuous and multicast modes. 578 */ 579static void at91ether_set_multicast_list(struct net_device *dev) 580{ 581 unsigned long cfg; 582 583 cfg = at91_emac_read(AT91_EMAC_CFG); 584 585 if (dev->flags & IFF_PROMISC) /* Enable promiscuous mode */ 586 cfg |= AT91_EMAC_CAF; 587 else if (dev->flags & (~IFF_PROMISC)) /* Disable promiscuous mode */ 588 cfg &= ~AT91_EMAC_CAF; 589 590 if (dev->flags & IFF_ALLMULTI) { /* Enable all multicast mode */ 591 at91_emac_write(AT91_EMAC_HSH, -1); 592 at91_emac_write(AT91_EMAC_HSL, -1); 593 cfg |= AT91_EMAC_MTI; 594 } else if (!netdev_mc_empty(dev)) { /* Enable specific multicasts */ 595 at91ether_sethashtable(dev); 596 cfg |= AT91_EMAC_MTI; 597 } else if (dev->flags & (~IFF_ALLMULTI)) { /* Disable all multicast mode */ 598 at91_emac_write(AT91_EMAC_HSH, 0); 599 at91_emac_write(AT91_EMAC_HSL, 0); 600 cfg &= ~AT91_EMAC_MTI; 601 } 602 603 at91_emac_write(AT91_EMAC_CFG, cfg); 604} 605 606/* ......................... ETHTOOL SUPPORT ........................... */ 607 608static int mdio_read(struct net_device *dev, int phy_id, int location) 609{ 610 unsigned int value; 611 612 read_phy(phy_id, location, &value); 613 return value; 614} 615 616static void mdio_write(struct net_device *dev, int phy_id, int location, int value) 617{ 618 write_phy(phy_id, location, value); 619} 620 621static int at91ether_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 622{ 623 struct at91_private *lp = netdev_priv(dev); 624 int ret; 625 626 spin_lock_irq(&lp->lock); 627 enable_mdi(); 628 629 ret = mii_ethtool_gset(&lp->mii, cmd); 630 631 disable_mdi(); 632 spin_unlock_irq(&lp->lock); 633 634 if (lp->phy_media == PORT_FIBRE) { /* override media type since mii.c doesn't know */ 635 cmd->supported = SUPPORTED_FIBRE; 636 cmd->port = PORT_FIBRE; 637 } 638 639 return ret; 640} 641 642static int at91ether_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 643{ 644 struct at91_private *lp = netdev_priv(dev); 645 int ret; 646 647 spin_lock_irq(&lp->lock); 648 enable_mdi(); 649 650 ret = mii_ethtool_sset(&lp->mii, cmd); 651 652 disable_mdi(); 653 spin_unlock_irq(&lp->lock); 654 655 return ret; 656} 657 658static int at91ether_nwayreset(struct net_device *dev) 659{ 660 struct at91_private *lp = netdev_priv(dev); 661 int ret; 662 663 spin_lock_irq(&lp->lock); 664 enable_mdi(); 665 666 ret = mii_nway_restart(&lp->mii); 667 668 disable_mdi(); 669 spin_unlock_irq(&lp->lock); 670 671 return ret; 672} 673 674static void at91ether_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 675{ 676 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 677 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 678 strlcpy(info->bus_info, dev_name(dev->dev.parent), sizeof(info->bus_info)); 679} 680 681static const struct ethtool_ops at91ether_ethtool_ops = { 682 .get_settings = at91ether_get_settings, 683 .set_settings = at91ether_set_settings, 684 .get_drvinfo = at91ether_get_drvinfo, 685 .nway_reset = at91ether_nwayreset, 686 .get_link = ethtool_op_get_link, 687}; 688 689static int at91ether_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 690{ 691 struct at91_private *lp = netdev_priv(dev); 692 int res; 693 694 if (!netif_running(dev)) 695 return -EINVAL; 696 697 spin_lock_irq(&lp->lock); 698 enable_mdi(); 699 res = generic_mii_ioctl(&lp->mii, if_mii(rq), cmd, NULL); 700 disable_mdi(); 701 spin_unlock_irq(&lp->lock); 702 703 return res; 704} 705 706/* ................................ MAC ................................ */ 707 708/* 709 * Initialize and start the Receiver and Transmit subsystems 710 */ 711static void at91ether_start(struct net_device *dev) 712{ 713 struct at91_private *lp = netdev_priv(dev); 714 struct recv_desc_bufs *dlist, *dlist_phys; 715 int i; 716 unsigned long ctl; 717 718 dlist = lp->dlist; 719 dlist_phys = lp->dlist_phys; 720 721 for (i = 0; i < MAX_RX_DESCR; i++) { 722 dlist->descriptors[i].addr = (unsigned int) &dlist_phys->recv_buf[i][0]; 723 dlist->descriptors[i].size = 0; 724 } 725 726 /* Set the Wrap bit on the last descriptor */ 727 dlist->descriptors[i-1].addr |= EMAC_DESC_WRAP; 728 729 /* Reset buffer index */ 730 lp->rxBuffIndex = 0; 731 732 /* Program address of descriptor list in Rx Buffer Queue register */ 733 at91_emac_write(AT91_EMAC_RBQP, (unsigned long) dlist_phys); 734 735 /* Enable Receive and Transmit */ 736 ctl = at91_emac_read(AT91_EMAC_CTL); 737 at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_RE | AT91_EMAC_TE); 738} 739 740/* 741 * Open the ethernet interface 742 */ 743static int at91ether_open(struct net_device *dev) 744{ 745 struct at91_private *lp = netdev_priv(dev); 746 unsigned long ctl; 747 748 if (!is_valid_ether_addr(dev->dev_addr)) 749 return -EADDRNOTAVAIL; 750 751 clk_enable(lp->ether_clk); /* Re-enable Peripheral clock */ 752 753 /* Clear internal statistics */ 754 ctl = at91_emac_read(AT91_EMAC_CTL); 755 at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_CSR); 756 757 /* Update the MAC address (incase user has changed it) */ 758 update_mac_address(dev); 759 760 /* Enable PHY interrupt */ 761 enable_phyirq(dev); 762 763 /* Enable MAC interrupts */ 764 at91_emac_write(AT91_EMAC_IER, AT91_EMAC_RCOM | AT91_EMAC_RBNA 765 | AT91_EMAC_TUND | AT91_EMAC_RTRY | AT91_EMAC_TCOM 766 | AT91_EMAC_ROVR | AT91_EMAC_ABT); 767 768 /* Determine current link speed */ 769 spin_lock_irq(&lp->lock); 770 enable_mdi(); 771 update_linkspeed(dev, 0); 772 disable_mdi(); 773 spin_unlock_irq(&lp->lock); 774 775 at91ether_start(dev); 776 netif_start_queue(dev); 777 return 0; 778} 779 780/* 781 * Close the interface 782 */ 783static int at91ether_close(struct net_device *dev) 784{ 785 struct at91_private *lp = netdev_priv(dev); 786 unsigned long ctl; 787 788 /* Disable Receiver and Transmitter */ 789 ctl = at91_emac_read(AT91_EMAC_CTL); 790 at91_emac_write(AT91_EMAC_CTL, ctl & ~(AT91_EMAC_TE | AT91_EMAC_RE)); 791 792 /* Disable PHY interrupt */ 793 disable_phyirq(dev); 794 795 /* Disable MAC interrupts */ 796 at91_emac_write(AT91_EMAC_IDR, AT91_EMAC_RCOM | AT91_EMAC_RBNA 797 | AT91_EMAC_TUND | AT91_EMAC_RTRY | AT91_EMAC_TCOM 798 | AT91_EMAC_ROVR | AT91_EMAC_ABT); 799 800 netif_stop_queue(dev); 801 802 clk_disable(lp->ether_clk); /* Disable Peripheral clock */ 803 804 return 0; 805} 806 807/* 808 * Transmit packet. 809 */ 810static int at91ether_start_xmit(struct sk_buff *skb, struct net_device *dev) 811{ 812 struct at91_private *lp = netdev_priv(dev); 813 814 if (at91_emac_read(AT91_EMAC_TSR) & AT91_EMAC_TSR_BNQ) { 815 netif_stop_queue(dev); 816 817 /* Store packet information (to free when Tx completed) */ 818 lp->skb = skb; 819 lp->skb_length = skb->len; 820 lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE); 821 dev->stats.tx_bytes += skb->len; 822 823 /* Set address of the data in the Transmit Address register */ 824 at91_emac_write(AT91_EMAC_TAR, lp->skb_physaddr); 825 /* Set length of the packet in the Transmit Control register */ 826 at91_emac_write(AT91_EMAC_TCR, skb->len); 827 828 } else { 829 printk(KERN_ERR "at91_ether.c: at91ether_start_xmit() called, but device is busy!\n"); 830 return NETDEV_TX_BUSY; /* if we return anything but zero, dev.c:1055 calls kfree_skb(skb) 831 on this skb, he also reports -ENETDOWN and printk's, so either 832 we free and return(0) or don't free and return 1 */ 833 } 834 835 return NETDEV_TX_OK; 836} 837 838/* 839 * Update the current statistics from the internal statistics registers. 840 */ 841static struct net_device_stats *at91ether_stats(struct net_device *dev) 842{ 843 int ale, lenerr, seqe, lcol, ecol; 844 845 if (netif_running(dev)) { 846 dev->stats.rx_packets += at91_emac_read(AT91_EMAC_OK); /* Good frames received */ 847 ale = at91_emac_read(AT91_EMAC_ALE); 848 dev->stats.rx_frame_errors += ale; /* Alignment errors */ 849 lenerr = at91_emac_read(AT91_EMAC_ELR) + at91_emac_read(AT91_EMAC_USF); 850 dev->stats.rx_length_errors += lenerr; /* Excessive Length or Undersize Frame error */ 851 seqe = at91_emac_read(AT91_EMAC_SEQE); 852 dev->stats.rx_crc_errors += seqe; /* CRC error */ 853 dev->stats.rx_fifo_errors += at91_emac_read(AT91_EMAC_DRFC); /* Receive buffer not available */ 854 dev->stats.rx_errors += (ale + lenerr + seqe 855 + at91_emac_read(AT91_EMAC_CDE) + at91_emac_read(AT91_EMAC_RJB)); 856 857 dev->stats.tx_packets += at91_emac_read(AT91_EMAC_FRA); /* Frames successfully transmitted */ 858 dev->stats.tx_fifo_errors += at91_emac_read(AT91_EMAC_TUE); /* Transmit FIFO underruns */ 859 dev->stats.tx_carrier_errors += at91_emac_read(AT91_EMAC_CSE); /* Carrier Sense errors */ 860 dev->stats.tx_heartbeat_errors += at91_emac_read(AT91_EMAC_SQEE);/* Heartbeat error */ 861 862 lcol = at91_emac_read(AT91_EMAC_LCOL); 863 ecol = at91_emac_read(AT91_EMAC_ECOL); 864 dev->stats.tx_window_errors += lcol; /* Late collisions */ 865 dev->stats.tx_aborted_errors += ecol; /* 16 collisions */ 866 867 dev->stats.collisions += (at91_emac_read(AT91_EMAC_SCOL) + at91_emac_read(AT91_EMAC_MCOL) + lcol + ecol); 868 } 869 return &dev->stats; 870} 871 872/* 873 * Extract received frame from buffer descriptors and sent to upper layers. 874 * (Called from interrupt context) 875 */ 876static void at91ether_rx(struct net_device *dev) 877{ 878 struct at91_private *lp = netdev_priv(dev); 879 struct recv_desc_bufs *dlist; 880 unsigned char *p_recv; 881 struct sk_buff *skb; 882 unsigned int pktlen; 883 884 dlist = lp->dlist; 885 while (dlist->descriptors[lp->rxBuffIndex].addr & EMAC_DESC_DONE) { 886 p_recv = dlist->recv_buf[lp->rxBuffIndex]; 887 pktlen = dlist->descriptors[lp->rxBuffIndex].size & 0x7ff; /* Length of frame including FCS */ 888 skb = dev_alloc_skb(pktlen + 2); 889 if (skb != NULL) { 890 skb_reserve(skb, 2); 891 memcpy(skb_put(skb, pktlen), p_recv, pktlen); 892 893 skb->protocol = eth_type_trans(skb, dev); 894 dev->stats.rx_bytes += pktlen; 895 netif_rx(skb); 896 } 897 else { 898 dev->stats.rx_dropped += 1; 899 printk(KERN_NOTICE "%s: Memory squeeze, dropping packet.\n", dev->name); 900 } 901 902 if (dlist->descriptors[lp->rxBuffIndex].size & EMAC_MULTICAST) 903 dev->stats.multicast++; 904 905 dlist->descriptors[lp->rxBuffIndex].addr &= ~EMAC_DESC_DONE; /* reset ownership bit */ 906 if (lp->rxBuffIndex == MAX_RX_DESCR-1) /* wrap after last buffer */ 907 lp->rxBuffIndex = 0; 908 else 909 lp->rxBuffIndex++; 910 } 911} 912 913/* 914 * MAC interrupt handler 915 */ 916static irqreturn_t at91ether_interrupt(int irq, void *dev_id) 917{ 918 struct net_device *dev = (struct net_device *) dev_id; 919 struct at91_private *lp = netdev_priv(dev); 920 unsigned long intstatus, ctl; 921 922 /* MAC Interrupt Status register indicates what interrupts are pending. 923 It is automatically cleared once read. */ 924 intstatus = at91_emac_read(AT91_EMAC_ISR); 925 926 if (intstatus & AT91_EMAC_RCOM) /* Receive complete */ 927 at91ether_rx(dev); 928 929 if (intstatus & AT91_EMAC_TCOM) { /* Transmit complete */ 930 /* The TCOM bit is set even if the transmission failed. */ 931 if (intstatus & (AT91_EMAC_TUND | AT91_EMAC_RTRY)) 932 dev->stats.tx_errors += 1; 933 934 if (lp->skb) { 935 dev_kfree_skb_irq(lp->skb); 936 lp->skb = NULL; 937 dma_unmap_single(NULL, lp->skb_physaddr, lp->skb_length, DMA_TO_DEVICE); 938 } 939 netif_wake_queue(dev); 940 } 941 942 /* Work-around for Errata #11 */ 943 if (intstatus & AT91_EMAC_RBNA) { 944 ctl = at91_emac_read(AT91_EMAC_CTL); 945 at91_emac_write(AT91_EMAC_CTL, ctl & ~AT91_EMAC_RE); 946 at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_RE); 947 } 948 949 if (intstatus & AT91_EMAC_ROVR) 950 printk("%s: ROVR error\n", dev->name); 951 952 return IRQ_HANDLED; 953} 954 955#ifdef CONFIG_NET_POLL_CONTROLLER 956static void at91ether_poll_controller(struct net_device *dev) 957{ 958 unsigned long flags; 959 960 local_irq_save(flags); 961 at91ether_interrupt(dev->irq, dev); 962 local_irq_restore(flags); 963} 964#endif 965 966static const struct net_device_ops at91ether_netdev_ops = { 967 .ndo_open = at91ether_open, 968 .ndo_stop = at91ether_close, 969 .ndo_start_xmit = at91ether_start_xmit, 970 .ndo_get_stats = at91ether_stats, 971 .ndo_set_multicast_list = at91ether_set_multicast_list, 972 .ndo_set_mac_address = set_mac_address, 973 .ndo_do_ioctl = at91ether_ioctl, 974 .ndo_validate_addr = eth_validate_addr, 975 .ndo_change_mtu = eth_change_mtu, 976#ifdef CONFIG_NET_POLL_CONTROLLER 977 .ndo_poll_controller = at91ether_poll_controller, 978#endif 979}; 980 981/* 982 * Initialize the ethernet interface 983 */ 984static int __init at91ether_setup(unsigned long phy_type, unsigned short phy_address, 985 struct platform_device *pdev, struct clk *ether_clk) 986{ 987 struct at91_eth_data *board_data = pdev->dev.platform_data; 988 struct net_device *dev; 989 struct at91_private *lp; 990 unsigned int val; 991 int res; 992 993 dev = alloc_etherdev(sizeof(struct at91_private)); 994 if (!dev) 995 return -ENOMEM; 996 997 dev->base_addr = AT91_VA_BASE_EMAC; 998 dev->irq = AT91RM9200_ID_EMAC; 999 1000 /* Install the interrupt handler */ 1001 if (request_irq(dev->irq, at91ether_interrupt, 0, dev->name, dev)) { 1002 free_netdev(dev); 1003 return -EBUSY; 1004 } 1005 1006 /* Allocate memory for DMA Receive descriptors */ 1007 lp = netdev_priv(dev); 1008 lp->dlist = (struct recv_desc_bufs *) dma_alloc_coherent(NULL, sizeof(struct recv_desc_bufs), (dma_addr_t *) &lp->dlist_phys, GFP_KERNEL); 1009 if (lp->dlist == NULL) { 1010 free_irq(dev->irq, dev); 1011 free_netdev(dev); 1012 return -ENOMEM; 1013 } 1014 lp->board_data = *board_data; 1015 lp->ether_clk = ether_clk; 1016 platform_set_drvdata(pdev, dev); 1017 1018 spin_lock_init(&lp->lock); 1019 1020 ether_setup(dev); 1021 dev->netdev_ops = &at91ether_netdev_ops; 1022 dev->ethtool_ops = &at91ether_ethtool_ops; 1023 1024 SET_NETDEV_DEV(dev, &pdev->dev); 1025 1026 get_mac_address(dev); /* Get ethernet address and store it in dev->dev_addr */ 1027 update_mac_address(dev); /* Program ethernet address into MAC */ 1028 1029 at91_emac_write(AT91_EMAC_CTL, 0); 1030 1031 if (lp->board_data.is_rmii) 1032 at91_emac_write(AT91_EMAC_CFG, AT91_EMAC_CLK_DIV32 | AT91_EMAC_BIG | AT91_EMAC_RMII); 1033 else 1034 at91_emac_write(AT91_EMAC_CFG, AT91_EMAC_CLK_DIV32 | AT91_EMAC_BIG); 1035 1036 /* Perform PHY-specific initialization */ 1037 spin_lock_irq(&lp->lock); 1038 enable_mdi(); 1039 if ((phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { 1040 read_phy(phy_address, MII_DSCR_REG, &val); 1041 if ((val & (1 << 10)) == 0) /* DSCR bit 10 is 0 -- fiber mode */ 1042 lp->phy_media = PORT_FIBRE; 1043 } else if (machine_is_csb337()) { 1044 /* mix link activity status into LED2 link state */ 1045 write_phy(phy_address, MII_LEDCTRL_REG, 0x0d22); 1046 } else if (machine_is_ecbat91()) 1047 write_phy(phy_address, MII_LEDCTRL_REG, 0x156A); 1048 1049 disable_mdi(); 1050 spin_unlock_irq(&lp->lock); 1051 1052 lp->mii.dev = dev; /* Support for ethtool */ 1053 lp->mii.mdio_read = mdio_read; 1054 lp->mii.mdio_write = mdio_write; 1055 lp->mii.phy_id = phy_address; 1056 lp->mii.phy_id_mask = 0x1f; 1057 lp->mii.reg_num_mask = 0x1f; 1058 1059 lp->phy_type = phy_type; /* Type of PHY connected */ 1060 lp->phy_address = phy_address; /* MDI address of PHY */ 1061 1062 /* Register the network interface */ 1063 res = register_netdev(dev); 1064 if (res) { 1065 free_irq(dev->irq, dev); 1066 free_netdev(dev); 1067 dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys); 1068 return res; 1069 } 1070 1071 /* Determine current link speed */ 1072 spin_lock_irq(&lp->lock); 1073 enable_mdi(); 1074 update_linkspeed(dev, 0); 1075 disable_mdi(); 1076 spin_unlock_irq(&lp->lock); 1077 netif_carrier_off(dev); /* will be enabled in open() */ 1078 1079 /* If board has no PHY IRQ, use a timer to poll the PHY */ 1080 if (!lp->board_data.phy_irq_pin) { 1081 init_timer(&lp->check_timer); 1082 lp->check_timer.data = (unsigned long)dev; 1083 lp->check_timer.function = at91ether_check_link; 1084 } else if (lp->board_data.phy_irq_pin >= 32) 1085 gpio_request(lp->board_data.phy_irq_pin, "ethernet_phy"); 1086 1087 /* Display ethernet banner */ 1088 printk(KERN_INFO "%s: AT91 ethernet at 0x%08x int=%d %s%s (%pM)\n", 1089 dev->name, (uint) dev->base_addr, dev->irq, 1090 at91_emac_read(AT91_EMAC_CFG) & AT91_EMAC_SPD ? "100-" : "10-", 1091 at91_emac_read(AT91_EMAC_CFG) & AT91_EMAC_FD ? "FullDuplex" : "HalfDuplex", 1092 dev->dev_addr); 1093 if ((phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) 1094 printk(KERN_INFO "%s: Davicom 9161 PHY %s\n", dev->name, (lp->phy_media == PORT_FIBRE) ? "(Fiber)" : "(Copper)"); 1095 else if (phy_type == MII_LXT971A_ID) 1096 printk(KERN_INFO "%s: Intel LXT971A PHY\n", dev->name); 1097 else if (phy_type == MII_RTL8201_ID) 1098 printk(KERN_INFO "%s: Realtek RTL8201(B)L PHY\n", dev->name); 1099 else if (phy_type == MII_BCM5221_ID) 1100 printk(KERN_INFO "%s: Broadcom BCM5221 PHY\n", dev->name); 1101 else if (phy_type == MII_DP83847_ID) 1102 printk(KERN_INFO "%s: National Semiconductor DP83847 PHY\n", dev->name); 1103 else if (phy_type == MII_DP83848_ID) 1104 printk(KERN_INFO "%s: National Semiconductor DP83848 PHY\n", dev->name); 1105 else if (phy_type == MII_AC101L_ID) 1106 printk(KERN_INFO "%s: Altima AC101L PHY\n", dev->name); 1107 else if (phy_type == MII_KS8721_ID) 1108 printk(KERN_INFO "%s: Micrel KS8721 PHY\n", dev->name); 1109 else if (phy_type == MII_T78Q21x3_ID) 1110 printk(KERN_INFO "%s: Teridian 78Q21x3 PHY\n", dev->name); 1111 else if (phy_type == MII_LAN83C185_ID) 1112 printk(KERN_INFO "%s: SMSC LAN83C185 PHY\n", dev->name); 1113 1114 return 0; 1115} 1116 1117/* 1118 * Detect MAC and PHY and perform initialization 1119 */ 1120static int __init at91ether_probe(struct platform_device *pdev) 1121{ 1122 unsigned int phyid1, phyid2; 1123 int detected = -1; 1124 unsigned long phy_id; 1125 unsigned short phy_address = 0; 1126 struct clk *ether_clk; 1127 1128 ether_clk = clk_get(&pdev->dev, "ether_clk"); 1129 if (IS_ERR(ether_clk)) { 1130 printk(KERN_ERR "at91_ether: no clock defined\n"); 1131 return -ENODEV; 1132 } 1133 clk_enable(ether_clk); /* Enable Peripheral clock */ 1134 1135 while ((detected != 0) && (phy_address < 32)) { 1136 /* Read the PHY ID registers */ 1137 enable_mdi(); 1138 read_phy(phy_address, MII_PHYSID1, &phyid1); 1139 read_phy(phy_address, MII_PHYSID2, &phyid2); 1140 disable_mdi(); 1141 1142 phy_id = (phyid1 << 16) | (phyid2 & 0xfff0); 1143 switch (phy_id) { 1144 case MII_DM9161_ID: /* Davicom 9161: PHY_ID1 = 0x181, PHY_ID2 = B881 */ 1145 case MII_DM9161A_ID: /* Davicom 9161A: PHY_ID1 = 0x181, PHY_ID2 = B8A0 */ 1146 case MII_LXT971A_ID: /* Intel LXT971A: PHY_ID1 = 0x13, PHY_ID2 = 78E0 */ 1147 case MII_RTL8201_ID: /* Realtek RTL8201: PHY_ID1 = 0, PHY_ID2 = 0x8201 */ 1148 case MII_BCM5221_ID: /* Broadcom BCM5221: PHY_ID1 = 0x40, PHY_ID2 = 0x61e0 */ 1149 case MII_DP83847_ID: /* National Semiconductor DP83847: */ 1150 case MII_DP83848_ID: /* National Semiconductor DP83848: */ 1151 case MII_AC101L_ID: /* Altima AC101L: PHY_ID1 = 0x22, PHY_ID2 = 0x5520 */ 1152 case MII_KS8721_ID: /* Micrel KS8721: PHY_ID1 = 0x22, PHY_ID2 = 0x1610 */ 1153 case MII_T78Q21x3_ID: /* Teridian 78Q21x3: PHY_ID1 = 0x0E, PHY_ID2 = 7237 */ 1154 case MII_LAN83C185_ID: /* SMSC LAN83C185: PHY_ID1 = 0x0007, PHY_ID2 = 0xC0A1 */ 1155 detected = at91ether_setup(phy_id, phy_address, pdev, ether_clk); 1156 break; 1157 } 1158 1159 phy_address++; 1160 } 1161 1162 clk_disable(ether_clk); /* Disable Peripheral clock */ 1163 1164 return detected; 1165} 1166 1167static int __devexit at91ether_remove(struct platform_device *pdev) 1168{ 1169 struct net_device *dev = platform_get_drvdata(pdev); 1170 struct at91_private *lp = netdev_priv(dev); 1171 1172 if (lp->board_data.phy_irq_pin >= 32) 1173 gpio_free(lp->board_data.phy_irq_pin); 1174 1175 unregister_netdev(dev); 1176 free_irq(dev->irq, dev); 1177 dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys); 1178 clk_put(lp->ether_clk); 1179 1180 platform_set_drvdata(pdev, NULL); 1181 free_netdev(dev); 1182 return 0; 1183} 1184 1185#ifdef CONFIG_PM 1186 1187static int at91ether_suspend(struct platform_device *pdev, pm_message_t mesg) 1188{ 1189 struct net_device *net_dev = platform_get_drvdata(pdev); 1190 struct at91_private *lp = netdev_priv(net_dev); 1191 int phy_irq = lp->board_data.phy_irq_pin; 1192 1193 if (netif_running(net_dev)) { 1194 if (phy_irq) 1195 disable_irq(phy_irq); 1196 1197 netif_stop_queue(net_dev); 1198 netif_device_detach(net_dev); 1199 1200 clk_disable(lp->ether_clk); 1201 } 1202 return 0; 1203} 1204 1205static int at91ether_resume(struct platform_device *pdev) 1206{ 1207 struct net_device *net_dev = platform_get_drvdata(pdev); 1208 struct at91_private *lp = netdev_priv(net_dev); 1209 int phy_irq = lp->board_data.phy_irq_pin; 1210 1211 if (netif_running(net_dev)) { 1212 clk_enable(lp->ether_clk); 1213 1214 netif_device_attach(net_dev); 1215 netif_start_queue(net_dev); 1216 1217 if (phy_irq) 1218 enable_irq(phy_irq); 1219 } 1220 return 0; 1221} 1222 1223#else 1224#define at91ether_suspend NULL 1225#define at91ether_resume NULL 1226#endif 1227 1228static struct platform_driver at91ether_driver = { 1229 .remove = __devexit_p(at91ether_remove), 1230 .suspend = at91ether_suspend, 1231 .resume = at91ether_resume, 1232 .driver = { 1233 .name = DRV_NAME, 1234 .owner = THIS_MODULE, 1235 }, 1236}; 1237 1238static int __init at91ether_init(void) 1239{ 1240 return platform_driver_probe(&at91ether_driver, at91ether_probe); 1241} 1242 1243static void __exit at91ether_exit(void) 1244{ 1245 platform_driver_unregister(&at91ether_driver); 1246} 1247 1248module_init(at91ether_init) 1249module_exit(at91ether_exit) 1250 1251MODULE_LICENSE("GPL"); 1252MODULE_DESCRIPTION("AT91RM9200 EMAC Ethernet driver"); 1253MODULE_AUTHOR("Andrew Victor"); 1254MODULE_ALIAS("platform:" DRV_NAME); 1255