/external/llvm/lib/Target/ARM/ |
H A D | Thumb2RegisterInfo.h | 37 unsigned PredReg = 0,
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H A D | Thumb2InstrInfo.cpp | 60 unsigned PredReg = 0; local 61 ARMCC::CondCodes CC = getInstrPredicate(Tail, PredReg); 108 unsigned PredReg = 0; local 109 return getITInstrPredicate(MBBI, PredReg) == ARMCC::AL; 180 ARMCC::CondCodes Pred, unsigned PredReg, 195 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); 202 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); 211 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 217 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 403 unsigned PredReg; 177 emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags) argument [all...] |
H A D | Thumb2RegisterInfo.cpp | 40 ARMCC::CondCodes Pred, unsigned PredReg, 35 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
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H A D | ARMLoadStoreOptimizer.cpp | 95 ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, 109 unsigned PredReg, 115 ARMCC::CondCodes Pred, unsigned PredReg, 286 unsigned PredReg, unsigned Scratch, DebugLoc dl, 340 .addImm(Pred).addReg(PredReg).addReg(0); 351 .addImm(Pred).addReg(PredReg); 371 ARMCC::CondCodes Pred, unsigned PredReg, 416 Pred, PredReg, Scratch, dl, Regs, ImpDefs)) 448 ARMCC::CondCodes Pred, unsigned PredReg, 501 Base, false, Opcode, Pred, PredReg, Scratc 282 MergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, int Offset, unsigned Base, bool BaseKill, int Opcode, ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, DebugLoc dl, ArrayRef<std::pair<unsigned, bool> > Regs, ArrayRef<unsigned> ImpDefs) argument 365 MergeOpsUpdate(MachineBasicBlock &MBB, MemOpQueue &memOps, unsigned memOpsBegin, unsigned memOpsEnd, unsigned insertAfter, int Offset, unsigned Base, bool BaseKill, int Opcode, ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, DebugLoc dl, SmallVector<MachineBasicBlock::iterator, 4> &Merges) argument 446 MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex, unsigned Base, int Opcode, unsigned Size, ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, MemOpQueue &MemOps, SmallVector<MachineBasicBlock::iterator, 4> &Merges) argument 531 isMatchingDecrement(MachineInstr *MI, unsigned Base, unsigned Bytes, unsigned Limit, ARMCC::CondCodes Pred, unsigned PredReg) argument 564 isMatchingIncrement(MachineInstr *MI, unsigned Base, unsigned Bytes, unsigned Limit, ARMCC::CondCodes Pred, unsigned PredReg) argument 720 unsigned PredReg = 0; local 873 unsigned PredReg = 0; local 1074 InsertLDR_STR(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, int Offset, bool isDef, DebugLoc dl, unsigned NewOpc, unsigned Reg, bool RegDeadKill, bool RegUndef, unsigned BaseReg, bool BaseKill, bool BaseUndef, bool OffKill, bool OffUndef, ARMCC::CondCodes Pred, unsigned PredReg, const TargetInstrInfo *TII, bool isT2) argument 1131 unsigned PredReg = 0; local 1253 unsigned PredReg = 0; local 1564 CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1, DebugLoc &dl, unsigned &NewOpc, unsigned &EvenReg, unsigned &OddReg, unsigned &BaseReg, int &Offset, unsigned &PredReg, ARMCC::CondCodes &Pred, bool &isT2) argument 1729 unsigned BaseReg = 0, PredReg = 0; local 1826 unsigned PredReg = 0; local [all...] |
H A D | Thumb1RegisterInfo.h | 42 unsigned PredReg = 0,
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H A D | Thumb2InstrInfo.h | 75 ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
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H A D | ARMBaseInstrInfo.h | 346 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg); 362 ARMCC::CondCodes Pred, unsigned PredReg, 368 ARMCC::CondCodes Pred, unsigned PredReg,
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H A D | ARMBaseRegisterInfo.cpp | 695 unsigned PredReg, unsigned MIFlags) const { 705 .addImm(0).addImm(Pred).addReg(PredReg) 729 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { 732 Pred, PredReg, TII); 735 Pred, PredReg, TII); 768 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN. 769 unsigned PredReg = Old->getOperand(2).getReg(); local 770 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg); 772 // Note: PredReg is operand 3 for ADJCALLSTACKUP. 773 unsigned PredReg local 690 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument 1108 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); local [all...] |
H A D | MLxExpansionPass.cpp | 219 unsigned PredReg = MI->getOperand(++NextOp).getReg(); local 230 MIB.addImm(Pred).addReg(PredReg); 242 MIB.addImm(Pred).addReg(PredReg);
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H A D | Thumb2ITBlockPass.cpp | 173 unsigned PredReg = 0; local 174 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg);
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H A D | ARMBaseRegisterInfo.h | 168 unsigned PredReg = 0,
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H A D | Thumb2SizeReduction.cpp | 543 unsigned PredReg = 0; local 544 if (getInstrPredicate(MI, PredReg) == ARMCC::AL) { 642 unsigned PredReg = 0; local 643 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); 734 unsigned PredReg = 0; local 735 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
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H A D | Thumb1RegisterInfo.cpp | 69 ARMCC::CondCodes Pred, unsigned PredReg, 79 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg) 412 unsigned PredReg; 413 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) { 64 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
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H A D | ARMExpandPseudoInsts.cpp | 614 unsigned PredReg = 0; local 615 ARMCC::CondCodes Pred = getInstrPredicate(&MI, PredReg); 638 LO16.addImm(Pred).addReg(PredReg).addReg(0); 639 HI16.addImm(Pred).addReg(PredReg).addReg(0); 675 LO16.addImm(Pred).addReg(PredReg); 676 HI16.addImm(Pred).addReg(PredReg);
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H A D | ARMConstantIslandPass.cpp | 1371 unsigned PredReg = 0; local 1372 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg); 1818 unsigned PredReg = 0; local 1819 ARMCC::CondCodes Pred = getInstrPredicate(Br.MI, PredReg); 1837 Pred = getInstrPredicate(CmpMI, PredReg);
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H A D | ARMBaseInstrInfo.cpp | 1480 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { argument 1483 PredReg = 0; 1487 PredReg = MI->getOperand(PIdx+1).getReg(); 1510 unsigned PredReg = 0; local 1511 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg); 1513 if (CC == ARMCC::AL || PredReg != ARM::CPSR) 1580 ARMCC::CondCodes Pred, unsigned PredReg, 1599 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 1577 emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags) argument
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H A D | ARMISelDAGToDAG.cpp | 2599 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); local 2600 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() }; 2836 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); local 2837 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; 2856 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); local 2857 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; 2875 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); local 2876 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
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