Searched defs:FS (Results 26 - 50 of 60) sorted by relevance

123

/external/llvm/lib/Target/Hexagon/
H A DHexagonTargetMachine.cpp65 StringRef CPU, StringRef FS,
70 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
74 Subtarget(TT, CPU, FS), InstrInfo(Subtarget), TLInfo(*this),
64 HexagonTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/external/llvm/lib/Target/MSP430/MCTargetDesc/
H A DMSP430MCTargetDesc.cpp47 StringRef FS) {
49 InitMSP430MCSubtargetInfo(X, TT, CPU, FS);
46 createMSP430MCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) argument
/external/llvm/lib/Target/Mips/
H A DMipsTargetMachine.cpp40 StringRef CPU, StringRef FS, const TargetOptions &Options,
44 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
45 Subtarget(TT, CPU, FS, isLittle, RM),
63 StringRef CPU, StringRef FS, const TargetOptions &Options,
66 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
72 StringRef CPU, StringRef FS, const TargetOptions &Options,
75 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
39 MipsTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle) argument
62 MipsebTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
71 MipselTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/external/llvm/lib/Target/NVPTX/
H A DNVPTXTargetMachine.cpp66 StringRef FS,
72 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
73 Subtarget(TT, CPU, FS, is64bit),
84 StringRef CPU, StringRef FS,
88 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
94 StringRef CPU, StringRef FS,
98 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
63 NVPTXTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions& Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit) argument
83 NVPTXTargetMachine32(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
93 NVPTXTargetMachine64(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/external/llvm/lib/Target/PowerPC/
H A DPPCTargetMachine.cpp36 StringRef CPU, StringRef FS,
41 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
42 Subtarget(TT, CPU, FS, is64Bit),
56 StringRef CPU, StringRef FS,
60 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
66 StringRef CPU, StringRef FS,
70 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
35 PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64Bit) argument
55 PPC32TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
65 PPC64TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/external/llvm/lib/Target/Sparc/
H A DSparcTargetMachine.cpp29 StringRef CPU, StringRef FS,
34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
35 Subtarget(TT, CPU, FS, is64bit),
80 StringRef FS,
85 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
92 StringRef FS,
97 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
28 SparcTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit) argument
78 SparcV8TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
90 SparcV9TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/external/eclipse-basebuilder/basebuilder-3.6.2/org.eclipse.releng.basebuilder/plugins/org.eclipse.build.tools/src_rss/org/eclipse/releng/services/rss/
H A DRSSFeedPublisherTask.java53 private static final String FS = File.separator; field in class:RSSFeedPublisherTask
176 File destFile = new File(CVSTemp + FS + "checkoutDir" + FS + filename); //$NON-NLS-1$
201 runCVSExecTask("add " + filename, CVSTemp + FS + "checkoutDir"); //$NON-NLS-1$ //$NON-NLS-2$
206 runCVSExecTask("ci -m '' " + filename, CVSTemp + FS + "checkoutDir"); //$NON-NLS-1$ //$NON-NLS-2$
218 String targetPath = SCPTarget.substring(SCPTarget.indexOf(CL)+1,SCPTarget.lastIndexOf(FS));
/external/llvm/lib/CodeGen/
H A DLLVMTargetMachine.cpp66 StringRef CPU, StringRef FS,
70 : TargetMachine(T, Triple, CPU, FS, Options) {
65 LLVMTargetMachine(const Target &T, StringRef Triple, StringRef CPU, StringRef FS, TargetOptions Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/external/llvm/lib/Target/MBlaze/MCTargetDesc/
H A DMBlazeMCTargetDesc.cpp50 StringRef FS) {
52 InitMBlazeMCSubtargetInfo(X, TT, CPU, FS);
49 createMBlazeMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) argument
/external/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCTargetDesc.cpp82 StringRef FS) {
84 if (!FS.empty()) {
86 ArchFS = ArchFS + "," + FS.str();
88 ArchFS = FS;
81 createMipsMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) argument
/external/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCMCTargetDesc.cpp55 StringRef FS) {
57 InitPPCMCSubtargetInfo(X, TT, CPU, FS);
54 createPPCMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) argument
/external/llvm/lib/Target/
H A DTargetMachine.cpp46 StringRef TT, StringRef CPU, StringRef FS,
48 : TheTarget(T), TargetTriple(TT), TargetCPU(CPU), TargetFS(FS),
45 TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options) argument
/external/llvm/lib/Target/X86/
H A DX86Subtarget.cpp321 const std::string &FS,
323 : X86GenSubtargetInfo(TT, CPU, FS)
358 if (!FS.empty() || !CPU.empty()) {
370 std::string FullFS = FS;
320 X86Subtarget(const std::string &TT, const std::string &CPU, const std::string &FS, unsigned StackAlignOverride, bool is64Bit) argument
H A DX86TargetMachine.cpp34 StringRef CPU, StringRef FS,
38 : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false),
57 StringRef CPU, StringRef FS,
61 : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true),
73 StringRef CPU, StringRef FS,
78 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
79 Subtarget(TT, CPU, FS, Options.StackAlignmentOverride, is64Bit),
33 X86_32TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
56 X86_64TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
72 X86TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64Bit) argument
/external/clang/lib/Analysis/
H A DFormatString.cpp145 FormatSpecifier &FS,
169 FS.setArgIndex(Amt.getConstantAmount() - 1);
170 FS.setUsesPositionalArg();
181 clang::analyze_format_string::ParseLengthModifier(FormatSpecifier &FS, argument
228 FS.setLengthModifier(lm);
144 ParseArgPosition(FormatStringHandler &H, FormatSpecifier &FS, const char *Start, const char *&Beg, const char *E) argument
H A DPrintfFormatString.cpp36 static bool ParsePrecision(FormatStringHandler &H, PrintfSpecifier &FS, argument
40 FS.setPrecision(ParseNonPositionAmount(Beg, E, *argIndex));
46 FS.setPrecision(Amt);
88 PrintfSpecifier FS; local
89 if (ParseArgPosition(H, FS, Start, I, E))
105 FS.setHasThousandsGrouping(I);
107 case '-': FS.setIsLeftJustified(I); break;
108 case '+': FS.setHasPlusPrefix(I); break;
109 case ' ': FS.setHasSpacePrefix(I); break;
110 case '#': FS
[all...]
/external/clang/tools/driver/
H A Dcc1as_main.cpp310 std::string FS; local
312 FS = Opts.Features[0];
314 FS += "," + Opts.Features[i];
321 STI(TheTarget->createMCSubtargetInfo(Opts.Triple, Opts.CPU, FS));
/external/guava/guava/src/com/google/common/base/
H A DAscii.java335 * relationship shall be: FS is the most inclusive, then GS, then RS,
341 public static final byte FS = 28; field in class:Ascii
344 * @see #FS
351 * @see #FS
358 * @see #FS
/external/kernel-headers/original/asm-x86/
H A Dptrace-abi.h15 #define FS 9 macro
/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.cpp117 StringRef FS) {
119 if (!FS.empty()) {
121 ArchFS = ArchFS + "," + FS.str();
123 ArchFS = FS;
116 createARMMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) argument
/external/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp48 std::string FS; local
50 FS = "+64bit-mode";
52 FS = "-64bit-mode";
53 return FS;
279 case X86::FS: return 4;
328 StringRef FS) {
330 if (!FS.empty()) {
332 ArchFS = ArchFS + "," + FS.str();
334 ArchFS = FS;
327 createX86MCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) argument
/external/clang/include/clang/StaticAnalyzer/Core/PathSensitive/
H A DCoreEngine.h108 FunctionSummariesTy *FS)
112 FunctionSummaries(FS){}
107 CoreEngine(SubEngine& subengine, FunctionSummariesTy *FS) argument
/external/clang/lib/StaticAnalyzer/Checkers/
H A DCheckSecuritySyntaxOnly.cpp89 void checkLoopConditionForFloat(const ForStmt *FS);
169 void WalkAST::VisitForStmt(ForStmt *FS) { argument
170 checkLoopConditionForFloat(FS);
173 VisitChildren(FS);
216 void WalkAST::checkLoopConditionForFloat(const ForStmt *FS) { argument
221 const Expr *condition = FS->getCond();
227 const Expr *increment = FS->getInc();
289 PathDiagnosticLocation::createBegin(FS, BR.getSourceManager(), AC);
/external/webrtc/src/modules/audio_processing/agc/
H A Ddigital_agc.c305 WebRtc_Word16 *out_H, WebRtc_UWord32 FS,
325 if (FS == 8000)
329 } else if (FS == 16000)
333 } else if (FS == 32000)
348 if (FS == 32000)
588 if (FS == 32000)
623 if (FS == 32000)
303 WebRtcAgc_ProcessDigital(DigitalAgc_t *stt, const WebRtc_Word16 *in_near, const WebRtc_Word16 *in_near_H, WebRtc_Word16 *out, WebRtc_Word16 *out_H, WebRtc_UWord32 FS, WebRtc_Word16 lowlevelSignal) argument
/external/llvm/include/llvm/Support/
H A DTargetRegistry.h1008 StringRef FS) {
1043 StringRef CPU, StringRef FS,
1048 return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL);
1007 Allocator(StringRef TT, StringRef CPU, StringRef FS) argument
1042 Allocator(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument

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