| /external/llvm/utils/TableGen/ |
| H A D | AsmWriterInst.cpp | 202 CGIOperandList::OperandInfo OpInfo = CGI.Operands[OpNo]; local
204 unsigned MIOp = OpInfo.MIOperandNo;
205 Operands.push_back(AsmWriterOperand(OpInfo.PrinterMethodName,
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| H A D | InstrInfoEmitter.cpp | 49 const OperandInfoMapTy &OpInfo,
299 const OperandInfoMapTy &OpInfo,
376 OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
296 emitRecord(const CodeGenInstruction &Inst, unsigned Num, Record *InstrInfo, std::map<std::vector<Record*>, unsigned> &EmittedLists, const OperandInfoMapTy &OpInfo, raw_ostream &OS) argument
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| H A D | AsmMatcherEmitter.cpp | 1563 const CGIOperandList::OperandInfo &OpInfo = ResultInst->Operands[i]; local
1566 int TiedOp = OpInfo.getTiedRegister();
1573 int SrcOperand = findAsmOperandNamed(OpInfo.Name);
1574 if (OpInfo.Name.empty() || SrcOperand == -1)
1576 TheDef->getName() + "' has operand '" + OpInfo.Name +
1580 unsigned NumOperands = OpInfo.MINumOperands;
1589 AsmOperands[SrcOperand+AI].SrcOpName == OpInfo.Name &&
1605 const CGIOperandList::OperandInfo *OpInfo = &ResultInst->Operands[i]; local
1608 int TiedOp = OpInfo->getTiedRegister();
1615 const std::string &OpName = OpInfo
[all...] |
| H A D | CodeGenDAGPatterns.cpp | 2397 const SDNodeInfo &OpInfo = CDP.getSDNodeInfo(N1->getOperator()); local
2398 if (OpInfo.getNumResults() != 1 || OpInfo.getNumOperands() != 1)
2400 return OpInfo.getEnumName() == "ISD::BITCAST";
2430 const SDNodeInfo &OpInfo = CDP.getSDNodeInfo(N->getOperator()); local
2433 if (OpInfo.hasProperty(SDNPMayStore)) mayStore = true;
2434 if (OpInfo.hasProperty(SDNPMayLoad)) mayLoad = true;
2435 if (OpInfo.hasProperty(SDNPSideEffect)) hasSideEffects = true;
2436 if (OpInfo.hasProperty(SDNPVariadic)) isVariadic = true;
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| /external/llvm/include/llvm/Bitcode/ |
| H A D | BitCodes.h | 180 void Add(const BitCodeAbbrevOp &OpInfo) { argument
181 OperandList.push_back(OpInfo);
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| /external/llvm/lib/Transforms/Utils/ |
| H A D | AddrModeMatcher.cpp | 387 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i]; local
390 TLI.ComputeConstraintToUse(OpInfo, SDValue());
394 if (OpInfo.CallOperandVal == OpVal &&
395 (OpInfo.ConstraintType != TargetLowering::C_Memory ||
396 !OpInfo.isIndirect))
|
| /external/webkit/Source/JavaScriptCore/dfg/ |
| H A D | DFGNode.h | 164 struct OpInfo { struct in namespace:JSC::DFG
165 explicit OpInfo(unsigned value) : m_value(value) {} function in struct:JSC::DFG::OpInfo
186 Node(NodeType op, ExceptionInfo exceptionInfo, OpInfo imm, NodeIndex child1 = NoNode, NodeIndex child2 = NoNode, NodeIndex child3 = NoNode)
199 Node(NodeType op, ExceptionInfo exceptionInfo, OpInfo imm1, OpInfo imm2, NodeIndex child1 = NoNode, NodeIndex child2 = NoNode, NodeIndex child3 = NoNode)
|
| /external/llvm/include/llvm/MC/ |
| H A D | MCInstrDesc.h | 145 const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands member in class:llvm::MCInstrDesc
152 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
154 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
533 if (OpInfo[i].isPredicate())
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| /external/llvm/lib/Transforms/Scalar/ |
| H A D | CodeGenPrepare.cpp | 1031 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i]; local
1034 TLI->ComputeConstraintToUse(OpInfo, SDValue());
1036 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
1037 OpInfo.isIndirect) {
1040 } else if (OpInfo.Type == InlineAsm::isInput)
|
| /external/clang/lib/CodeGen/ |
| H A D | CGExprComplex.cpp | 603 BinOpInfo OpInfo; local
608 OpInfo.Ty = E->getComputationResultType();
611 assert(OpInfo.Ty->isAnyComplexType());
612 assert(CGF.getContext().hasSameUnqualifiedType(OpInfo.Ty,
614 OpInfo.RHS = Visit(E->getRHS());
621 OpInfo.LHS = EmitComplexToComplexCast(LHSComplexPair, LHSTy, OpInfo.Ty);
624 ComplexPairTy Result = (this->*Func)(OpInfo);
627 Result = EmitComplexToComplexCast(Result, OpInfo.Ty, LHSTy);
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| H A D | CGExprScalar.cpp | 1666 BinOpInfo OpInfo; local
1680 OpInfo.RHS = Visit(E->getRHS());
1681 OpInfo.Ty = E->getComputationResultType();
1682 OpInfo.Opcode = E->getOpcode();
1683 OpInfo.E = E;
1686 OpInfo.LHS = EmitLoadOfLValue(LHSLV);
1696 atomicPHI = Builder.CreatePHI(OpInfo.LHS->getType(), 2);
1697 atomicPHI->addIncoming(OpInfo.LHS, startBB);
1698 OpInfo.LHS = atomicPHI;
1701 OpInfo
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 2889 AsmOperandInfo &OpInfo = ConstraintOperands.back(); local
2892 if (OpInfo.multipleAlternatives.size() > maCount)
2893 maCount = OpInfo.multipleAlternatives.size();
2895 OpInfo.ConstraintVT = MVT::Other;
2898 switch (OpInfo.Type) {
2901 if (OpInfo.isIndirect) {
2902 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2911 OpInfo.ConstraintVT = getValueType(STy->getElementType(ResNo));
2914 OpInfo.ConstraintVT = getValueType(CS.getType());
2919 OpInfo
2978 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex]; local
3026 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex]; local
3168 ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, const TargetLowering &TLI, SDValue Op, SelectionDAG *DAG) argument
3219 ComputeConstraintToUse(AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG) const argument
[all...] |
| H A D | SelectionDAGBuilder.cpp | 5809 /// OpInfo describes the operand.
5814 SDISelAsmOperandInfo &OpInfo) {
5823 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5824 OpInfo.ConstraintVT);
5827 if (OpInfo.ConstraintVT != MVT::Other) {
5831 if (OpInfo.Type == InlineAsm::isInput &&
5832 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5837 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
5838 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5839 RegVT, OpInfo
5811 GetRegistersForValue(SelectionDAG &DAG, const TargetLowering &TLI, DebugLoc DL, SDISelAsmOperandInfo &OpInfo) argument
5929 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); local
6002 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; local
6087 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; local
6127 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; local
[all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 636 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; local
641 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
642 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
701 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; local
706 if (OpInfo[i].isPredicate()) {
738 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; local
[all...] |