| /external/qemu/target-mips/ |
| H A D | machine.c | 68 (env->tlb->mmu.r4k.tlb[i].D1 << 0));
226 env->tlb->mmu.r4k.tlb[i].D1 = (flags >> 0) & 1;
|
| H A D | cpu.h | 35 uint_fast16_t D1:1; member in struct:r4k_tlb_t
|
| H A D | helper.c | 94 if (rw == 0 || (n ? tlb->D1 : tlb->D0)) {
97 if (n ? tlb->D1 : tlb->D0)
|
| H A D | op_helper.c | 1584 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1629 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1703 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
|
| /external/icu4c/data/sprep/ |
| H A D | rfc3491.txt | 503 00D1; 00F1; MAP
626 01D1; 01D2; MAP
716 03D1; 03B8; MAP
838 04D0; 04D1; MAP
1231 24B7; 24D1; MAP
|
| H A D | rfc3530csci.txt | 502 00D1; 00F1; MAP
625 01D1; 01D2; MAP
715 03D1; 03B8; MAP
837 04D0; 04D1; MAP
1230 24B7; 24D1; MAP
|
| H A D | rfc3722.txt | 503 00D1; 00F1; MAP
626 01D1; 01D2; MAP
716 03D1; 03B8; MAP
838 04D0; 04D1; MAP
1231 24B7; 24D1; MAP
|
| H A D | rfc3920node.txt | 503 00D1; 00F1; MAP
626 01D1; 01D2; MAP
716 03D1; 03B8; MAP
838 04D0; 04D1; MAP
1231 24B7; 24D1; MAP
|
| H A D | rfc4518ci.txt | 470 00D1; 00F1; MAP
593 01D1; 01D2; MAP
683 03D1; 03B8; MAP
805 04D0; 04D1; MAP
1198 24B7; 24D1; MAP
|
| /external/icu4c/test/testdata/ |
| H A D | nfs4_cis_prep.txt | 493 00D1; 00F1; MAP
616 01D1; 01D2; MAP
706 03D1; 03B8; MAP
828 04D0; 04D1; MAP
1221 24B7; 24D1; MAP
|
| H A D | nfs4_cs_prep_ci.txt | 493 00D1; 00F1; MAP
616 01D1; 01D2; MAP
706 03D1; 03B8; MAP
828 04D0; 04D1; MAP
1221 24B7; 24D1; MAP
|
| H A D | nfs4_mixed_prep_s.txt | 493 00D1; 00F1; MAP
616 01D1; 01D2; MAP
706 03D1; 03B8; MAP
828 04D0; 04D1; MAP
1221 24B7; 24D1; MAP
|
| /external/valgrind/main/memcheck/ |
| H A D | mc_machine.c | 879 if (o >= GOF(D1) && o+sz <= GOF(D1) +SZB(D1)) return GOF(D1);
|
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.cpp | 628 case ARM::D1: return ARM::D0;
681 case ARM::D0: return ARM::D1;
|
| H A D | ARMAsmPrinter.cpp | 266 unsigned D1 = 256 + 2 * QReg; local
267 unsigned D2 = D1 + 1;
269 OutStreamer.AddComment("DW_OP_regx for Q register: D1");
271 EmitULEB128(D1);
|
| /external/valgrind/main/none/tests/arm/ |
| H A D | vfp.c | 655 #define TESTINSN_vpush_vpop_f64(D1, Dval10, Dval11, D2, Dval20, Dval21, D3, D4) \
662 "vmov "#D1", %1, %2\n\t" \
664 "vpush {"#D1", "#D2"}\n\t" \
667 "vstmia %0!, {"#D1"}\n\t" \
674 : #D1, #D2, #D3, #D4, "r4", "memory" \
676 printf(#D1" 0x%08x %08x "#D2" 0x%08x %08x "#D3" 0x%08x %08x "#D4" 0x%08x %08x\n",\
|
| /external/openssl/crypto/bn/asm/ |
| H A D | pa-risc2.s | 806 MOVB,TR %r6,%r29,$D1 ;offset 0x994
868 $D1
|
| H A D | pa-risc2W.s | 858 ADDIB,=,N -1,%r9,$D1 ;if (--count == 0) break (forward)
866 $D1
|
| /external/llvm/utils/TableGen/ |
| H A D | X86RecognizableInstr.cpp | 39 MAP(D1, 46) \
|
| /external/mdnsresponder/mDNSShared/ |
| H A D | CommonServices.h | 1469 #define HEX_DIGIT_11010001 D1
|
| /external/valgrind/main/cachegrind/ |
| H A D | cg_main.c | 1281 // "desc:" lines (giving I1/D1/LL cache configuration). The spaces after
1284 "desc: D1 cache: %s\n"
1286 I1.desc_line, D1.desc_line, LL.desc_line);
1514 VG_(umsg)(fmt, "D1 misses: ",
1525 VG_(umsg)("D1 miss rate: %s (%s + %s )\n", buf1, buf2,buf3);
|
| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 187 Hexagon::D1, Hexagon::D2
|
| /external/clang/lib/Sema/ |
| H A D | SemaDeclCXX.cpp | 5906 IsEquivalentForUsingDecl(ASTContext &Context, NamedDecl *D1, NamedDecl *D2, argument
5908 if (D1->getCanonicalDecl() == D2->getCanonicalDecl()) {
5913 if (TypedefNameDecl *TD1 = dyn_cast<TypedefNameDecl>(D1))
|
| H A D | SemaChecking.cpp | 3329 if (const DeclRefExpr *D1 = dyn_cast_or_null<DeclRefExpr>(E1))
3331 return D1->getDecl() == D2->getDecl();
|
| /external/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1001 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
|