Searched refs:Cond (Results 1 - 25 of 134) sorted by relevance

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/external/clang/test/SemaTemplate/
H A Dvalue-dependent-null-pointer-constant.cpp5 const char *f0(bool Cond) { argument
6 return Cond? "honk" : N;
9 const char *f1(bool Cond) { argument
10 return Cond? N : "honk";
H A Doverload-candidates.cpp52 template<typename Cond, typename T = void> struct enable_if : boost::enable_if<Cond::value, T> {};
H A Dinstantiate-expr-2.cpp77 struct Cond {
81 enum { resultT = Cond<true>::is,
82 resultF = Cond<false>::is };
92 struct Cond { struct in namespace:N6
97 typedef Cond<true, int, char>::True True;
98 typedef Cond<true, int, char>::False False;
112 struct Cond { struct in namespace:N7
117 //Cond<true, int*, double> C; // Errors
119 //typedef Cond<true, int*, double>::Type Type; // Errors
120 typedef Cond<tru
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H A Dconstructor-template.cpp60 X2 test(bool Cond, X2 x2) { argument
61 if (Cond)
80 X4 test_X4(bool Cond, X4 x4) { argument
/external/llvm/lib/Target/MBlaze/
H A DMBlazeInstrInfo.cpp118 SmallVectorImpl<MachineOperand> &Cond,
146 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
147 Cond.push_back(LastInst->getOperand(0));
165 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
166 Cond.push_back(SecondLastInst->getOperand(0));
189 const SmallVectorImpl<MachineOperand> &Cond,
193 assert((Cond.size() == 2 || Cond.size() == 0) &&
197 if (!Cond.empty())
198 Opc = (unsigned)Cond[
115 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument
187 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument
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/external/llvm/lib/Target/Mips/
H A DMipsInstrInfo.cpp79 SmallVectorImpl<MachineOperand> &Cond) const {
86 Cond.push_back(MachineOperand::CreateImm(Opc));
89 Cond.push_back(Inst->getOperand(i));
95 SmallVectorImpl<MachineOperand> &Cond,
140 AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
166 AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
174 const SmallVectorImpl<MachineOperand>& Cond)
176 unsigned Opc = Cond[0].getImm();
180 for (unsigned i = 1; i < Cond.size(); ++i)
181 MIB.addReg(Cond[
92 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument
187 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument
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H A DMipsInstrInfo.h41 SmallVectorImpl<MachineOperand> &Cond,
48 const SmallVectorImpl<MachineOperand> &Cond,
52 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
85 SmallVectorImpl<MachineOperand> &Cond) const;
88 const SmallVectorImpl<MachineOperand>& Cond) const;
/external/clang/include/clang/StaticAnalyzer/Core/PathSensitive/
H A DConstraintManager.h67 DefinedSVal Cond,
72 ProgramStatePair assumeDual(ProgramStateRef state, DefinedSVal Cond) { argument
73 ProgramStatePair res(assume(state, Cond, true),
74 assume(state, Cond, false));
/external/clang/lib/StaticAnalyzer/Core/
H A DSimpleConstraintManager.h36 ProgramStateRef assume(ProgramStateRef state, DefinedSVal Cond,
39 ProgramStateRef assume(ProgramStateRef state, Loc Cond, bool Assumption);
41 ProgramStateRef assume(ProgramStateRef state, NonLoc Cond, bool Assumption);
89 Loc Cond,
93 NonLoc Cond,
H A DSimpleConstraintManager.cpp59 DefinedSVal Cond,
61 if (isa<NonLoc>(Cond))
62 return assume(state, cast<NonLoc>(Cond), Assumption);
64 return assume(state, cast<Loc>(Cond), Assumption);
76 Loc Cond, bool Assumption) {
77 switch (Cond.getSubKind()) {
85 const MemRegion *R = cast<loc::MemRegionVal>(Cond).getRegion();
107 bool b = cast<loc::ConcreteInt>(Cond).getValue() != 0;
155 NonLoc Cond,
160 if (!canReasonAbout(Cond)) {
58 assume(ProgramStateRef state, DefinedSVal Cond, bool Assumption) argument
75 assumeAux(ProgramStateRef state, Loc Cond, bool Assumption) argument
154 assumeAux(ProgramStateRef state, NonLoc Cond, bool Assumption) argument
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/external/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.cpp189 SmallVectorImpl<MachineOperand> &Cond,
222 Cond.push_back(MachineOperand::CreateImm(BranchCode));
223 Cond.push_back(LastInst->getOperand(0));
244 Cond.push_back(MachineOperand::CreateImm(BranchCode));
245 Cond.push_back(SecondLastInst->getOperand(0));
277 const SmallVectorImpl<MachineOperand> &Cond,
281 assert((Cond.size() == 2 || Cond.size() == 0) &&
285 if (Cond.empty()) {
290 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[
187 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument
275 InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument
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H A DXCoreInstrInfo.h54 SmallVectorImpl<MachineOperand> &Cond,
59 const SmallVectorImpl<MachineOperand> &Cond,
88 SmallVectorImpl<MachineOperand> &Cond) const;
/external/clang/test/SemaCXX/
H A Dvector.cpp40 void conditional(bool Cond, char16 c16, longlong16 ll16, char16_e c16e, argument
43 __typeof__(Cond? c16 : c16) *c16p1 = &c16;
44 __typeof__(Cond? ll16 : ll16) *ll16p1 = &ll16;
45 __typeof__(Cond? c16e : c16e) *c16ep1 = &c16e;
46 __typeof__(Cond? ll16e : ll16e) *ll16ep1 = &ll16e;
49 __typeof__(Cond? c16 : c16e) *c16ep2 = &c16e;
50 __typeof__(Cond? c16e : c16) *c16ep3 = &c16e;
51 __typeof__(Cond? ll16 : ll16e) *ll16ep2 = &ll16e;
52 __typeof__(Cond? ll16e : ll16) *ll16ep3 = &ll16e;
55 (void)(Cond
108 test_implicit_conversions(bool Cond, char16 c16, longlong16 ll16, char16_e c16e, longlong16_e ll16e, convertible_to<char16> to_c16, convertible_to<longlong16> to_ll16, convertible_to<char16_e> to_c16e, convertible_to<longlong16_e> to_ll16e, convertible_to<char16&> rto_c16, convertible_to<char16_e&> rto_c16e) argument
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/external/llvm/lib/Target/CellSPU/
H A DSPUInstrInfo.h68 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
72 SmallVectorImpl<MachineOperand> &Cond,
79 const SmallVectorImpl<MachineOperand> &Cond,
H A DSPUInstrInfo.cpp211 SmallVectorImpl<MachineOperand> &Cond,
242 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
243 Cond.push_back(LastInst->getOperand(0));
263 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
264 Cond.push_back(SecondLastInst->getOperand(0));
349 const SmallVectorImpl<MachineOperand> &Cond,
353 assert((Cond.size() == 2 || Cond.size() == 0) &&
368 if (Cond.empty()) {
384 MIB = BuildMI(&MBB, DL, get(Cond[
209 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument
347 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument
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/external/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.h74 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
78 SmallVectorImpl<MachineOperand> &Cond,
84 const SmallVectorImpl<MachineOperand> &Cond,
H A DMSP430InstrInfo.cpp127 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
128 assert(Cond.size() == 1 && "Invalid Xbranch condition!");
130 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm());
154 Cond[0].setImm(CC);
172 SmallVectorImpl<MachineOperand> &Cond,
207 Cond.clear();
231 if (Cond.empty()) {
234 Cond.push_back(MachineOperand::CreateImm(BranchCode));
240 assert(Cond.size() == 1);
248 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[
169 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument
260 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument
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H A DMSP430BranchSelector.cpp150 SmallVector<MachineOperand, 1> Cond; local
151 Cond.push_back(I->getOperand(1));
154 TII->ReverseBranchCondition(Cond);
156 .addImm(4).addOperand(Cond[0]);
/external/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp215 SmallVectorImpl<MachineOperand> &Cond,
247 Cond.push_back(LastInst->getOperand(0));
248 Cond.push_back(LastInst->getOperand(1));
257 Cond.push_back(MachineOperand::CreateImm(1));
258 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
268 Cond.push_back(MachineOperand::CreateImm(0));
269 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
293 Cond.push_back(SecondLastInst->getOperand(0));
294 Cond.push_back(SecondLastInst->getOperand(1));
306 Cond
213 AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument
376 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument
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H A DPPCInstrInfo.h114 SmallVectorImpl<MachineOperand> &Cond,
119 const SmallVectorImpl<MachineOperand> &Cond,
145 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
/external/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.h68 SmallVectorImpl<MachineOperand> &Cond,
73 const SmallVectorImpl<MachineOperand> &Cond,
/external/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.h75 SmallVectorImpl<MachineOperand> &Cond,
82 const SmallVectorImpl<MachineOperand> &Cond,
/external/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp1906 ISD::CondCode Cond, bool foldBooleans,
1911 switch (Cond) {
1922 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1935 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1937 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1940 Cond = ISD::SETNE;
1944 Cond = ISD::SETEQ;
1948 Zero, Cond);
1965 if ((Cond
1905 SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, DebugLoc dl) const argument
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/external/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h770 inline bool isTrueWhenEqual(CondCode Cond) { argument
771 return ((int)Cond & 1) != 0;
778 inline unsigned getUnorderedFlavor(CondCode Cond) { argument
779 return ((int)Cond >> 3) & 3;
/external/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.h59 SmallVectorImpl<MachineOperand> &Cond,
66 const SmallVectorImpl<MachineOperand> &Cond,
113 const SmallVectorImpl<MachineOperand> &Cond) const;
133 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;

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