Searched refs:FS (Results 1 - 25 of 130) sorted by relevance

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/external/llvm/lib/Target/XCore/
H A DXCoreSubtarget.cpp27 const std::string &CPU, const std::string &FS)
28 : XCoreGenSubtargetInfo(TT, CPU, FS)
26 XCoreSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS) argument
H A DXCoreSubtarget.h35 const std::string &FS);
39 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
H A DXCoreTargetMachine.cpp24 StringRef CPU, StringRef FS,
28 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
29 Subtarget(TT, CPU, FS),
23 XCoreTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/external/llvm/lib/Target/MSP430/
H A DMSP430Subtarget.cpp28 const std::string &FS) :
29 MSP430GenSubtargetInfo(TT, CPU, FS) {
33 ParseSubtargetFeatures(CPUName, FS);
26 MSP430Subtarget(const std::string &TT, const std::string &CPU, const std::string &FS) argument
H A DMSP430Subtarget.h34 const std::string &FS);
38 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
H A DMSP430TargetMachine.cpp30 StringRef FS,
34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
35 Subtarget(TT, CPU, FS),
27 MSP430TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/external/llvm/lib/Target/Sparc/
H A DSparcSubtarget.cpp27 const std::string &FS, bool is64Bit) :
28 SparcGenSubtargetInfo(TT, CPU, FS),
45 ParseSubtargetFeatures(CPUName, FS);
26 SparcSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS, bool is64Bit) argument
H A DSparcTargetMachine.cpp29 StringRef CPU, StringRef FS,
34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
35 Subtarget(TT, CPU, FS, is64bit),
80 StringRef FS,
85 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
92 StringRef FS,
97 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
28 SparcTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit) argument
78 SparcV8TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
90 SparcV9TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
H A DSparcSubtarget.h35 const std::string &FS, bool is64bit);
43 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
/external/clang/lib/Analysis/
H A DFormatStringParsing.h47 bool ParseLengthModifier(FormatSpecifier &FS, const char *&Beg, const char *E,
51 T FS; member in class:clang::analyze_format_string::SpecifierResult
59 : FS(fs), Start(start), Stop(false) {}
66 return FS;
68 const T &getValue() { return FS; }
/external/llvm/include/llvm/MC/
H A DMCSubtargetInfo.h39 uint64_t FeatureBits; // Feature bits for current CPU + FS
42 void InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS,
63 uint64_t ReInitMCSubtargetInfo(StringRef CPU, StringRef FS);
71 uint64_t ToggleFeature(StringRef FS);
/external/llvm/lib/Target/CellSPU/
H A DSPUSubtarget.cpp26 const std::string &FS) :
27 SPUGenSubtargetInfo(TT, CPU, FS),
37 ParseSubtargetFeatures(default_cpu, FS);
25 SPUSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS) argument
H A DSPUSubtarget.h57 const std::string &FS);
61 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
H A DSPUTargetMachine.cpp35 StringRef CPU, StringRef FS,
39 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
40 Subtarget(TT, CPU, FS),
34 SPUTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/external/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp41 HexagonSubtarget::HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS): argument
42 HexagonGenSubtargetInfo(TT, CPU, FS),
62 ParseSubtargetFeatures(CPUString, FS);
/external/llvm/lib/Target/MBlaze/
H A DMBlazeSubtarget.cpp28 const std::string &FS):
29 MBlazeGenSubtargetInfo(TT, CPU, FS),
37 ParseSubtargetFeatures(CPUName, FS);
26 MBlazeSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS) argument
H A DMBlazeSubtarget.h46 const std::string &FS);
50 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
H A DMBlazeTargetMachine.cpp36 StringRef CPU, StringRef FS, const TargetOptions &Options,
39 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
40 Subtarget(TT, CPU, FS),
35 MBlazeTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/external/llvm/lib/Target/NVPTX/
H A DNVPTXSubtarget.cpp36 const std::string &FS, bool is64Bit)
37 :NVPTXGenSubtargetInfo(TT, "", FS), // Don't pass CPU to subtarget,
47 // Get the TargetName from the FS if available
48 if (FS.empty() && CPU.empty())
35 NVPTXSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS, bool is64Bit) argument
H A DNVPTXTargetMachine.cpp66 StringRef FS,
72 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
73 Subtarget(TT, CPU, FS, is64bit),
84 StringRef CPU, StringRef FS,
88 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
94 StringRef CPU, StringRef FS,
98 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
63 NVPTXTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions& Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit) argument
83 NVPTXTargetMachine32(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
93 NVPTXTargetMachine64(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/external/llvm/lib/MC/
H A DMCSubtargetInfo.cpp23 MCSubtargetInfo::InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS, argument
41 SubtargetFeatures Features(FS);
49 uint64_t MCSubtargetInfo::ReInitMCSubtargetInfo(StringRef CPU, StringRef FS) { argument
50 SubtargetFeatures Features(FS);
65 uint64_t MCSubtargetInfo::ToggleFeature(StringRef FS) { argument
67 FeatureBits = Features.ToggleFeature(FeatureBits, FS,
/external/llvm/lib/Target/CppBackend/
H A DCPPTargetMachine.h26 StringRef CPU, StringRef FS, const TargetOptions &Options,
29 : TargetMachine(T, TT, CPU, FS, Options) {}
25 CPPTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/external/llvm/lib/Target/Mips/
H A DMipsTargetMachine.cpp40 StringRef CPU, StringRef FS, const TargetOptions &Options,
44 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
45 Subtarget(TT, CPU, FS, isLittle, RM),
63 StringRef CPU, StringRef FS, const TargetOptions &Options,
66 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
72 StringRef CPU, StringRef FS, const TargetOptions &Options,
75 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
39 MipsTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle) argument
62 MipsebTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
71 MipselTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
H A DMipsSubtarget.cpp28 const std::string &FS, bool little,
30 MipsGenSubtargetInfo(TT, CPU, FS),
41 ParseSubtargetFeatures(CPUName, FS);
27 MipsSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS, bool little, Reloc::Model RM) argument
/external/llvm/lib/Target/PowerPC/
H A DPPCTargetMachine.cpp36 StringRef CPU, StringRef FS,
41 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
42 Subtarget(TT, CPU, FS, is64Bit),
56 StringRef CPU, StringRef FS,
60 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
66 StringRef CPU, StringRef FS,
70 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
35 PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64Bit) argument
55 PPC32TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
65 PPC64TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument

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