/external/llvm/include/llvm/MC/ |
H A D | MCInstrItineraries.h | 173 unsigned Latency = 0, StartCycle = 0; local 176 Latency = std::max(Latency, StartCycle + IS->getCycles()); 180 return Latency;
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/external/llvm/lib/CodeGen/ |
H A D | ScheduleDAGInstrs.cpp | 242 unsigned DataLatency = SU->Latency; 277 unsigned Latency = local 280 dep.setLatency(Latency); 365 unsigned Latency = SU->Latency; local 367 Latency += SpecialAddressLatency; 371 Latency -= std::min(Latency, Count); 373 ExitSU.addPred(SDep(SU, SDep::Order, Latency, 475 SDep dep(DefSU, SDep::Data, DefSU->Latency, Re 480 unsigned Latency = local 670 unsigned Latency = ((*I)->getInstr()->mayLoad()) ? LatencyToLoad : 0; local [all...] |
H A D | CriticalAntiDepBreaker.cpp | 432 if (!Max || SU->getDepth() + SU->Latency > Max->getDepth() + Max->Latency) 439 << (Max->getDepth() + Max->Latency) << "\n");
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H A D | AggressiveAntiDepBreaker.cpp | 750 ((SU->getDepth() + SU->Latency) > 751 (CriticalPathSU->getDepth() + CriticalPathSU->Latency))) {
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H A D | ScheduleDAG.cpp | 296 dbgs() << " Latency : " << Latency << "\n"; 314 dbgs() << ": Latency=" << I->getLatency(); 334 dbgs() << ": Latency=" << I->getLatency();
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | ScheduleDAGSDNodes.cpp | 92 SU->Latency = Old->Latency; 402 // Assign the Latency field of NodeSUnit using target-provided information. 483 unsigned OpLatency = isChain ? 1 : OpSU->Latency; 591 SU->Latency = 0; 597 SU->Latency = 1; 604 SU->Latency = HighLatencyCycles; 606 SU->Latency = 1; 612 SU->Latency = 0; 615 SU->Latency [all...] |
H A D | ScheduleDAGVLIW.cpp | 242 if (FoundSUnit->Latency) // Don't increment CurCycle for pseudo-ops!
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H A D | ScheduleDAGFast.cpp | 334 AddPred(NewSU, SDep(LoadSU, SDep::Order, LoadSU->Latency)); 411 AddPred(CopyFromSU, SDep(SU, SDep::Data, SU->Latency, Reg)); 412 AddPred(CopyToSU, SDep(CopyFromSU, SDep::Data, CopyFromSU->Latency, 0)); 589 AddPred(TrySU, SDep(Copies.front(), SDep::Order, /*Latency=*/1, 598 AddPred(NewDef, SDep(TrySU, SDep::Order, /*Latency=*/1,
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H A D | ScheduleDAGRRList.cpp | 1061 AddPred(NewSU, SDep(LoadSU, SDep::Data, LoadSU->Latency)); 1143 SDep D(CopyFromSU, SDep::Order, /*Latency=*/0, 1152 AddPred(CopyFromSU, SDep(SU, SDep::Data, SU->Latency, Reg)); 1153 AddPred(CopyToSU, SDep(CopyFromSU, SDep::Data, CopyFromSU->Latency, 0)); 1362 AddPred(TrySU, SDep(BtSU, SDep::Order, /*Latency=*/1, 1416 AddPred(TrySU, SDep(Copies.front(), SDep::Order, /*Latency=*/1, 1426 AddPred(NewDef, SDep(TrySU, SDep::Order, /*Latency=*/1, 2356 if (left->Latency != right->Latency) 2357 return left->Latency > righ [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | ScheduleDAG.h | 84 /// Latency - The time associated with this edge. Often this is just 85 /// the value of the Latency field of the predecessor, however advanced 87 unsigned Latency; member in class:llvm::SDep 88 /// Record MinLatency seperately from "expected" Latency. 101 : Dep(S, kind), Contents(), Latency(latency), MinLatency(latency) { 141 && Latency == Other.Latency && MinLatency == Other.MinLatency; 153 return Latency; 158 Latency = Lat; 273 unsigned short Latency; // Nod member in class:llvm::SUnit [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMBaseInstrInfo.cpp | 2960 unsigned Latency = getInstrLatency(ItinData, DefMI); local 2966 if (Latency > 0 && Subtarget.isThumb2()) { 2969 --Latency; 2971 return Latency; 2983 int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign, local 2986 if (Latency < 0) 2987 return Latency; 2994 if (Adj >= 0 || (int)Latency > -Adj) { 2995 return Latency + Adj; 2998 return Latency; 3017 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx); local 3031 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign, local 3210 unsigned Latency = 0; local 3238 unsigned Latency = ItinData->getStageLatency(Class); local 3281 int Latency = computeOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx, local [all...] |
/external/oprofile/events/mips/1004K/ |
H A D | events | 95 event:0x3d counters:0 um:zero minimum:500 name:SELF_INTERVENTION_LATENCY : 61-0 Latency from miss detection to self intervention
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/external/blktrace/btt/doc/ |
H A D | btt.tex | 463 \item[iostat] Latency information -- both Q2d, D2c and Q2C -- 676 \newpage\section{\label{sec:lat}\label{sec:lat-q2d}\label{sec:lat-q2c}\label{sec:lat-d2c}Latency Data Files}
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