Searched refs:RegInfo (Results 1 - 25 of 44) sorted by relevance

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/external/llvm/lib/Target/ARM/
H A DThumb1FrameLowering.cpp51 const Thumb1RegisterInfo *RegInfo = local
60 unsigned FramePtr = RegInfo->getFrameRegister(MF);
61 unsigned BasePtr = RegInfo->getBaseRegister();
73 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -VARegSaveSize,
78 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
146 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
159 if (RegInfo->needsStackRealignment(MF))
166 if (RegInfo->hasBasePointer(MF))
209 const Thumb1RegisterInfo *RegInfo = local
216 const uint16_t *CSRegs = RegInfo
[all...]
H A DARMFrameLowering.cpp44 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); local
54 RegInfo->needsStackRealignment(MF) ||
137 const ARMBaseRegisterInfo *RegInfo = local
148 unsigned FramePtr = RegInfo->getFrameRegister(MF);
291 if (!AFI->getNumAlignedDPRCS2Regs() && RegInfo->needsStackRealignment(MF)) {
325 if (RegInfo->hasBasePointer(MF)) {
328 TII.get(ARM::MOVr), RegInfo->getBaseRegister())
333 RegInfo->getBaseRegister())
352 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); local
361 unsigned FramePtr = RegInfo
491 const ARMBaseRegisterInfo *RegInfo = local
1044 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); local
1166 const ARMBaseRegisterInfo *RegInfo = local
1206 const ARMBaseRegisterInfo *RegInfo = local
[all...]
/external/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.h29 const NVPTXRegisterInfo RegInfo; member in class:llvm::NVPTXInstrInfo
33 virtual const NVPTXRegisterInfo &getRegisterInfo() const { return RegInfo; }
H A DVectorElementize.cpp65 const NVPTXRegisterInfo *RegInfo; member in class:__anon8956::VectorElementize
613 if (!RegInfo->isVirtualRegister(oper.getReg())) continue;
623 if (!RegInfo->isVirtualRegister(defSrc.getReg())) continue;
642 if (!(RegInfo->isVirtualRegister(oper.getReg())))
650 if (!(RegInfo->isVirtualRegister(defSrc.getReg())))
687 assert(RegInfo->isVirtualRegister(dest.getReg()) &&
708 RegInfo = TM.getRegisterInfo();
/external/llvm/lib/CodeGen/
H A DMachineFunction.cpp57 RegInfo = new (Allocator) MachineRegisterInfo(*TM.getRegisterInfo());
59 RegInfo = 0;
79 if (RegInfo) {
80 RegInfo->~MachineRegisterInfo();
81 Allocator.Deallocate(RegInfo);
300 if (RegInfo) {
301 OS << (RegInfo->isSSA() ? "SSA" : "Post SSA");
302 if (!RegInfo->tracksLiveness())
319 if (RegInfo && !RegInfo
[all...]
H A DMachineInstr.cpp133 MachineRegisterInfo *RegInfo = 0; local
137 RegInfo = &MF->getRegInfo();
141 if (RegInfo && WasReg)
142 RegInfo->removeRegOperandFromUseList(this);
164 if (RegInfo)
165 RegInfo->addRegOperandToUseList(this);
667 MachineRegisterInfo *RegInfo = getRegInfo(); local
670 // be removed and re-added to RegInfo. It is storing pointers to operands.
671 bool Reallocate = RegInfo &&
678 // Remove all the implicit operands from RegInfo i
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H A DPrologEpilogInserter.cpp153 const TargetRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo(); local
200 RegInfo->eliminateCallFramePseudoInstr(Fn, *I->getParent(), I);
208 const TargetRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo(); local
213 const uint16_t *CSRegs = RegInfo->getCalleeSavedRegs(&Fn);
248 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg);
251 if (RegInfo->hasReservedSpillSlot(Fn, Reg, FrameIdx)) {
560 const TargetRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo(); local
561 if (RS && TFI.hasFP(Fn) && RegInfo->useFPForScavengingIndex(Fn) &&
562 !RegInfo->needsStackRealignment(Fn)) {
644 if (RS && (!TFI.hasFP(Fn) || RegInfo
[all...]
H A DMachineInstrBundle.cpp251 MachineOperandIteratorBase::RegInfo
254 RegInfo RI = { false, false, false };
/external/llvm/lib/Target/X86/
H A DX86FrameLowering.cpp48 const TargetRegisterInfo *RegInfo = TM.getRegisterInfo(); local
51 RegInfo->needsStackRealignment(MF) ||
497 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
498 unsigned FramePtr = RegInfo->getFrameRegister(MF);
499 unsigned StackPtr = RegInfo->getStackRegister();
637 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
650 unsigned SlotSize = RegInfo->getSlotSize();
651 unsigned FramePtr = RegInfo->getFrameRegister(MF);
652 unsigned StackPtr = RegInfo->getStackRegister();
653 unsigned BasePtr = RegInfo
[all...]
/external/llvm/include/llvm/CodeGen/
H A DMachineInstrBundle.h133 /// RegInfo - Information about a virtual register used by a set of operands.
135 struct RegInfo { struct in class:llvm::MachineOperandIteratorBase
156 /// @returns A filled-in RegInfo struct.
157 RegInfo analyzeVirtReg(unsigned Reg,
H A DMachineFunction.h81 // RegInfo - Information about each register in use in the function.
82 MachineRegisterInfo *RegInfo; member in class:llvm::MachineFunction
160 MachineRegisterInfo &getRegInfo() { return *RegInfo; }
161 const MachineRegisterInfo &getRegInfo() const { return *RegInfo; }
H A DMachineInstr.h839 const TargetRegisterInfo &RegInfo);
846 const TargetRegisterInfo *RegInfo,
849 /// clearRegisterKills - Clear all kill flags affecting Reg. If RegInfo is
851 void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo);
857 bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo,
863 const TargetRegisterInfo *RegInfo = 0);
H A DFunctionLoweringInfo.h59 MachineRegisterInfo *RegInfo; member in class:llvm::FunctionLoweringInfo
H A DSelectionDAGISel.h49 MachineRegisterInfo *RegInfo; member in class:llvm::SelectionDAGISel
/external/llvm/lib/Target/Mips/
H A DMipsSEFrameLowering.cpp34 const MipsRegisterInfo *RegInfo = local
90 MachineLocation SrcML0(RegInfo->getSubReg(Reg, Mips::sub_fpeven));
91 MachineLocation SrcML1(RegInfo->getSubReg(Reg, Mips::sub_fpodd));
H A DMipsISelLowering.cpp1042 MachineRegisterInfo &RegInfo = MF->getRegInfo(); local
1069 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1070 unsigned AndRes = RegInfo.createVirtualRegister(RC);
1071 unsigned Success = RegInfo.createVirtualRegister(RC);
1130 MachineRegisterInfo &RegInfo = MF->getRegInfo(); local
1141 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1142 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1143 unsigned Mask = RegInfo.createVirtualRegister(RC);
1144 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1145 unsigned NewVal = RegInfo
1282 MachineRegisterInfo &RegInfo = MF->getRegInfo(); local
1365 MachineRegisterInfo &RegInfo = MF->getRegInfo(); local
[all...]
H A DMipsISelDAGToDAG.cpp125 MachineRegisterInfo &RegInfo = MF.getRegInfo(); local
138 V0 = RegInfo.createVirtualRegister(RC);
139 V1 = RegInfo.createVirtualRegister(RC);
140 V2 = RegInfo.createVirtualRegister(RC);
/external/llvm/lib/Target/MBlaze/
H A DMBlazeInstrInfo.cpp287 MachineRegisterInfo &RegInfo = MF->getRegInfo(); local
290 GlobalBaseReg = RegInfo.createVirtualRegister(&MBlaze::GPRRegClass);
293 RegInfo.addLiveIn(MBlaze::R20);
/external/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp41 MCDisassembler(STI), RegInfo(Info), isBigEndian(bigEndian) {}
48 const MCRegisterInfo *getRegInfo() const { return RegInfo; }
51 const MCRegisterInfo *RegInfo; member in class:__anon8943::MipsDisassemblerBase
/external/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp191 for (unsigned i = 0, e = RegInfo->getNumVirtRegs(); i != e; ++i) {
193 if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) {
212 unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
213 unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
258 GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
262 GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::G8RCRegClass);
H A DPPCISelLowering.cpp4810 MachineRegisterInfo &RegInfo = F->getRegInfo(); local
4812 RegInfo.createVirtualRegister(
4879 MachineRegisterInfo &RegInfo = F->getRegInfo(); local
4883 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
4884 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
4885 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
4886 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
4887 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
4888 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
4889 unsigned Mask3Reg = RegInfo
5227 MachineRegisterInfo &RegInfo = F->getRegInfo(); local
[all...]
/external/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.cpp347 MachineRegisterInfo &RegInfo = MF->getRegInfo(); local
349 GlobalBaseReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
/external/llvm/lib/Target/XCore/
H A DXCoreFrameLowering.cpp341 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); local
360 if (RegInfo->requiresRegisterScavenging(MF)) {
/external/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGISel.cpp348 RegInfo = &MF->getRegInfo();
373 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
377 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
378 E = RegInfo->livein_end(); LI != E; ++LI)
389 MachineInstr *Def = RegInfo->getVRegDef(Reg);
398 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
414 UI = RegInfo->use_begin(LDI->second);
859 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg);
860 if (RI == RegInfo->reg_end())
868 if (PostRI != RegInfo
[all...]
H A DFunctionLoweringInfo.cpp65 RegInfo = &MF->getRegInfo();
212 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));

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