Searched refs:SETCC (Results 1 - 25 of 26) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h349 SETCC, enumerator in enum:llvm::ISD::NodeType
H A DSelectionDAG.h614 return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond));
/external/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h31 SETCC, enumerator in enum:llvm::HexagonISD::__anon8900
H A DHexagonISelDAGToDAG.cpp819 if (N0.getOpcode() == ISD::SETCC) {
H A DHexagonISelLowering.cpp935 SDValue Cond = DAG.getNode(ISD::SETCC, dl, MVT::i1, LHS, RHS, CC);
1318 // Lower SELECT_CC to SETCC and SELECT.
/external/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.h52 SETCC, enumerator in enum:llvm::MSP430ISD::__anon8933
H A DMSP430ISelLowering.cpp112 setOperationAction(ISD::SETCC, MVT::i8, Custom);
113 setOperationAction(ISD::SETCC, MVT::i16, Custom);
189 case ISD::SETCC: return LowerSETCC(Op, DAG);
/external/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp200 case ISD::SETCC:
271 else if (Node->getOpcode() == ISD::SETCC)
606 Ops[i] = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(TmpEltVT),
H A DLegalizeVectorTypes.cpp64 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
308 // Turn it into a scalar SETCC.
309 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
335 // Turn it into a scalar SETCC.
336 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
492 case ISD::SETCC:
1024 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break;
1235 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
1236 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
1298 case ISD::SETCC
[all...]
H A DDAGCombiner.cpp538 if (N.getOpcode() == ISD::SETCC) {
1122 case ISD::SETCC: return visitSETCC(N);
3370 case ISD::SETCC:
4101 if (N0.getOpcode() == ISD::SETCC) {
4142 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC)
4179 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
4180 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
4242 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0),
4403 if (N0.getOpcode() == ISD::SETCC) {
8508 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), local
[all...]
H A DLegalizeFloatTypes.cpp591 case ISD::SETCC: Res = SoftenFloatOp_SETCC(N); break;
611 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
686 SDValue Tmp = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(RetVT),
689 NewLHS = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(RetVT), NewLHS,
1270 case ISD::SETCC: Res = ExpandFloatOp_SETCC(N); break;
1292 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
H A DSelectionDAGDumper.cpp187 case ISD::SETCC: return "setcc";
H A DLegalizeDAG.cpp1183 case ISD::SETCC:
1186 Node->getOpcode() == ISD::SETCC ? 2 : 1;
1575 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
1576 /// condition code CC on the current target. This routine expands SETCC with
1577 /// illegal condition code into AND / OR of multiple SETCC values.
3351 if (Tmp1.getOpcode() == ISD::SETCC) {
3398 if (Tmp2.getOpcode() == ISD::SETCC) {
3415 case ISD::SETCC: {
3421 // If we expanded the SETCC into an AND/OR, return the new node
3427 // Otherwise, SETCC fo
[all...]
H A DTargetLowering.cpp2003 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
2108 (isOperationLegal(ISD::SETCC, newVT) &&
2150 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
2151 if (N0.getOpcode() == ISD::SETCC &&
2199 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
2200 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
H A DLegalizeIntegerTypes.cpp70 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
524 // Get the SETCC result using the canonical SETCC type.
776 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
809 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
2449 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
2482 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
2551 Tmp2 = DAG.getNode(ISD::SETCC, dl,
H A DSelectionDAG.cpp1816 case ISD::SETCC:
2222 case ISD::SETCC:
3216 case ISD::SETCC: {
3217 // Use FoldSetCC to simplify SETCC's.
/external/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp449 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
450 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
451 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
452 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
453 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
454 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
457 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
759 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
868 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
869 setOperationAction(ISD::SETCC, MV
[all...]
H A DX86ISelLowering.h91 SETCC, enumerator in enum:llvm::X86ISD::NodeType
93 // Same as SETCC except it's materialized with a sbb and the value is all
97 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
531 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
/external/llvm/lib/Target/CellSPU/
H A DSPUISelLowering.cpp321 setOperationAction(ISD::SETCC, MVT::i8, Legal);
322 setOperationAction(ISD::SETCC, MVT::i16, Legal);
323 setOperationAction(ISD::SETCC, MVT::i32, Legal);
324 setOperationAction(ISD::SETCC, MVT::i64, Legal);
325 setOperationAction(ISD::SETCC, MVT::f64, Custom);
513 // Return the Cell SPU's SETCC result type
517 // i8, i16 and i32 are valid SETCC result types
2511 //! Lower ISD::SETCC
2665 // legalizer insists on combining SETCC/SELECT into SELECT_CC, so we end up
2668 SDValue compare = DAG.getNode(ISD::SETCC, d
[all...]
/external/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp739 setOperationAction(ISD::SETCC, MVT::i32, Expand);
740 setOperationAction(ISD::SETCC, MVT::f32, Expand);
741 setOperationAction(ISD::SETCC, MVT::f64, Expand);
/external/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp144 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
157 setOperationAction(ISD::SETCC, MVT::f32, Custom);
158 setOperationAction(ISD::SETCC, MVT::f64, Custom);
576 // must be a SETCC node
577 if (Op.getOpcode() != ISD::SETCC)
615 if ((SetCC.getOpcode() != ISD::SETCC) ||
801 case ISD::SETCC: return LowerSETCC(Op, DAG);
1545 SDValue Cond = DAG.getNode(ISD::SETCC, DL, getSetCCResultType(Ty),
/external/llvm/lib/Target/MBlaze/
H A DMBlazeISelLowering.cpp142 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
/external/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp834 case ISD::SETCC:
/external/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp105 setOperationAction(ISD::SETCC, VT, Custom);
484 // FIXME: Code duplication: SETCC has custom operation action, see
486 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
530 setOperationAction(ISD::SETCC, MVT::v1i64, Expand);
531 setOperationAction(ISD::SETCC, MVT::v2i64, Expand);
743 setOperationAction(ISD::SETCC, MVT::i32, Expand);
744 setOperationAction(ISD::SETCC, MVT::f32, Expand);
745 setOperationAction(ISD::SETCC, MVT::f64, Expand);
5247 case ISD::SETCC: return LowerVSETCC(Op, DAG);
/external/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp216 SDValue Cond = DAG.getNode(ISD::SETCC, dl, MVT::i32, Op.getOperand(2),

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