| /external/llvm/lib/Target/ARM/ |
| H A D | Thumb1InstrInfo.h | 48 unsigned SrcReg, bool isKill, int FrameIndex,
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| H A D | Thumb2InstrInfo.h | 50 unsigned SrcReg, bool isKill, int FrameIndex,
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| H A D | Thumb1InstrInfo.cpp | 53 unsigned SrcReg, bool isKill, int FI,
74 .addReg(SrcReg, getKillRegState(isKill))
52 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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| H A D | Thumb1FrameLowering.cpp | 308 bool isKill = true; local
317 isKill = false;
320 if (isKill)
323 MIB.addReg(Reg, getKillRegState(isKill));
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| H A D | ARMLoadStoreOptimizer.cpp | 82 bool isKill; member in struct:__anon8843::ARMLoadStoreOpt::MemOpQueueEntry
88 : Offset(o), Reg(r), isKill(k), Position(p), MBBI(i), Merged(false) {}
386 if (memOps[i].Position < insertPos && memOps[i].isKill) {
399 bool isKill = memOps[i].isKill || KilledRegs.count(Reg); local
400 Regs.push_back(std::make_pair(Reg, isKill));
430 memOps[j].isKill = false;
432 memOps[i].isKill = true;
716 bool BaseKill = MI->getOperand(0).isKill();
852 bool BaseKill = MI->getOperand(1).isKill();
1247 bool isKill = MO.isDef() ? false : MO.isKill(); local
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.h | 72 unsigned SrcReg, bool isKill, int FrameIdx,
128 unsigned SrcReg, bool isKill, int FrameIndex,
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| H A D | PPCInstrInfo.cpp | 161 bool Reg1IsKill = MI->getOperand(1).isKill();
162 bool Reg2IsKill = MI->getOperand(2).isKill();
444 unsigned SrcReg, bool isKill,
453 getKillRegState(isKill)),
462 getKillRegState(isKill)),
469 getKillRegState(isKill)),
478 getKillRegState(isKill)),
484 getKillRegState(isKill)),
489 getKillRegState(isKill)),
496 getKillRegState(isKill)),
443 StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const argument
587 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
[all...] |
| /external/llvm/lib/CodeGen/ |
| H A D | MachineInstrBundle.cpp | 137 if (MO.isKill())
146 if (MO.isKill())
197 bool isKill = KilledUseSet.count(Reg); local
199 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) |
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| H A D | TwoAddressInstructionPass.cpp | 228 if (!UseMO.isKill())
270 if (MO.isKill()) {
772 if (MO.isKill() && MOReg != Reg)
821 ((MO.isKill() && Uses.count(MOReg)) || Kills.count(MOReg)))
824 if (MOReg == Reg && !MO.isKill())
923 if (MOReg == Reg && !MO.isKill())
926 if (MO.isKill() && MOReg != Reg)
966 if (OtherMI != MI && MOReg == Reg && !MO.isKill())
1148 NewMIs[1]->getOperand(NewSrcIdx).isKill()) {
1157 if (MO.isKill()) {
1702 bool isKill = MI->getOperand(i).isKill(); local
[all...] |
| H A D | ExpandPostRAPseudos.cpp | 132 MI->getOperand(2).isKill());
172 DstMO.getReg(), SrcMO.getReg(), SrcMO.isKill());
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| H A D | MachineInstr.cpp | 131 bool isKill, bool isDead, bool isUndef,
150 IsKill = isKill;
269 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
290 if (isKill()) {
883 if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
1057 /// the search criteria to a use that kills the register if isKill is true.
1058 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
1072 if (!isKill || MO.isKill())
130 ChangeToRegister(unsigned Reg, bool isDef, bool isImp, bool isKill, bool isDead, bool isUndef, bool isDebug) argument
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| H A D | SPUInstrInfo.h | 55 unsigned SrcReg, bool isKill, int FrameIndex,
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| /external/llvm/lib/Target/MSP430/ |
| H A D | MSP430InstrInfo.h | 61 unsigned SrcReg, bool isKill,
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| H A D | MSP430InstrInfo.cpp | 36 unsigned SrcReg, bool isKill, int FrameIdx,
53 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
57 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
34 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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| /external/llvm/lib/Target/Mips/ |
| H A D | Mips16InstrInfo.h | 53 unsigned SrcReg, bool isKill, int FrameIndex,
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| H A D | MipsSEInstrInfo.h | 54 unsigned SrcReg, bool isKill, int FrameIndex,
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| H A D | Mips16InstrInfo.cpp | 84 unsigned SrcReg, bool isKill, int FI,
83 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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| /external/llvm/lib/Target/Sparc/ |
| H A D | SparcInstrInfo.h | 92 unsigned SrcReg, bool isKill, int FrameIndex,
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| H A D | SparcInstrInfo.cpp | 299 unsigned SrcReg, bool isKill, int FI,
308 .addReg(SrcReg, getKillRegState(isKill));
311 .addReg(SrcReg, getKillRegState(isKill));
314 .addReg(SrcReg, getKillRegState(isKill));
298 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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| /external/llvm/lib/Target/XCore/ |
| H A D | XCoreInstrInfo.h | 71 unsigned SrcReg, bool isKill, int FrameIndex,
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| H A D | XCoreRegisterInfo.cpp | 211 bool isKill = MI.getOpcode() == XCore::STWFI && MI.getOperand(0).isKill(); local
235 .addReg(Reg, getKillRegState(isKill))
256 .addReg(Reg, getKillRegState(isKill))
285 .addReg(Reg, getKillRegState(isKill))
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| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.h | 76 unsigned SrcReg, bool isKill, int FrameIndex,
80 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
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| H A D | HexagonNewValueJump.cpp | 413 // if(!jmpInstr->getOperand(0).isKill()) break;
476 if (MI->getOperand(1).isKill())
481 if (MI->getOperand(2).isKill())
564 localMO.isKill() && feederReg == localMO.getReg()) {
626 cmpInstr->getOperand(0).isKill())
629 cmpInstr->getOperand(1).isKill())
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| /external/llvm/lib/Target/X86/ |
| H A D | X86InstrBuilder.h | 108 unsigned Reg, bool isKill, int Offset) {
109 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
107 addRegOffset(const MachineInstrBuilder &MIB, unsigned Reg, bool isKill, int Offset) argument
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| /external/llvm/include/llvm/CodeGen/ |
| H A D | MachineOperand.h | 287 bool isKill() const { function in class:llvm::MachineOperand
513 /// operand. Note: This method ignores isKill and isDead properties.
532 bool isKill = false, bool isDead = false,
558 bool isKill = false, bool isDead = false,
567 Op.IsKill = isKill;
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