/external/llvm/lib/Target/PowerPC/ |
H A D | PPCCTRLoops.cpp | 66 const TargetInstrInfo *TII; member in struct:__anon9758::PPCCTRLoops 233 TII = MF.getTarget().getInstrInfo(); 692 TII->get(CopyOp), CountReg).addReg(TripCount->getReg()); 697 TII->get(isPPC64 ? PPC::NEG8 : PPC::NEG), 711 TII->get(isPPC64 ? PPC::LIS8 : PPC::LIS), 716 TII->get(isPPC64 ? PPC::ORI8 : PPC::ORI), 720 TII->get(isPPC64 ? PPC::LI8 : PPC::LI), 727 TII->get(isPPC64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(CountReg, 757 TII->get((BranchTarget == LoopStart) ?
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H A D | PPCHazardRecognizers.cpp | 75 : TII(tii) { 94 const MCInstrDesc &MCID = TII.get(Opcode);
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/external/llvm/lib/CodeGen/ |
H A D | TailDuplication.cpp | 62 const TargetInstrInfo *TII; member in class:__anon9543::TailDuplicatePass 131 TII = MF.getTarget().getInstrInfo(); 424 MachineInstr *NewMI = TII->duplicate(MI, MF); 654 if (TII->AnalyzeBranch(*PredBB, PredTBB, PredFBB, PredCond, true)) 685 if (TII->AnalyzeBranch(*PredBB, PredTBB, PredFBB, PredCond, true)) 723 TII->RemoveBranch(*PredBB); 726 TII->InsertBranch(*PredBB, PredTBB, PredFBB, PredCond, DebugLoc()); 773 if (TII->AnalyzeBranch(*PredBB, PredTBB, PredFBB, PredCond, true)) 787 TII->RemoveBranch(*PredBB); 828 TII [all...] |
H A D | DFAPacketizer.cpp | 131 TII = TM.getInstrInfo(); 132 ResourceTracker = TII->CreateTargetScheduleState(&TM, 0);
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H A D | OptimizePHIs.cpp | 32 const TargetInstrInfo *TII; member in class:__anon9493::OptimizePHIs 65 TII = Fn.getTarget().getInstrInfo();
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H A D | AggressiveAntiDepBreaker.h | 120 const TargetInstrInfo *TII; member in class:llvm::AggressiveAntiDepBreaker
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H A D | MachineRegisterInfo.cpp | 62 const TargetInstrInfo *TII = TM.getInstrInfo(); local 74 I->getRegClassConstraint(I.getOperandNo(), TII, TRI); 310 const TargetInstrInfo &TII) { 325 TII.get(TargetOpcode::COPY), LiveIns[i].second) 308 EmitLiveInCopies(MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII) argument
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H A D | RegisterScavenging.cpp | 72 TII = TM.getInstrInfo(); 138 bool isPred = TII->isPredicated(MI); 375 TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC,TRI); 382 TII->loadRegFromStackSlot(*MBB, UseMI, SReg, ScavengingFrameIndex, RC, TRI);
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H A D | VirtRegMap.cpp | 54 TII = mf.getTarget().getInstrInfo(); 157 const TargetInstrInfo *TII; member in class:__anon9547::VirtRegRewriter 205 TII = TM->getInstrInfo(); 348 MI->setDesc(TII->get(TargetOpcode::KILL));
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H A D | InlineSpiller.cpp | 64 const TargetInstrInfo &TII; member in class:__anon9463::InlineSpiller 148 TII(*mf.getTarget().getInstrInfo()), 248 if (SnipLI.reg == TII.isLoadFromStackSlot(MI, FI) && FI == StackSlot) 252 if (SnipLI.reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot) 603 if (Reg == TII.isLoadFromStackSlot(MI, FI) && FI == StackSlot) { 725 TII.storeRegToStackSlot(*MBB, MII, SVI.SpillReg, false, StackSlot, 782 if (Reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot) { 785 MI->setDesc(TII.get(TargetOpcode::KILL)); 981 unsigned InstrReg = TII.isLoadFromStackSlot(MI, FI); 984 InstrReg = TII [all...] |
H A D | MachineSink.cpp | 46 const TargetInstrInfo *TII; member in class:__anon9488::MachineSinking 225 TII = TM.getInstrInfo(); 506 if (!TII->isSafeToMoveRegClassDefs(MRI->getRegClass(Reg))) 584 if (!MI->isSafeToMove(TII, AA, SawStore)) 626 if (!MI->isSafeToMove(TII, AA, store)) {
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H A D | PrologEpilogInserter.cpp | 141 const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo(); local 149 int FrameSetupOpcode = TII.getCallFrameSetupOpcode(); 150 int FrameDestroyOpcode = TII.getCallFrameDestroyOpcode(); 288 const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo(); local 305 TII.storeRegToStackSlot(*EntryBlock, I, Reg, true, 332 TII.loadRegFromStackSlot(*MBB, I, Reg, 380 TII.storeRegToStackSlot(*MBB, I, Reg, 431 TII.loadRegFromStackSlot(*MBB, I, Reg, 712 const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo(); local 717 int FrameSetupOpcode = TII [all...] |
H A D | ExecutionDepsFix.cpp | 131 const TargetInstrInfo *TII; member in class:__anon9457::ExeDepsFix 301 TII->setExecutionDomain(dv->Instrs.pop_back_val(), domain); 438 std::pair<uint16_t, uint16_t> DomP = TII->getExecutionDomain(MI); 483 unsigned Pref = TII->getPartialRegUpdateClearance(MI, i, TRI); 489 TII->breakPartialRegDependency(MI, i, TRI); 568 TII->setExecutionDomain(mi, domain); 647 TII = MF->getTarget().getInstrInfo();
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H A D | MachineLICM.cpp | 64 const TargetInstrInfo *TII; member in class:__anon9479::MachineLICM 324 TII = TM->getInstrInfo(); 484 (TII->isLoadFromStackSlot(MI, FI) && MFI->isSpillSlotObjectIndex(FI))) 806 if (!TII->AnalyzeBranch(*BB, TBB, FBB, Cond, false) && Cond.empty()) 897 if (!I.isSafeToMove(TII, AA, DontMoveAcrossStore)) 1029 if (TII->hasHighOperandLatency(InstrItins, MRI, &MI, DefIdx, UseMI, i)) 1059 if (!TII->hasLowDefLatency(InstrItins, &MI, i)) 1171 if (TII->isTriviallyReMaterializable(&MI, AA)) 1233 if (!TII->isTriviallyReMaterializable(&MI, AA) && 1256 TII [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | ScheduleDAGRRList.cpp | 276 const TargetInstrInfo *TII, 306 const MCInstrDesc Desc = TII->get(Opcode); 307 const TargetRegisterClass *RC = TII->getRegClass(Desc, Idx, TRI, MF); 408 const TargetInstrInfo *TII) { 418 if (IsChainDependent(N->getOperand(i).getNode(), Inner, NestLevel, TII)) 425 (unsigned)TII->getCallFrameDestroyOpcode()) { 428 (unsigned)TII->getCallFrameSetupOpcode()) { 458 const TargetInstrInfo *TII) { 470 MyNestLevel, MyMaxNest, TII)) 483 (unsigned)TII 274 GetCostForDef(const ScheduleDAGSDNodes::RegDefIter &RegDefPos, const TargetLowering *TLI, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, unsigned &RegClass, unsigned &Cost, const MachineFunction &MF) argument 406 IsChainDependent(SDNode *Outer, SDNode *Inner, unsigned NestLevel, const TargetInstrInfo *TII) argument 457 FindCallSeqStart(SDNode *N, unsigned &NestLevel, unsigned &MaxNest, const TargetInstrInfo *TII) argument 1190 getPhysicalRegisterVT(SDNode *N, unsigned Reg, const TargetInstrInfo *TII) argument [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | A15SDOptimizer.cpp | 61 const ARMBaseInstrInfo *TII; member in struct:__anon9652::A15SDOptimizer 440 TII->get(QPR ? ARM::VDUPLN32q : ARM::VDUPLN32d), 459 TII->get(TargetOpcode::COPY), Out) 475 TII->get(TargetOpcode::REG_SEQUENCE), Out) 494 TII->get(ARM::VEXTd32), Out) 510 TII->get(TargetOpcode::INSERT_SUBREG), Out) 526 TII->get(TargetOpcode::IMPLICIT_DEF), Out); 673 TII = static_cast<const ARMBaseInstrInfo*>(Fn.getTarget().getInstrInfo());
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H A D | ARMInstrInfo.cpp | 124 const TargetInstrInfo &TII = *TM->getInstrInfo(); local 126 TII.get(Opc), GlobalBaseReg)
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H A D | Thumb2ITBlockPass.cpp | 31 const Thumb2InstrInfo *TII; member in class:__anon9693::Thumb2ITBlockPass 181 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT)) 251 TII = static_cast<const Thumb2InstrInfo*>(TM.getInstrInfo());
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H A D | ARMLoadStoreOptimizer.cpp | 65 const TargetInstrInfo *TII; member in struct:__anon9669::ARMLoadStoreOpt 124 const TargetInstrInfo *TII, 338 BuildMI(MBB, MBBI, dl, TII->get(BaseOpc), NewBase) 349 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(Opcode)) 777 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(NewOpc)) 847 const TargetInstrInfo *TII, 930 BuildMI(MBB, MBBI, dl, TII->get(NewOpc)) 941 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg()) 946 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg()) 953 BuildMI(MBB, MBBI, dl, TII 845 MergeBaseUpdateLoadStore(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const TargetInstrInfo *TII, bool &Advance, MachineBasicBlock::iterator &I) argument 1072 InsertLDR_STR(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, int Offset, bool isDef, DebugLoc dl, unsigned NewOpc, unsigned Reg, bool RegDeadKill, bool RegUndef, unsigned BaseReg, bool BaseKill, bool BaseUndef, bool OffKill, bool OffUndef, ARMCC::CondCodes Pred, unsigned PredReg, const TargetInstrInfo *TII, bool isT2) argument 1451 const TargetInstrInfo *TII; member in struct:__anon9670::ARMPreAllocLoadStoreOpt [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | DFAPacketizer.h | 96 const TargetInstrInfo *TII; member in class:llvm::VLIWPacketizerList
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H A D | RegisterScavenging.h | 33 const TargetInstrInfo *TII; member in class:llvm::RegScavenger
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H A D | ResourcePriorityQueue.h | 62 const TargetInstrInfo *TII; member in class:llvm::ResourcePriorityQueue
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/external/llvm/lib/Target/R600/ |
H A D | R600ISelLowering.h | 43 const R600InstrInfo * TII; member in class:llvm::R600TargetLowering
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/external/llvm/lib/Target/MBlaze/ |
H A D | MBlazeDelaySlotFiller.cpp | 42 const TargetInstrInfo *TII; member in struct:__anon9714::Filler 46 : MachineFunctionPass(ID), TM(tm), TII(tm.getInstrInfo()) { } 242 BuildMI(MBB, ++J, I->getDebugLoc(), TII->get(MBlaze::NOP));
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/external/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 1077 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local 1134 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0); 1138 BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr); 1139 BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes); 1142 BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr); 1146 BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0); 1147 BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB); 1165 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local 1225 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2) 1227 BuildMI(BB, DL, TII 1317 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local 1400 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local [all...] |