| /external/llvm/lib/CodeGen/ |
| H A D | TargetInstrInfo.cpp | 439 const TargetInstrInfo &TII = *TM.getInstrInfo(); local
458 if (TII.isLoadFromStackSlot(MI, FrameIdx) &&
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| H A D | SplitKit.cpp | 49 TII(*MF.getTarget().getInstrInfo()),
332 TII(*vrm.getMachineFunction().getTarget().getInstrInfo()),
448 CopyMI = BuildMI(MBB, I, DebugLoc(), TII.get(TargetOpcode::COPY), LI->reg)
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| H A D | LiveIntervalAnalysis.cpp | 104 TII = TM->getInstrInfo();
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| H A D | ScheduleDAGInstrs.cpp | 58 SchedModel.init(*ST.getSchedModel(), &ST, TII);
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| /external/llvm/include/llvm/CodeGen/ |
| H A D | MachineRegisterInfo.h | 498 const TargetInstrInfo &TII);
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| H A D | ScheduleDAG.h | 559 const TargetInstrInfo *TII; // Target instruction information member in class:llvm::ScheduleDAG
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| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 71 const TargetInstrInfo *TII = TM.getInstrInfo(); local
72 assert(TII && "No InstrInfo?");
74 return new PPCHazardRecognizer970(*TII);
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGISel.cpp | 352 const TargetInstrInfo &TII = *TM.getInstrInfo(); local
388 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
420 TII.get(TargetOpcode::DBG_VALUE))
441 TII.get(TargetOpcode::DBG_VALUE))
3007 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
3008 Msg << "target intrinsic %" << TII->getName(iid);
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| H A D | SelectionDAGBuilder.cpp | 4368 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo(); local
4416 TII->get(TargetOpcode::DBG_VALUE))
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| /external/llvm/lib/Target/R600/ |
| H A D | AMDILCFGStructurizer.cpp | 2477 const TargetInstrInfo *TII; member in class:llvm::AMDGPUCFGStructurizer
2490 : MachineFunctionPass(pid), TM(tm), TII(tm.getInstrInfo()),
2495 return TII;
2709 const AMDGPUInstrInfo * TII = static_cast<const AMDGPUInstrInfo *>( local
2719 } else if (!TII->isMov(instr->getOpcode())) {
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| /external/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 3588 const TargetInstrInfo &TII) {
3591 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
3616 MachineInstr *MI, const TargetInstrInfo &TII) {
3618 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
3638 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode, argument
3642 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
4738 const X86InstrInfo *TII = TM->getInstrInfo(); local
4748 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
4754 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
4836 const X86InstrInfo *TII local
3585 FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode, const SmallVectorImpl<MachineOperand> &MOs, MachineInstr *MI, const TargetInstrInfo &TII) argument
3613 FuseInst(MachineFunction &MF, unsigned Opcode, unsigned OpNo, const SmallVectorImpl<MachineOperand> &MOs, MachineInstr *MI, const TargetInstrInfo &TII) argument
4857 const X86InstrInfo *TII = TM->getInstrInfo(); local
[all...] |
| H A D | X86RegisterInfo.cpp | 65 TM(tm), TII(tii) {
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| H A D | X86ISelDAGToDAG.cpp | 555 const TargetInstrInfo *TII = TM.getInstrInfo(); local
560 TII->get(CallOp)).addExternalSymbol("__main");
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 1625 const TargetInstrInfo *TII) {
1654 if (!MI->isSafeToMove(TII, /* AliasAnalysis = */ 0, DontMoveAcrossStores))
1778 const ARMBaseInstrInfo &TII, unsigned MIFlags) {
1794 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1804 const ARMBaseInstrInfo &TII) {
1818 MI.setDesc(TII.get(ARM::MOVr));
1826 MI.setDesc(TII.get(ARM::SUBri));
1623 canFoldIntoMOVCC(unsigned Reg, const MachineRegisterInfo &MRI, const TargetInstrInfo *TII) argument
1774 emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags) argument
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| H A D | ARMISelDAGToDAG.cpp | 64 const ARMBaseInstrInfo *TII; member in class:__anon9665::ARMDAGToDAGISel
74 TII(static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo())),
437 const MCInstrDesc &MCID = TII->get(Use->getMachineOpcode());
456 return TII->isFpMLxInstruction(Opcode);
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| /external/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1166 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); local
1217 BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
1231 BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI->getOperand(0).getReg())
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| /external/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 1289 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); local
1325 BuildMI(BB, dl, TII.get(XCore::BRFT_lru6))
1341 TII.get(XCore::PHI), MI->getOperand(0).getReg())
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| /external/apache-harmony/luni/src/test/api/common/org/apache/harmony/luni/tests/java/util/ |
| H A D | ArraysTest.java | 3456 public void test_copyOfRange_$TII() throws Exception {
|