Searched refs:TII (Results 76 - 100 of 193) sorted by relevance

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/external/llvm/lib/CodeGen/
H A DLiveRangeEdit.cpp50 if (!TII.isTriviallyReMaterializable(DefMI, aa))
149 TII.reMaterialize(MBB, MI, DestReg, 0, RM.OrigMI, tri);
197 if (!DefMI->isSafeToMove(&TII, 0, SawStore))
207 MachineInstr *FoldMI = TII.foldMemoryOperand(UseMI, Ops, DefMI);
240 if (!MI->isSafeToMove(&TII, 0, SawStore)) {
294 MI->setDesc(TII.get(TargetOpcode::KILL));
H A DEarlyIfConversion.cpp81 const TargetInstrInfo *TII; member in class:__anon9453::SSAIfConv
155 TII = MF.getTarget().getInstrInfo();
222 if (!I->isSafeToMove(TII, 0, DontMoveAcrossStore)) {
388 if (TII->AnalyzeBranch(*Head, TBB, FBB, Cond)) {
422 if (!TII->canInsertSelect(*Head, Cond, PI.TReg, PI.FReg,
463 TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg, PI.FReg);
484 TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg, PI.FReg);
540 TII->RemoveBranch(*Head);
567 TII->InsertBranch(*Head, Tail, 0, EmptyCond, HeadDL);
580 const TargetInstrInfo *TII; member in class:__anon9454::EarlyIfConverter
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H A DCriticalAntiDepBreaker.h37 const TargetInstrInfo *TII; member in class:llvm::CriticalAntiDepBreaker
H A DTwoAddressInstructionPass.cpp64 const TargetInstrInfo *TII; member in class:__anon9544::TwoAddressInstructionPass
180 if (!MI->isSafeToMove(TII, AA, SeenStore))
332 static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII, argument
397 const TargetInstrInfo *TII,
420 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
450 const TargetInstrInfo *TII,
461 if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) {
575 MachineInstr *NewMI = TII->commuteInstruction(MI);
623 MachineInstr *NewMI = TII->convertToThreeAddress(MFI, mi, LV);
664 while (MachineInstr *UseMI = findOnlyInterestingUse(Reg, MBB, MRI, TII,IsCop
395 isKilled(MachineInstr &MI, unsigned Reg, const MachineRegisterInfo *MRI, const TargetInstrInfo *TII, LiveIntervals *LIS, bool allowFalsePositives) argument
448 findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB, MachineRegisterInfo *MRI, const TargetInstrInfo *TII, bool &IsCopy, unsigned &DstReg, bool &IsDstPhys) argument
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H A DCodePlacementOpt.cpp34 const TargetInstrInfo *TII; member in class:__anon9450::CodePlacementOpt
79 if (TII->AnalyzeBranch(*MBB, TBB, FBB, Cond))
109 if (TII->AnalyzeBranch(*MBB, TBB, FBB, Cond))
120 if (!Cond.empty() && TII->ReverseBranchCondition(Cond))
416 TII = MF.getTarget().getInstrInfo();
/external/llvm/lib/Target/MBlaze/
H A DMBlazeISelLowering.cpp253 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local
297 BuildMI(MBB, dl, TII->get(MBlaze::ANDI), IAMT)
302 BuildMI(MBB, dl, TII->get(MBlaze::ADDIK), IVAL)
306 BuildMI(MBB, dl, TII->get(MBlaze::BEQID))
312 BuildMI(loop, dl, TII->get(MBlaze::PHI), DST)
318 BuildMI(loop, dl, TII->get(MBlaze::PHI), SAMT)
323 BuildMI(loop, dl, TII->get(MBlaze::ADD), NDST).addReg(DST).addReg(DST);
325 BuildMI(loop, dl, TII->get(MBlaze::SRA), NDST).addReg(DST);
327 BuildMI(loop, dl, TII->get(MBlaze::SRL), NDST).addReg(DST);
331 BuildMI(loop, dl, TII
352 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local
420 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local
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/external/llvm/include/llvm/CodeGen/
H A DLiveRangeEdit.h63 const TargetInstrInfo &TII; member in class:llvm::LiveRangeEdit
110 TII(*MF.getTarget().getInstrInfo()),
H A DMachineSSAUpdater.h54 const TargetInstrInfo *TII; member in class:llvm::MachineSSAUpdater
/external/llvm/lib/Target/ARM/
H A DARMConstantIslandPass.cpp259 const ARMBaseInstrInfo *TII; member in class:__anon9659::ARMConstantIslands
384 TII = (const ARMBaseInstrInfo*)MF->getTarget().getInstrInfo();
545 BuildMI(*BB, InsAt, DebugLoc(), TII->get(ARM::CONSTPOOL_ENTRY))
805 BBI.Size += TII->GetInstSizeInBytes(I);
836 Offset += TII->GetInstSizeInBytes(I);
889 BuildMI(OrigBB, DebugLoc(), TII->get(Opc)).addMBB(NewBB);
891 BuildMI(OrigBB, DebugLoc(), TII->get(Opc)).addMBB(NewBB)
1259 BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr)).addMBB(NewMBB);
1261 BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr)).addMBB(NewMBB)
1320 for (unsigned Offset = UserOffset+TII
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H A DMLxExpansionPass.cpp50 const ARMBaseInstrInfo *TII; member in struct:__anon9692::MLxExpansion
220 if (TII->isFpMLxInstruction(DefMI->getOpcode())) {
255 if (TII->canCauseFpMLxStall(NextMI->getOpcode())) {
286 const MCInstrDesc &MCID1 = TII->get(MulOpc);
287 const MCInstrDesc &MCID2 = TII->get(AddSubOpc);
290 TII->getRegClass(MCID1, 0, TRI, MF));
361 if (!TII->isFpMLxInstruction(MCID.getOpcode(),
380 TII = static_cast<const ARMBaseInstrInfo*>(Fn.getTarget().getInstrInfo());
H A DThumb1RegisterInfo.h51 const ARMBaseInstrInfo &TII) const;
H A DARMBaseRegisterInfo.cpp48 : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), TII(tii), STI(sti),
377 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
553 const MCInstrDesc &MCID = TII.get(ADDriOpc);
556 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
584 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
587 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
703 Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
706 Done = rewriteT2FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
731 Offset, Pred, PredReg, TII);
735 Offset, Pred, PredReg, TII);
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H A DARMBaseInstrInfo.h386 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
392 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
396 int NumBytes, const TargetInstrInfo &TII,
407 const ARMBaseInstrInfo &TII);
411 const ARMBaseInstrInfo &TII);
/external/llvm/lib/Target/R600/
H A DR600MachineScheduler.h37 const R600InstrInfo *TII; member in class:llvm::R600SchedStrategy
78 DAG(0), TII(0), TRI(0), MRI(0) {
H A DR600RegisterInfo.cpp27 TII(tii)
58 const R600InstrInfo *RII = static_cast<const R600InstrInfo*>(&TII);
H A DSIISelLowering.h24 const SIInstrInfo * TII; member in class:llvm::SITargetLowering
H A DR600ISelLowering.cpp30 TII(static_cast<const R600InstrInfo*>(TM.getInstrInfo())) {
110 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
114 TII->addFlag(NewMI, 0, MO_FLAG_CLAMP);
119 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
123 TII->addFlag(NewMI, 0, MO_FLAG_ABS);
128 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
132 TII->addFlag(NewMI, 0, MO_FLAG_NEG);
140 TII->addFlag(defInstr, 0, MO_FLAG_MASK);
145 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
150 TII
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H A DR600MachineScheduler.cpp31 TII = static_cast<const R600InstrInfo*>(DAG->TII);
208 if(TII->isVector(*MI) ||
209 TII->isCubeOp(MI->getOpcode()) ||
210 TII->isReductionOp(MI->getOpcode()))
249 if (TII->isALUInstr(Opcode)) {
297 if (TII->canBundle(InstructionsGroupCandidate)) {
/external/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp132 const MCInstrDesc &II = TII->get(User->getMachineOpcode());
136 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF));
176 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
220 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
281 TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
319 DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF));
323 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
443 BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg)
483 TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) &&
493 TII
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H A DFastISel.cpp237 TII.get(TargetOpcode::IMPLICIT_DEF), Reg);
580 TII.get(TargetOpcode::INLINEASM))
645 TII.get(TargetOpcode::DBG_VALUE))
657 const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
792 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
874 TII.InsertBranch(*FuncInfo.MBB, MSucc, NULL,
1091 TII(*TM.getInstrInfo()),
1199 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1209 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1217 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII
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/external/llvm/lib/Target/MSP430/
H A DMSP430RegisterInfo.cpp37 : MSP430GenRegisterInfo(MSP430::PCW), TM(tm), TII(tii) {
136 MI.setDesc(TII.get(MSP430::MOV16rr));
145 BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::SUB16ri), DstReg)
148 BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::ADD16ri), DstReg)
/external/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.h32 const TargetInstrInfo &TII; member in class:llvm::PPCRegisterInfo
/external/llvm/lib/Target/X86/
H A DX86RegisterInfo.h30 const TargetInstrInfo &TII; member in class:llvm::X86RegisterInfo
/external/llvm/lib/Target/Mips/
H A DMipsSEISelDAGToDAG.cpp86 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local
107 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
109 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
111 BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
121 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
123 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
136 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
138 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
139 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
165 BuildMI(MBB, I, DL, TII
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/external/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp605 const AArch64InstrInfo &TII) {
616 DebugLoc dl, const TargetInstrInfo &TII,
626 BuildMI(MBB, MBBI, dl, TII.get(AArch64::MOVZxii), ScratchReg)
632 BuildMI(MBB, MBBI, dl, TII.get(AArch64::MOVKxii), ScratchReg)
640 BuildMI(MBB, MBBI, dl, TII.get(AArch64::MOVKxii), ScratchReg)
648 BuildMI(MBB, MBBI, dl, TII.get(AArch64::MOVKxii), ScratchReg)
656 BuildMI(MBB, MBBI, dl, TII.get(AddOp), DstReg)
682 BuildMI(MBB, MBBI, dl, TII.get(LowOp), DstReg)
692 BuildMI(MBB, MBBI, dl, TII.get(HighOp), DstReg)
700 DebugLoc dl, const TargetInstrInfo &TII,
603 rewriteA64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const AArch64InstrInfo &TII) argument
614 emitRegUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc dl, const TargetInstrInfo &TII, unsigned DstReg, unsigned SrcReg, unsigned ScratchReg, int64_t NumBytes, MachineInstr::MIFlag MIFlags) argument
699 emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc dl, const TargetInstrInfo &TII, unsigned ScratchReg, int64_t NumBytes, MachineInstr::MIFlag MIFlags) argument
771 const AArch64InstrInfo *TII = TM->getInstrInfo(); local
792 const AArch64InstrInfo *TII = TM->getInstrInfo(); local
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