/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.h | 79 explicit NVPTXTargetLowering(NVPTXTargetMachine &TM);
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/external/llvm/lib/Target/R600/ |
H A D | AMDGPUISelLowering.h | 46 AMDGPUTargetLowering(TargetMachine &TM);
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H A D | R600InstrInfo.h | 69 DFAPacketizer *CreateTargetScheduleState(const TargetMachine *TM,
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H A D | R600InstrInfo.cpp | 196 DFAPacketizer *R600InstrInfo::CreateTargetScheduleState(const TargetMachine *TM, argument 198 const InstrItineraryData *II = TM->getInstrItineraryData(); 199 return TM->getSubtarget<AMDGPUSubtarget>().createDFAPacketizer(II); 565 Offset = TM.getFrameLowering()->getFrameIndexOffset(MF, -1); 573 static_cast<const AMDGPUFrameLowering*>(TM.getFrameLowering());
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/external/llvm/lib/Target/ARM/ |
H A D | ARMAsmPrinter.cpp | 231 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 309 uint64_t Size = TM.getDataLayout()->getTypeAllocSize(CV->getType()); 581 Reloc::Model RelocM = TM.getRelocationModel(); 601 TextSections.insert(TLOFMacho.SectionForGlobal(F, Mang, TM)); 829 if (!TM.Options.UnsafeFPMath) { 836 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath) 849 if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard) { 909 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel()); 928 int Size = TM [all...] |
/external/llvm/lib/CodeGen/ |
H A D | MachineRegisterInfo.cpp | 61 MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) { argument 62 const TargetInstrInfo *TII = TM.getInstrInfo();
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H A D | PostRASchedulerList.cpp | 202 const TargetMachine &TM = MF.getTarget(); local 203 const InstrItineraryData *InstrItins = TM.getInstrItineraryData(); 205 TM.getInstrInfo()->CreateTargetPostRAHazardRecognizer(InstrItins, this);
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H A D | ScheduleDAG.cpp | 37 : TM(mf.getTarget()), 38 TII(TM.getInstrInfo()), 39 TRI(TM.getRegisterInfo()),
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H A D | TargetInstrInfo.cpp | 438 const TargetMachine &TM = MF.getTarget(); local 439 const TargetInstrInfo &TII = *TM.getInstrInfo(); 547 CreateTargetHazardRecognizer(const TargetMachine *TM, argument
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H A D | MachineLICM.cpp | 63 const TargetMachine *TM; member in class:__anon9479::MachineLICM 323 TM = &MF.getTarget(); 324 TII = TM->getInstrInfo(); 325 TLI = TM->getTargetLowering(); 326 TRI = TM->getRegisterInfo(); 329 InstrItins = TM->getInstrItineraryData();
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/external/llvm/lib/ExecutionEngine/ |
H A D | ExecutionEngine.cpp | 46 TargetMachine *TM) = 0; 52 TargetMachine *TM) = 0; 444 TargetMachine *TM = EB.selectTarget(); local 445 if (!TM || (ErrorStr && ErrorStr->length() > 0)) return 0; 447 return ExecutionEngine::JITCtor(M, ErrorStr, JMM, GVsWithCode, TM); 450 ExecutionEngine *EngineBuilder::create(TargetMachine *TM) { argument 451 OwningPtr<TargetMachine> TheTM(TM); // Take ownership. 475 if (!TM->getTarget().hasJIT()) {
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/external/llvm/lib/Target/MBlaze/ |
H A D | MBlazeInstrInfo.cpp | 32 TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
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/external/llvm/lib/Target/X86/ |
H A D | X86JITInfo.cpp | 436 X86JITInfo::X86JITInfo(X86TargetMachine &tm) : TM(tm) { 437 Subtarget = &TM.getSubtarget<X86Subtarget>();
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H A D | X86FastISel.cpp | 63 Subtarget = &TM.getSubtarget<X86Subtarget>(); 66 RegInfo = static_cast<const X86RegisterInfo*>(TM.getRegisterInfo()); 126 return static_cast<const X86TargetMachine *>(&TM); 487 if (TM.getCodeModel() != CodeModel::Small) 512 unsigned char GVFlags = Subtarget->ClassifyGlobalReference(GV, TM); 633 if (TM.getCodeModel() != CodeModel::Small) 735 if (CC == CallingConv::Fast && TM.Options.GuaranteedTailCallOpt) 751 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs, 1649 if (CC == CallingConv::Fast && TM.Options.GuaranteedTailCallOpt) 1663 TM [all...] |
H A D | X86FrameLowering.cpp | 48 const TargetRegisterInfo *RegInfo = TM.getRegisterInfo(); 316 const X86RegisterInfo *RegInfo = TM.getRegisterInfo(); 497 const X86RegisterInfo *RegInfo = TM.getRegisterInfo(); 653 const X86RegisterInfo *RegInfo = TM.getRegisterInfo(); 654 const X86InstrInfo &TII = *TM.getInstrInfo(); 993 const X86RegisterInfo *RegInfo = TM.getRegisterInfo(); 994 const X86InstrInfo &TII = *TM.getInstrInfo(); 1337 const X86RegisterInfo *RegInfo = TM.getRegisterInfo(); 1430 const X86InstrInfo &TII = *TM.getInstrInfo(); 1630 const X86InstrInfo &TII = *TM [all...] |
/external/harfbuzz_ng/src/ |
H A D | hb-ot-shape-complex-indic-table.cc | 268 /* 0E48 */ _(TM,x), _(TM,x), _(TM,x), _(TM,x), _(x,x), _(Bi,x), _(V,T), _(x,x), 287 /* 0EC8 */ _(TM,x), _(TM,x), _(TM,x), _(TM,x), _(x,x), _(Bi,x), _(x,x), _(x,x), 338 /* 1030 */ _(M,B), _(M,L), _(M,T), _(M,T), _(M,T), _(M,T), _(Bi,x), _(TM,x), 344 /* 1060 */ _(CM,x), _(C,x), _(M,R), _(TM, [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 47 const PPCTargetMachine &TM; member in class:__anon9760::PPCDAGToDAGISel 53 : SelectionDAGISel(tm), TM(tm), 54 PPCLowering(*TM.getTargetLowering()), 55 PPCSubTarget(*TM.getSubtargetImpl()) { 227 const TargetInstrInfo &TII = *TM.getInstrInfo(); 263 const TargetInstrInfo &TII = *TM.getInstrInfo(); 1287 CodeModel::Model CModel = TM.getCodeModel(); 1409 if (TM.getOptLevel() == CodeGenOpt::None) 1558 FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) { argument 1559 return new PPCDAGToDAGISel(TM); [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonHardwareLoops.cpp | 67 const HexagonTargetMachine *TM; member in struct:__anon9699::HexagonHardwareLoops 268 void print(raw_ostream &OS, const TargetMachine *TM = 0) const { 269 const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0; 304 TM = static_cast<const HexagonTargetMachine*>(&MF.getTarget()); 305 TII = static_cast<const HexagonInstrInfo*>(TM->getInstrInfo()); 306 TRI = static_cast<const HexagonRegisterInfo*>(TM->getRegisterInfo());
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGISel.cpp | 226 const TargetSubtargetInfo &ST = IS->TM.getSubtarget<TargetSubtargetInfo>(); 276 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()), 346 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) && 348 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) && 352 const TargetInstrInfo &TII = *TM.getInstrInfo(); 353 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 363 const_cast<TargetSubtargetInfo&>(TM.getSubtarget<TargetSubtargetInfo>()); 365 TM.resetTargetOptions(MF); 461 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode()); 817 const MCInstrDesc &II = TM [all...] |
H A D | InstrEmitter.cpp | 393 Align = TM->getDataLayout()->getPrefTypeAlignment(Type); 396 Align = TM->getDataLayout()->getTypeAllocSize(Type); 977 TM(&MF->getTarget()), 978 TII(TM->getInstrInfo()), 979 TRI(TM->getRegisterInfo()), 980 TLI(TM->getTargetLowering()),
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/external/llvm/utils/TableGen/ |
H A D | FastISelEmitter.cpp | 592 const TypeRetPredMap &TM = I->second; 598 for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end(); 772 for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end();
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/external/llvm/lib/Target/Mips/ |
H A D | MipsSEISelDAGToDAG.cpp | 241 if (TM.getRelocationModel() != Reloc::PIC_) { 458 FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM) { argument 459 return new MipsSEDAGToDAGISel(TM);
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/external/clang/lib/StaticAnalyzer/Core/ |
H A D | ProgramState.cpp | 421 TaintMapImpl TM = get<TaintMap>(); local 423 if (!TM.isEmpty()) 426 for (TaintMapImpl::iterator I = TM.begin(), E = TM.end(); I != E; ++I) {
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/external/llvm/include/llvm/CodeGen/ |
H A D | FastISel.h | 56 const TargetMachine &TM; member in class:llvm::FastISel
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H A D | LiveIntervalAnalysis.h | 52 const TargetMachine* TM; member in class:llvm::LiveIntervals
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