| /external/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 284 return static_cast<const X86TargetMachine &>(TM);
555 const TargetInstrInfo *TII = TM.getInstrInfo();
584 CodeModel::Model M = TM.getCodeModel();
635 CodeModel::Model M = TM.getCodeModel();
739 if (TM.getCodeModel() == CodeModel::Small &&
2723 FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, argument
2725 return new X86DAGToDAGISel(TM, OptLevel);
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| H A D | X86AsmPrinter.cpp | 693 const DataLayout *TD = TM.getDataLayout();
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| H A D | X86ISelLowering.h | 470 explicit X86TargetLowering(X86TargetMachine &TM);
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| H A D | X86ISelLowering.cpp | 142 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) { argument
143 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
161 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) argument
162 : TargetLowering(TM, createTLOF(TM)) {
163 Subtarget = &TM.getSubtarget<X86Subtarget>();
167 RegInfo = TM.getRegisterInfo();
190 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
264 } else if (!TM.Options.UseSoftFloat) {
278 if (!TM
2747 const TargetMachine &TM = MF.getTarget(); local
11210 const TargetMachine &TM = MF.getTarget(); local
[all...] |
| /external/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 200 MipsTargetLowering(MipsTargetMachine &TM) argument
201 : TargetLowering(TM, new MipsTargetObjectFile()),
202 Subtarget(&TM.getSubtarget<MipsSubtarget>()),
244 if (!TM.Options.NoNaNsFPMath) {
327 if (!TM.Options.NoNaNsFPMath) {
398 const MipsTargetLowering *MipsTargetLowering::create(MipsTargetMachine &TM) { argument
399 if (TM.getSubtargetImpl()->inMips16Mode())
400 return llvm::createMips16TargetLowering(TM);
402 return llvm::createMipsSETargetLowering(TM);
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| /external/llvm/lib/Target/R600/ |
| H A D | R600ISelLowering.cpp | 28 R600TargetLowering::R600TargetLowering(TargetMachine &TM) : argument
29 AMDGPUTargetLowering(TM),
30 TII(static_cast<const R600InstrInfo*>(TM.getInstrInfo())) {
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| H A D | AMDILCFGStructurizer.cpp | 2476 TargetMachine &TM; member in class:llvm::AMDGPUCFGStructurizer
2490 : MachineFunctionPass(pid), TM(tm), TII(tm.getInstrInfo()),
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| /external/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 690 SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) argument
691 : TargetLowering(TM, new TargetLoweringObjectFileELF()) {
807 if (TM.getSubtarget<SparcSubtarget>().isV9())
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| /external/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstr.h | 954 void print(raw_ostream &OS, const TargetMachine *TM = 0,
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| H A D | ScheduleDAG.h | 558 const TargetMachine &TM; // Target processor member in class:llvm::ScheduleDAG
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| /external/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 70 NVPTXTargetLowering::NVPTXTargetLowering(NVPTXTargetMachine &TM) argument
71 : TargetLowering(TM, new NVPTXTargetObjectFile()),
72 nvTM(&TM),
73 nvptxSubtarget(TM.getSubtarget<NVPTXSubtarget>()) {
|
| H A D | NVPTXISelDAGToDAG.cpp | 53 FunctionPass *llvm::createNVPTXISelDag(NVPTXTargetMachine &TM, argument
55 return new NVPTXDAGToDAGISel(TM, OptLevel);
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| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCCTRLoops.cpp | 176 void print(raw_ostream &OS, const TargetMachine *TM = 0) const {
|
| /external/llvm/lib/CodeGen/ |
| H A D | MachineScheduler.cpp | 1253 const TargetMachine &TM = DAG->MF.getTarget(); local
1254 Top.HazardRec = TM.getInstrInfo()->CreateTargetMIHazardRecognizer(Itin, DAG);
1255 Bot.HazardRec = TM.getInstrInfo()->CreateTargetMIHazardRecognizer(Itin, DAG);
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| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 2407 CreateTargetScheduleState(const TargetMachine *TM, argument
2409 const InstrItineraryData *II = TM->getInstrItineraryData();
2410 return TM->getSubtarget<HexagonGenSubtargetInfo>().createDFAPacketizer(II);
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| /external/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 66 TM(XTM),
289 const DataLayout *TD = TM.getDataLayout();
1593 const DataLayout *TD = TM.getDataLayout();
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 63 ARMBaseTargetMachine &TM; member in class:__anon9665::ARMDAGToDAGISel
73 : SelectionDAGISel(tm, OptLevel), TM(tm),
74 TII(static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo())),
75 Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
3600 FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM, argument
3602 return new ARMDAGToDAGISel(TM, OptLevel);
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| H A D | ARMISelLowering.cpp | 77 const TargetMachine &TM, SmallVector<CCValAssign, 16> &locs,
79 : CCState(CC, isVarArg, MF, TM, locs, C) {
162 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) { argument
163 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
169 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) argument
170 : TargetLowering(TM, createTLOF(TM)) {
171 Subtarget = &TM.getSubtarget<ARMSubtarget>();
172 RegInfo = TM.getRegisterInfo();
173 Itins = TM
76 ARMCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF, const TargetMachine &TM, SmallVector<CCValAssign, 16> &locs, LLVMContext &C, ParmContext PC) argument
[all...] |
| H A D | ARMBaseInstrInfo.cpp | 103 CreateTargetHazardRecognizer(const TargetMachine *TM, argument
106 const InstrItineraryData *II = TM->getInstrItineraryData();
109 return TargetInstrInfo::CreateTargetHazardRecognizer(TM, DAG);
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 51 const TargetMachine &TM; member in class:__anon9515::SelectionDAGLegalize
213 TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
1577 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
2117 const TargetMachine &TM) {
2122 bool isGNU = Triple(TM.getTargetTriple()).getEnvironment() == Triple::GNU;
2123 if (isGNU && !TM.Options.UnsafeFPMath)
3154 canCombineSinCosLibcall(Node, TLI, TM))
3587 if (TM.getRelocationModel() == Reloc::PIC_) {
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| H A D | ScheduleDAGSDNodes.cpp | 422 const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
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| H A D | SelectionDAGBuilder.cpp | 1396 if (TM.Options.NoNaNsFPMath)
2724 if (TM.Options.NoNaNsFPMath)
3238 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
4916 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
5088 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
5154 if (TM.getOptLevel() == CodeGenOpt::None)
5534 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
6764 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
6774 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
6785 if (!isOnlyUsedInEntryBlock(I, TM
[all...] |
| H A D | SelectionDAG.cpp | 876 : TM(tm), TLI(*tm.getTargetLowering()), TSI(*tm.getSelectionDAGInfo()),
|
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| H A D | DwarfDebug.cpp | 410 const TargetRegisterInfo *RI = Asm->TM.getRegisterInfo();
629 if (Asm->TM.hasMCUseLoc() &&
1377 const TargetRegisterInfo *TRI = Asm->TM.getRegisterInfo();
|