/external/llvm/lib/CodeGen/ |
H A D | BranchFolding.h | 91 const TargetRegisterInfo *TRI; member in class:llvm::BranchFolder
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H A D | RegAllocBase.cpp | 56 TRI = &vrm.getTargetRegInfo();
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H A D | MachineBasicBlock.cpp | 286 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); local 291 OS << ' ' << PrintReg(*I, TRI); 778 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); local 784 if (!(--I)->addRegisterKilled(Reg, TRI, /* addIfNotFound= */ false)) 1107 MachineBasicBlock::computeRegisterLiveness(const TargetRegisterInfo *TRI, 1122 MIOperands(I).analyzePhysReg(Reg, TRI); 1143 for (MCRegAliasIterator RAI(Reg, TRI, /*IncludeSelf=*/true); 1160 MIOperands(I).analyzePhysReg(Reg, TRI);
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H A D | RegAllocBasic.cpp | 174 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { 186 DEBUG(dbgs() << "spilling " << TRI->getName(PhysReg) <<
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H A D | TargetSchedule.cpp | 292 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); local 293 if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(DepMI))
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H A D | MachineCSE.cpp | 42 const TargetRegisterInfo *TRI; member in class:__anon9474::MachineCSE 171 if (!TRI->regsOverlap(MO.getReg(), Reg)) 210 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) 239 for (MCRegAliasIterator AI(PhysDefs[i], TRI, true); AI.isValid(); ++AI) 656 TRI = MF.getTarget().getRegisterInfo();
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H A D | BranchFolding.cpp | 139 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) 183 TRI = tri; 189 if (MRI.tracksLiveness() && TRI->trackLivenessAfterRegAlloc(MF)) 383 BitVector RegsLiveAtExit(TRI->getNumRegs()); 385 for (unsigned int i = 0, e = TRI->getNumRegs(); i != e; i++) 1475 const TargetRegisterInfo *TRI, 1490 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) 1551 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) 1555 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) 1558 for (MCRegAliasIterator AI(Reg, TRI, tru 1473 findHoistingInsertPosAndDeps(MachineBasicBlock *MBB, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, SmallSet<unsigned,4> &Uses, SmallSet<unsigned,4> &Defs) argument [all...] |
H A D | TwoAddressInstructionPass.cpp | 65 const TargetRegisterInfo *TRI; member in class:__anon9544::TwoAddressInstructionPass 285 KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI); 491 regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) { argument 496 return TRI->regsOverlap(RegA, RegB); 544 bool BComp = !FromRegB || regsAreCompatible(FromRegB, ToRegA, TRI); 545 bool CComp = !FromRegC || regsAreCompatible(FromRegC, ToRegA, TRI); 611 return (ToRegA && !regsAreCompatible(FromRegB, ToRegA, TRI)); 635 if (NewMI->findRegisterUseOperand(RegB, false, TRI)) 1193 TRI->getAllocatableClass( 1194 TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI, *M [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.h | 34 const TargetRegisterInfo *TRI; member in class:llvm::InstrEmitter
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H A D | ScheduleDAGFast.cpp | 120 LiveRegDefs.resize(TRI->getNumRegs(), NULL); 121 LiveRegCycles.resize(TRI->getNumRegs(), 0); 452 const TargetRegisterInfo *TRI) { 454 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) { 480 RegAdded, LRegs, TRI); 504 CheckForLiveRegDef(SU, Reg, LiveRegDefs, RegAdded, LRegs, TRI); 517 CheckForLiveRegDef(SU, *Reg, LiveRegDefs, RegAdded, LRegs, TRI); 576 TRI->getMinimalPhysRegClass(Reg, VT); 577 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC); 448 CheckForLiveRegDef(SUnit *SU, unsigned Reg, std::vector<SUnit*> &LiveRegDefs, SmallSet<unsigned, 4> &RegAdded, SmallVector<unsigned, 4> &LRegs, const TargetRegisterInfo *TRI) argument
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/external/llvm/lib/Target/ARM/ |
H A D | MLxExpansionPass.cpp | 51 const TargetRegisterInfo *TRI; member in struct:__anon9692::MLxExpansion 194 return MI->readsRegister(Reg, TRI); 290 TII->getRegClass(MCID1, 0, TRI, MF)); 381 TRI = Fn.getTarget().getRegisterInfo();
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H A D | ARMFrameLowering.cpp | 732 const TargetRegisterInfo *TRI) { 804 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, 822 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, 834 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, 853 llvm::prior(MI)->addRegisterKilled(ARM::R4, TRI); 891 const TargetRegisterInfo *TRI) { 922 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, 938 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, 949 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, 963 llvm::prior(MI)->addRegisterKilled(ARM::R4, TRI); 728 emitAlignedDPRCS2Spills(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned NumAlignedDPRCS2Regs, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) argument 887 emitAlignedDPRCS2Restores(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned NumAlignedDPRCS2Regs, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) argument [all...] |
H A D | Thumb2InstrInfo.cpp | 128 const TargetRegisterInfo *TRI) const { 148 ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI); 155 const TargetRegisterInfo *TRI) const { 174 ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI);
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonInstrInfo.h | 82 const TargetRegisterInfo *TRI) const; 93 const TargetRegisterInfo *TRI) const;
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H A D | HexagonCallingConvLower.h | 51 const TargetRegisterInfo &TRI; member in class:llvm::Hexagon_CCState
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/external/llvm/lib/Target/Mips/ |
H A D | Mips16FrameLowering.cpp | 103 const TargetRegisterInfo *TRI) const { 131 const TargetRegisterInfo *TRI) const {
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H A D | MipsSEInstrInfo.cpp | 158 const TargetRegisterInfo *TRI) const { 185 const TargetRegisterInfo *TRI) const 353 const TargetRegisterInfo &TRI = getRegisterInfo(); local 357 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_fpeven)) 359 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_fpodd))
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H A D | MipsSEFrameLowering.cpp | 216 const TargetRegisterInfo *TRI) const { 235 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 237 CSI[i].getFrameIdx(), RC, TRI);
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCFrameLowering.h | 56 const TargetRegisterInfo *TRI) const; 65 const TargetRegisterInfo *TRI) const;
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/external/llvm/lib/Target/R600/ |
H A D | AMDGPUInstrInfo.cpp | 129 const TargetRegisterInfo *TRI) const { 138 const TargetRegisterInfo *TRI) const {
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H A D | AMDGPUInstrInfo.h | 83 const TargetRegisterInfo *TRI) const; 88 const TargetRegisterInfo *TRI) const;
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64FrameLowering.cpp | 425 const TargetRegisterInfo *TRI, 525 const TargetRegisterInfo *TRI) const { 535 emitFrameMemOps(/* isPrologue = */ true, MBB, MBBI, CSI, TRI, 545 const TargetRegisterInfo *TRI) const { 556 emitFrameMemOps(/* isPrologue = */ false, MBB, MBBI, CSI, TRI, 422 emitFrameMemOps(bool isPrologue, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI, LoadStoreMethod PossClasses[], unsigned NumClasses) const argument
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/external/llvm/include/llvm/CodeGen/ |
H A D | LiveIntervalUnion.h | 95 // Print union, using TRI to translate register names 96 void print(raw_ostream &OS, const TargetRegisterInfo *TRI) const;
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H A D | MachineInstrBundle.h | 207 PhysRegInfo analyzePhysReg(unsigned Reg, const TargetRegisterInfo *TRI);
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H A D | MachineTraceMetrics.h | 70 const TargetRegisterInfo *TRI; member in class:llvm::MachineTraceMetrics
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