Searched refs:TRI (Results 51 - 75 of 190) sorted by relevance

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/external/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp62 const TargetRegisterInfo *TRI; member in struct:__anon9652::A15SDOptimizer
152 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1,
161 if (!TRI->isVirtualRegister(SReg))
203 if (!TRI->isVirtualRegister(Reg))
226 if (!TRI->isVirtualRegister(DefReg)) {
262 if (TRI->isVirtualRegister(DPRReg) && TRI->isVirtualRegister(SPRReg)) {
312 if (!TRI->isVirtualRegister(OpReg))
357 if (!TRI->isVirtualRegister(MI->getOperand(1).getReg()))
385 if (!TRI
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H A DThumb1InstrInfo.cpp55 const TargetRegisterInfo *TRI) const {
83 const TargetRegisterInfo *TRI) const {
H A DARMExpandPseudoInsts.cpp43 const TargetRegisterInfo *TRI; member in class:__anon9660::ARMExpandPseudo
351 const TargetRegisterInfo *TRI, unsigned &D0,
354 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
355 D1 = TRI->getSubReg(Reg, ARM::dsub_1);
356 D2 = TRI->getSubReg(Reg, ARM::dsub_2);
357 D3 = TRI->getSubReg(Reg, ARM::dsub_3);
359 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
360 D1 = TRI->getSubReg(Reg, ARM::dsub_2);
361 D2 = TRI->getSubReg(Reg, ARM::dsub_4);
362 D3 = TRI
350 GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc, const TargetRegisterInfo *TRI, unsigned &D0, unsigned &D1, unsigned &D2, unsigned &D3) argument
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/external/llvm/include/llvm/CodeGen/
H A DMachineRegisterInfo.h29 const TargetRegisterInfo *const TRI; member in class:llvm::MachineRegisterInfo
111 explicit MachineRegisterInfo(const TargetRegisterInfo &TRI);
374 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
389 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
403 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
439 /// TRI::getReservedRegs() when possible.
443 "Use TRI::getReservedRegs().");
463 return TRI->isInAllocatableClass(PhysReg) && !isReserved(PhysReg);
497 const TargetRegisterInfo &TRI,
H A DLiveVariables.h134 const TargetRegisterInfo *TRI; member in class:llvm::LiveVariables
202 if (MI->addRegisterKilled(IncomingReg, TRI, AddIfNotFound))
238 if (MI->addRegisterDead(IncomingReg, TRI, AddIfNotFound))
H A DVirtRegMap.h43 const TargetRegisterInfo *TRI; member in class:llvm::VirtRegMap
86 const TargetRegisterInfo &getTargetRegInfo() const { return *TRI; }
H A DLiveRegMatrix.h41 const TargetRegisterInfo *TRI; member in class:llvm::LiveRegMatrix
H A DRegisterClassInfo.h53 const TargetRegisterInfo *TRI; member in class:llvm::RegisterClassInfo
116 /// This is the smallest value returned by TRI->getCostPerUse(Reg) for all
125 /// same cost according to TRI->getCostPerUse().
/external/llvm/lib/Target/R600/
H A DSIInsertWaits.cpp50 const SIRegisterInfo &TRI; member in class:__anon9785::SIInsertWaits
101 TRI(TII->getRegisterInfo()) { }
140 unsigned Size = TRI.getMinimalPhysRegClass(Reg)->getSize();
185 unsigned Size = TRI.getMinimalPhysRegClass(Reg)->getSize();
190 Result.first = TRI.getEncodingValue(Reg);
H A DR600MachineScheduler.h38 const R600RegisterInfo *TRI; member in class:llvm::R600SchedStrategy
78 DAG(0), TII(0), TRI(0), MRI(0) {
H A DSIISelLowering.h25 const TargetRegisterInfo * TRI; member in class:llvm::SITargetLowering
/external/llvm/lib/CodeGen/
H A DProcessImplicitDefs.cpp29 const TargetRegisterInfo *TRI; member in class:__anon9497::ProcessImplicitDefs
110 !TRI->regsOverlap(Reg, UserReg))
145 TRI = MF.getTarget().getRegisterInfo();
H A DPrologEpilogInserter.cpp68 const TargetRegisterInfo *TRI = Fn.getTarget().getRegisterInfo(); local
73 RS = TRI->requiresRegisterScavenging(Fn) ? new RegScavenger() : NULL;
74 FrameIndexVirtualScavenging = TRI->requiresFrameIndexScavenging(Fn);
126 if (TRI->requiresRegisterScavenging(Fn) && FrameIndexVirtualScavenging)
290 const TargetRegisterInfo *TRI = Fn.getTarget().getRegisterInfo(); local
296 if (!TFI->spillCalleeSavedRegisters(*EntryBlock, I, CSI, TRI)) {
304 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
306 CSI[i].getFrameIdx(), RC, TRI);
328 if (!TFI->restoreCalleeSavedRegisters(*MBB, I, CSI, TRI)) {
331 const TargetRegisterClass *RC = TRI
713 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); local
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H A DLiveIntervalAnalysis.cpp103 TRI = TM->getRegisterInfo();
129 OS << PrintRegUnit(i, TRI) << " = " << *LI << '\n';
231 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
235 for (MCSuperRegIterator Supers(Root, TRI); Supers.isValid(); ++Supers) {
243 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
247 for (MCSuperRegIterator Supers(Root, TRI); Supers.isValid(); ++Supers) {
261 RegUnitIntervals.resize(TRI->getNumRegUnits());
281 for (MCRegUnitIterator Units(*LII, TRI); Units.isValid(); ++Units) {
290 DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI) << '#' << VNI->id);
420 MI->addRegisterDead(li->reg, TRI);
712 const TargetRegisterInfo& TRI; member in class:LiveIntervals::HMEditor
719 HMEditor(LiveIntervals& LIS, const MachineRegisterInfo& MRI, const TargetRegisterInfo& TRI, SlotIndex OldIdx, SlotIndex NewIdx, bool UpdateFlags) argument
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H A DCriticalAntiDepBreaker.h38 const TargetRegisterInfo *TRI; member in class:llvm::CriticalAntiDepBreaker
H A DEarlyIfConversion.cpp82 const TargetRegisterInfo *TRI; member in class:__anon9453::SSAIfConv
156 TRI = MF.getTarget().getRegisterInfo();
159 LiveRegUnits.setUniverse(TRI->getNumRegUnits());
161 ClobberedRegUnits.resize(TRI->getNumRegUnits());
239 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
295 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
303 for (MCRegUnitIterator Units(Reads.pop_back_val(), TRI); Units.isValid();
319 dbgs() << ' ' << PrintRegUnit(*i, TRI);
581 const TargetRegisterInfo *TRI; member in class:__anon9454::EarlyIfConverter
779 TRI
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H A DTargetInstrInfo.cpp40 const TargetRegisterInfo *TRI,
47 return TRI->getPointerRegClass(MF, RegClass);
54 return TRI->getRegClass(RegClass);
284 const TargetRegisterInfo &TRI) const {
286 MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
396 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); local
399 storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI);
401 loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, TRI);
532 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); local
533 if (MI->modifiesRegister(TLI.getStackPointerRegisterToSaveRestore(), TRI))
39 getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const argument
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H A DMachineInstrBundle.cpp108 const TargetRegisterInfo *TRI = TM.getRegisterInfo(); local
174 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
282 const TargetRegisterInfo *TRI) {
301 bool IsRegOrSuperReg = MOReg == Reg || TRI->isSubRegister(MOReg, Reg);
302 bool IsRegOrOverlapping = MOReg == Reg || TRI->regsOverlap(MOReg, Reg);
281 analyzePhysReg(unsigned Reg, const TargetRegisterInfo *TRI) argument
/external/llvm/lib/Target/Mips/
H A DMipsDelaySlotFiller.cpp107 const TargetRegisterInfo &TRI; member in class:__anon9744::RegDefsUses
293 : TRI(*TM.getRegisterInfo()), Defs(TRI.getNumRegs(), false),
294 Uses(TRI.getNumRegs(), false) {}
317 BitVector CallerSavedRegs(TRI.getNumRegs(), true);
322 for (const MCPhysReg *R = TRI.getCalleeSavedRegs(); *R; ++R)
323 for (MCRegAliasIterator AI(*R, &TRI, true); AI.isValid(); ++AI)
330 BitVector AllocSet = TRI.getAllocatableSet(MF);
333 for (MCRegAliasIterator AI(R, &TRI, false); AI.isValid(); ++AI)
353 BitVector NewDefs(TRI
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/external/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.h54 const TargetRegisterInfo *TRI) const;
59 const TargetRegisterInfo *TRI) const;
/external/llvm/lib/Target/Hexagon/
H A DHexagonNewValueJump.cpp91 const TargetRegisterInfo *TRI,
140 if (localBegin->modifiesRegister(Reg, TRI) ||
141 localBegin->readsRegister(Reg, TRI))
197 const TargetRegisterInfo *TRI,
253 if (localII->modifiesRegister(pReg, TRI) ||
254 localII->readsRegister(pReg, TRI))
264 if (localII->modifiesRegister(cmpReg1, TRI) ||
265 (secondReg && localII->modifiesRegister(cmpOp2, TRI)))
90 canBeFeederToNewValueJump(const HexagonInstrInfo *QII, const TargetRegisterInfo *TRI, MachineBasicBlock::iterator II, MachineBasicBlock::iterator end, MachineBasicBlock::iterator skip, MachineFunction &MF) argument
196 canCompareBeNewValueJump(const HexagonInstrInfo *QII, const TargetRegisterInfo *TRI, MachineBasicBlock::iterator II, unsigned pReg, bool secondReg, bool optLocation, MachineBasicBlock::iterator end, MachineFunction &MF) argument
/external/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.h132 const TargetRegisterInfo *TRI) const;
138 const TargetRegisterInfo *TRI) const;
/external/llvm/include/llvm/Target/
H A DTargetInstrInfo.h62 const TargetRegisterInfo *TRI,
185 const TargetRegisterInfo &TRI) const;
481 const TargetRegisterInfo *TRI) const {
494 const TargetRegisterInfo *TRI) const {
623 const TargetRegisterInfo *TRI) const {
943 const TargetRegisterInfo *TRI) const {
967 const TargetRegisterInfo *TRI) const {}
/external/llvm/lib/Target/X86/
H A DX86InstrInfo.h193 const TargetRegisterInfo &TRI) const;
241 const TargetRegisterInfo *TRI) const;
254 const TargetRegisterInfo *TRI) const;
361 const TargetRegisterInfo *TRI) const;
363 const TargetRegisterInfo *TRI) const;
/external/llvm/lib/CodeGen/SelectionDAG/
H A DResourcePriorityQueue.cpp48 TRI = IS->getTargetLowering().getTargetMachine().getRegisterInfo();
57 unsigned NumRC = TRI->getNumRegClasses();
62 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
63 E = TRI->regclass_end(); I != E; ++I)
64 RegLimit[(*I)->getID()] = TRI->getRegPressureLimit(*I, *IS->MF);
368 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
369 E = TRI->regclass_end(); I != E; ++I) {
375 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
376 E = TRI->regclass_end(); I != E; ++I) {

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