| /external/llvm/lib/CodeGen/ |
| H A D | CallingConvLower.cpp | 86 bool CCState::CheckReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, argument
89 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
90 MVT VT = Outs[i].VT;
91 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
100 void CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, argument
103 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
104 MVT VT = Outs[i].VT;
105 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
118 void CCState::AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, argument
120 unsigned NumOps = Outs
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonCallingConvLower.cpp | 94 Hexagon_CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, argument
116 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
117 EVT VT = Outs[i].VT;
118 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
132 &Outs,
136 unsigned NumOps = Outs.size();
147 EVT ArgVT = Outs[i].VT;
148 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
131 AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, Hexagon_CCAssignFn Fn, int NonVarArgsParams, unsigned SretValueSize) argument
|
| H A D | HexagonCallingConvLower.h | 85 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
90 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| H A D | HexagonISelLowering.h | 89 SmallVectorImpl<ISD::OutputArg> &Outs,
131 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| H A D | HexagonISelLowering.cpp | 303 const SmallVectorImpl<ISD::OutputArg> &Outs,
315 CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon);
386 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; local
395 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
421 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_VarArg);
423 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon);
432 Outs, OutVals, Ins, DAG);
460 ISD::ArgFlagsTy Flags = Outs[
301 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, DebugLoc dl, SelectionDAG &DAG) const argument
1642 IsEligibleForTailCallOptimization( SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet, bool isCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const argument
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.h | 130 const SmallVectorImpl<ISD::OutputArg> &Outs,
163 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| H A D | MSP430ISelLowering.cpp | 280 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; local
298 Outs, OutVals, Ins, dl, DAG, InVals);
408 const SmallVectorImpl<ISD::OutputArg> &Outs,
416 if (CallConv == CallingConv::MSP430_INTR && !Outs.empty())
424 CCInfo.AnalyzeReturn(Outs, RetCC_MSP430);
463 &Outs,
473 CCInfo.AnalyzeCallOperands(Outs, CC_MSP430);
521 ISD::ArgFlagsTy Flags = Outs[i].Flags;
406 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, DebugLoc dl, SelectionDAG &DAG) const argument
459 LowerCCCCallTo(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
|
| /external/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.h | 85 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| H A D | SparcISelLowering.cpp | 82 const SmallVectorImpl<ISD::OutputArg> &Outs,
96 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
349 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; local
365 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32);
377 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
378 ISD::ArgFlagsTy Flags = Outs[i].Flags;
411 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
80 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, DebugLoc dl, SelectionDAG &DAG) const argument
|
| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.h | 542 const SmallVectorImpl<ISD::OutputArg> &Outs,
548 const SmallVectorImpl<ISD::OutputArg> &Outs,
589 const SmallVectorImpl<ISD::OutputArg> &Outs,
598 const SmallVectorImpl<ISD::OutputArg> &Outs,
606 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.h | 224 void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
236 void analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
389 const SmallVectorImpl<ISD::OutputArg> &Outs,
395 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/llvm/include/llvm/CodeGen/ |
| H A D | CallingConvLower.h | 202 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
213 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 133 const SmallVectorImpl<ISD::OutputArg> &Outs,
158 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.h | 123 const SmallVectorImpl<ISD::OutputArg> &Outs,
187 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| H A D | XCoreISelLowering.cpp | 899 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; local
919 Outs, OutVals, Ins, dl, DAG, InVals);
931 const SmallVectorImpl<ISD::OutputArg> &Outs,
946 CCInfo.AnalyzeCallOperands(Outs, CC_XCore);
1227 const SmallVectorImpl<ISD::OutputArg> &Outs,
1231 return CCInfo.CheckReturn(Outs, RetCC_XCore);
1237 const SmallVectorImpl<ISD::OutputArg> &Outs,
1250 CCInfo.AnalyzeReturn(Outs, RetCC_XCore);
928 LowerCCCCallTo(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1225 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const argument
1235 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, DebugLoc dl, SelectionDAG &DAG) const argument
|
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 502 const SmallVectorImpl<ISD::OutputArg> &Outs,
509 const SmallVectorImpl<ISD::OutputArg> &Outs,
515 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| H A D | A15SDOptimizer.cpp | 115 SmallVectorImpl<MachineInstr*> &Outs);
368 SmallVectorImpl<MachineInstr*> &Outs) {
402 Outs.push_back(MI);
367 elideCopiesAndPHIs(MachineInstr *MI, SmallVectorImpl<MachineInstr*> &Outs) argument
|
| /external/llvm/lib/Target/MBlaze/ |
| H A D | MBlazeISelLowering.h | 141 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| H A D | MBlazeISelLowering.cpp | 690 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; local
714 CCInfo.AnalyzeCallOperands(Outs, CC_MBlaze);
1018 const SmallVectorImpl<ISD::OutputArg> &Outs,
1030 CCInfo.AnalyzeReturn(Outs, RetCC_MBlaze);
1017 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, DebugLoc dl, SelectionDAG &DAG) const argument
|
| /external/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 253 const SmallVectorImpl<ISD::OutputArg> &Outs,
350 if (Outs[i].Flags.isByVal() == false) {
373 unsigned align = Outs[i].Flags.getByValAlign();
415 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; local
432 assert((Outs.size() == Args.size()) &&
437 for (unsigned i=0, e=Outs.size(); i!=e; ++i) {
438 EVT VT = Outs[i].VT;
440 if (Outs[i].Flags.isByVal() == false) {
466 if (Outs[
251 getPrototype(Type *retTy, const ArgListTy &Args, const SmallVectorImpl<ISD::OutputArg> &Outs, unsigned retAlignment) const argument
1200 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, DebugLoc dl, SelectionDAG &DAG) const argument
[all...] |
| H A D | NVPTXISelLowering.h | 128 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/llvm/lib/Target/R600/ |
| H A D | AMDGPUISelLowering.h | 50 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FunctionLoweringInfo.cpp | 68 SmallVector<ISD::OutputArg, 4> Outs; local
69 GetReturnInfo(Fn->getReturnType(), Fn->getAttributes(), Outs, TLI);
72 Outs, Fn->getContext());
|
| /external/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.h | 773 const SmallVectorImpl<ISD::OutputArg> &Outs,
863 const SmallVectorImpl<ISD::OutputArg> &Outs,
877 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| H A D | X86FastISel.cpp | 746 SmallVector<ISD::OutputArg, 4> Outs; local
747 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI);
753 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
786 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt())
792 if (Outs[0].Flags.isSExt())
797 unsigned Op = Outs[0].Flags.isZExt() ? ISD::ZERO_EXTEND :
1667 SmallVector<ISD::OutputArg, 4> Outs;
1668 GetReturnInfo(I->getType(), CS.getAttributes(), Outs, TLI);
1671 Outs, FT
[all...] |