Searched refs:TII (Results 1 - 25 of 193) sorted by relevance

12345678

/external/llvm/lib/Target/R600/
H A DR600ExpandSpecialInstrs.cpp34 const R600InstrInfo *TII; member in class:__anon9782::R600ExpandSpecialInstrsPass
41 TII (static_cast<const R600InstrInfo *>(tm.getInstrInfo())) { }
60 const R600RegisterInfo &TRI = TII->getRegisterInfo();
77 MachineInstr *PredSet = TII->buildDefaultInstruction(MBB, I,
82 TII->addFlag(PredSet, 0, MO_FLAG_MASK);
84 TII->setImmOperand(PredSet, R600Operands::UPDATE_EXEC_MASK, 1);
86 TII->setImmOperand(PredSet, R600Operands::UPDATE_PREDICATE, 1);
92 MachineInstr *PredSet = TII->buildDefaultInstruction(MBB, I,
97 TII->addFlag(PredSet, 0, MO_FLAG_MASK);
98 TII
[all...]
H A DAMDGPUIndirectAddressing.cpp35 const AMDGPUInstrInfo *TII; member in class:__anon9769::AMDGPUIndirectAddressingPass
42 TII(static_cast<const AMDGPUInstrInfo*>(tm.getInstrInfo()))
62 int IndirectBegin = TII->getIndirectIndexBegin(MF);
63 int IndirectEnd = TII->getIndirectIndexEnd(MF);
90 if (!TII->isRegisterStore(MI)) {
98 unsigned Address = TII->calculateIndirectAddress(RegIndex, Channel);
100 TII->getIndirectAddrStoreRegClass(MI.getOperand(0).getReg());
106 BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDGPU::COPY), DstReg)
113 MachineInstrBuilder MOV = TII->buildIndirectWrite(BB, I,
118 unsigned Addr = TII
[all...]
H A DAMDGPUConvertToISA.cpp49 const AMDGPUInstrInfo * TII = local
58 TII->convertToISA(MI, MF, MBB.findDebugLoc(I));
H A DR600RegisterInfo.h28 const TargetInstrInfo &TII; member in struct:llvm::R600RegisterInfo
H A DSIRegisterInfo.h28 const TargetInstrInfo &TII; member in struct:llvm::SIRegisterInfo
H A DSILowerControlFlow.cpp70 const TargetInstrInfo *TII; member in class:__anon9788::SILowerControlFlowPass
95 TII(tm.getInstrInfo()) { }
139 BuildMI(*From.getParent(), &From, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ))
156 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
161 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::EXP))
173 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM));
182 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), Reg)
185 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), Reg)
200 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_SAVEEXEC_B64), Dst)
203 BuildMI(MBB, &MI, DL, TII
[all...]
/external/llvm/lib/Target/Mips/
H A DMipsSERegisterInfo.h24 const MipsSEInstrInfo &TII; member in class:llvm::MipsSERegisterInfo
28 const MipsSEInstrInfo &TII);
H A DMips16RegisterInfo.h23 const Mips16InstrInfo &TII; member in class:llvm::Mips16RegisterInfo
26 const Mips16InstrInfo &TII);
H A DMipsConstantIslandPass.cpp53 TII(static_cast<const MipsInstrInfo*>(tm.getInstrInfo())),
67 const MipsInstrInfo *TII; member in class:__anon9743::MipsConstantIslands
H A DMipsLongBranch.cpp68 TII(static_cast<const MipsInstrInfo*>(tm.getInstrInfo())),
88 const MipsInstrInfo *TII; member in class:__anon9745::MipsLongBranch
181 MBBInfos[I].Size += TII->GetInstSizeInBytes(&*MI);
220 unsigned NewOpc = TII->GetOppositeBranchOpc(Br->getOpcode());
221 const MCInstrDesc &NewDesc = TII->get(NewOpc);
283 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
285 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA)
289 .append(BuildMI(*MF, DL, TII->get(Mips::BAL_BR)).addMBB(BalTgtMBB))
290 .append(BuildMI(*MF, DL, TII->get(Mips::LUi), Mips::AT).addImm(Hi));
294 BuildMI(*BalTgtMBB, Pos, DL, TII
390 emitGPDisp(MachineFunction &F, const MipsInstrInfo *TII) argument
[all...]
/external/llvm/lib/Target/Hexagon/
H A DHexagonExpandPredSpillCode.cpp67 const HexagonInstrInfo *TII = QTM.getInstrInfo(); local
88 if (!TII->isValidOffset(Hexagon::STriw_indexed, Offset)) {
89 if (!TII->isValidOffset(Hexagon::ADD_ri, Offset)) {
91 TII->get(Hexagon::CONST32_Int_Real),
93 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_rr),
96 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd),
99 TII->get(Hexagon::STriw_indexed))
103 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_ri),
105 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd),
108 TII
[all...]
H A DHexagonRegisterInfo.cpp44 TII(tii) {
145 TII.isValidOffset(MI.getOpcode(), (FrameSize+Offset)) &&
146 !TII.isSpillPredRegOp(&MI)) {
153 if (!TII.isValidOffset(MI.getOpcode(), Offset)) {
175 if (!TII.isValidOffset(Hexagon::ADD_ri, Offset)) {
177 TII.get(Hexagon::CONST32_Int_Real), dstReg).addImm(Offset);
179 TII.get(Hexagon::ADD_rr),
183 TII.get(Hexagon::ADD_ri),
204 if (!TII.isValidOffset(Hexagon::ADD_ri, Offset)) {
206 TII
[all...]
H A DHexagonSplitTFRCondSets.cpp75 const TargetInstrInfo *TII = QTM.getInstrInfo(); local
107 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Opc1),
111 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Opc2),
127 TII->get(Hexagon::TFR_cPt), DestReg).
132 TII->get(Hexagon::TFRI_cNotPt), DestReg).
137 TII->get(Hexagon::TFRI_cNotPt_f), DestReg).
153 TII->get(Hexagon::TFRI_cPt), DestReg).
158 TII->get(Hexagon::TFRI_cPt_f), DestReg).
167 TII->get(Hexagon::TFR_cNotPt), DestReg).
183 TII
[all...]
H A DHexagonFrameLowering.cpp145 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local
149 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::ALLOCFRAME)).addImm(0);
152 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::CONST32_Int_Real),
154 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::SUB_rr),
159 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::ALLOCFRAME)).addImm(NumBytes);
188 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local
197 BuildMI(MBB, MBBI_end, dl, TII.get(Hexagon::DEALLOC_RET_V4))
200 BuildMI(MBB, MBBI, dl, TII.get(Hexagon::DEALLOCFRAME)).addImm(NumBytes);
230 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); local
261 TII
285 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); local
[all...]
/external/llvm/lib/Target/Sparc/
H A DSparcFrameLowering.cpp32 const SparcInstrInfo &TII = local
55 BuildMI(MBB, MBBI, dl, TII.get(SP::SAVEri), SP::O6)
61 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
63 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
65 BuildMI(MBB, MBBI, dl, TII.get(SP::SAVErr), SP::O6)
78 const SparcInstrInfo &TII = local
81 BuildMI(MBB, I, dl, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size);
89 const SparcInstrInfo &TII = local
94 BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
/external/llvm/lib/Target/MSP430/
H A DMSP430FrameLowering.cpp45 const MSP430InstrInfo &TII = local
66 BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r))
70 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FPW)
98 BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SPW)
110 const MSP430InstrInfo &TII = local
135 BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FPW);
157 TII.get(MSP430::MOV16rr), MSP430::SPW).addReg(MSP430::FPW);
161 TII.get(MSP430::SUB16ri), MSP430::SPW)
170 BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SPW)
191 const TargetInstrInfo &TII local
217 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local
228 const MSP430InstrInfo &TII = local
[all...]
H A DMSP430BranchSelector.cpp55 const MSP430InstrInfo *TII = local
70 BlockSize += TII->GetInstSizeInBytes(MBBI);
107 MBBStartOffset += TII->GetInstSizeInBytes(I);
154 TII->ReverseBranchCondition(Cond);
155 BuildMI(MBB, I, dl, TII->get(MSP430::JCC))
161 I = BuildMI(MBB, I, dl, TII->get(MSP430::Bi)).addMBB(Dest);
/external/llvm/lib/Target/ARM/
H A DThumb1FrameLowering.cpp39 const TargetInstrInfo &TII, DebugLoc dl,
42 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
50 const Thumb1InstrInfo &TII = local
71 emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount);
74 emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount);
88 const Thumb1InstrInfo &TII = local
108 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -VARegSaveSize,
113 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
173 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
184 emitSPUpdate(MBB, MBBI, TII, d
37 emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const TargetInstrInfo &TII, DebugLoc dl, const Thumb1RegisterInfo &MRI, int NumBytes, unsigned MIFlags = MachineInstr::NoFlags) argument
249 const Thumb1InstrInfo &TII = local
338 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local
377 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local
[all...]
H A DARMHazardRecognizer.h31 const ARMBaseInstrInfo &TII; member in class:llvm::ARMHazardRecognizer
44 ScoreboardHazardRecognizer(ItinData, DAG, "post-RA-sched"), TII(tii),
/external/llvm/lib/Target/PowerPC/
H A DPPCBranchSelector.cpp65 const PPCInstrInfo *TII = local
80 BlockSize += TII->GetInstSizeInBytes(MBBI);
116 MBBStartOffset += TII->GetInstSizeInBytes(I);
161 BuildMI(MBB, I, dl, TII->get(PPC::BCC))
164 BuildMI(MBB, I, dl, TII->get(PPC::BDZ)).addImm(2);
166 BuildMI(MBB, I, dl, TII->get(PPC::BDZ8)).addImm(2);
168 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ)).addImm(2);
170 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ8)).addImm(2);
176 I = BuildMI(MBB, I, dl, TII->get(PPC::B)).addMBB(Dest);
H A DPPCFrameLowering.cpp104 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { argument
151 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
155 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
160 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
164 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
169 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
173 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
177 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
307 const PPCInstrInfo &TII = local
323 HandleVRSaveUpdate(MBBI, TII);
575 const PPCInstrInfo &TII = local
1079 const PPCInstrInfo &TII = local
1136 const PPCInstrInfo &TII = local
1173 const PPCInstrInfo &TII = local
1223 const PPCInstrInfo &TII = local
[all...]
/external/llvm/include/llvm/CodeGen/
H A DTargetSchedule.h38 const TargetInstrInfo *TII; member in class:llvm::TargetSchedModel
44 TargetSchedModel(): STI(0), TII(0) {}
58 const TargetInstrInfo *getInstrInfo() const { return TII; }
/external/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.cpp41 : XCoreGenRegisterInfo(XCore::LR), TII(tii) {
171 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
176 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r))
182 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
192 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
197 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
203 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
221 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
226 BuildMI(MBB, II, dl, TII.get(NewOpcode))
232 BuildMI(MBB, II, dl, TII
[all...]
H A DXCoreFrameLowering.cpp48 const TargetInstrInfo &TII) {
55 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg)
63 const TargetInstrInfo &TII) {
70 BuildMI(MBB, I, dl, TII.get(Opcode))
95 const XCoreInstrInfo &TII = local
104 loadFromStack(MBB, MBBI, XCore::R11, 0, dl, TII);
132 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
139 BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(FrameLabel);
153 storeToStack(MBB, MBBI, XCore::LR, LRSpillOffset + FrameSize*4, dl, TII);
158 BuildMI(MBB, MBBI, dl, TII
45 loadFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DstReg, int Offset, DebugLoc dl, const TargetInstrInfo &TII) argument
60 storeToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, int Offset, DebugLoc dl, const TargetInstrInfo &TII) argument
214 const XCoreInstrInfo &TII = local
278 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); local
309 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); local
340 const XCoreInstrInfo &TII = local
[all...]
/external/llvm/lib/CodeGen/
H A DTargetSchedule.cpp59 TII = tii;
81 return (UOps >= 0) ? UOps : TII->getNumMicroOps(&InstrItins, MI);
117 return TII->defaultDefLatency(&SchedModel, DefMI);
189 TII->getOperandLatency(&InstrItins, DefMI, DefOperIdx, UseMI, UseOperIdx);
199 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, DefMI);
202 // Rather than directly querying InstrItins stage latency, we call a TII
205 // special cases without TII hooks.
208 TII->defaultDefLatency(&SchedModel, DefMI));
246 return DefMI->isTransient() ? 0 : TII->defaultDefLatency(&SchedModel, DefMI);
253 return TII
[all...]

Completed in 362 milliseconds

12345678