Searched defs:NumVecs (Results 1 - 2 of 2) sorted by relevance
/external/llvm/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 205 /// SelectVLD - Select NEON load intrinsics. NumVecs should be 208 /// For NumVecs <= 2, QOpcodes1 is not used. 209 SDNode *SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs, 213 /// SelectVST - Select NEON store intrinsics. NumVecs should 216 /// For NumVecs <= 2, QOpcodes1 is not used. 217 SDNode *SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs, 221 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should 225 bool isUpdating, unsigned NumVecs, 228 /// SelectVLDDup - Select NEON load-duplicate intrinsics. NumVecs 231 SDNode *SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs, 1665 GetVLDSTAlign(SDValue Align, unsigned NumVecs, bool is64BitVector) argument 1730 SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs, const uint16_t *DOpcodes, const uint16_t *QOpcodes0, const uint16_t *QOpcodes1) argument 1862 SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs, const uint16_t *DOpcodes, const uint16_t *QOpcodes0, const uint16_t *QOpcodes1) argument 2007 SelectVLDSTLane(SDNode *N, bool IsLoad, bool isUpdating, unsigned NumVecs, const uint16_t *DOpcodes, const uint16_t *QOpcodes) argument 2126 SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs, const uint16_t *Opcodes) argument 2209 SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc) argument [all...] |
H A D | ARMISelLowering.cpp | 9043 unsigned NumVecs = 0; local 9049 NumVecs = 1; break; 9051 NumVecs = 2; break; 9053 NumVecs = 3; break; 9055 NumVecs = 4; break; 9057 NumVecs = 2; isLaneOp = true; break; 9059 NumVecs = 3; isLaneOp = true; break; 9061 NumVecs = 4; isLaneOp = true; break; 9063 NumVecs = 1; isLoad = false; break; 9065 NumVecs 9160 unsigned NumVecs = 0; local [all...] |
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