| /external/llvm/lib/Target/ARM/ |
| H A D | ARMFrameLowering.cpp | 659 bool isTailCall = (RetOpcode == ARM::TCRETURNdi || local
675 if (Reg == ARM::LR && !isTailCall && !isVarArg && STI.hasV5TOps()) {
|
| H A D | ARMISelLowering.cpp | 1405 bool &isTailCall = CLI.IsTailCall; local
1416 isTailCall = false;
1417 if (isTailCall) {
1419 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1424 if (isTailCall) {
1584 if (!isTailCall)
1592 if (isTailCall) {
1771 if (isTailCall)
2221 if (!CI->isTailCall())
2315 0, CallingConv::C, /*isTailCall
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 287 bool &isTailCall = CLI.IsTailCall; local
292 isTailCall = false;
299 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
463 bool isTailCall,
461 LowerCCCCallTo(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
|
| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 391 bool &isTailCall = CLI.IsTailCall; local
426 if(isTailCall) {
429 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
436 isTailCall = false;
440 if (isTailCall) {
514 if (!isTailCall)
524 if (!isTailCall) {
533 if (isTailCall) {
584 if (isTailCall)
|
| /external/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 501 bool &isTailCall = CLI.IsTailCall; local
1107 // set isTailCall to false for now, until we figure out how to express
1109 isTailCall = false;
|
| /external/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 662 bool &isTailCall = CLI.IsTailCall; local
667 isTailCall = false;
|
| /external/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 702 bool &isTailCall = CLI.IsTailCall; local
709 isTailCall = false;
|
| /external/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 442 false, false, 0, CallingConv::C, /*isTailCall=*/false,
505 false, false, 0, CallingConv::C, /*isTailCall=*/false,
858 bool &isTailCall = CLI.IsTailCall; local
863 isTailCall = false;
872 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
880 /// TODO: isTailCall, sret.
884 bool isTailCall,
882 LowerCCCCallTo(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
|
| /external/llvm/include/llvm/IR/ |
| H A D | Instructions.h | 1238 bool isTailCall() const { return getSubclassDataFromInstruction() & 1; } function in class:llvm::CallInst
|
| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1845 // isTailCall may be true since the callee does not reference caller stack
1848 bool isTailCall = isInTailCallPosition(DAG, Op.getNode(), TCChain); local
1849 if (isTailCall)
1854 0, getLibcallCallingConv(Call), isTailCall,
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.cpp | 5121 /*isTailCall=*/false,
5217 bool isTailCall,
5313 if (isTailCall && !isInTailCallPosition(CS, *TLI))
5314 isTailCall = false;
5317 CallLoweringInfo CLI(getRoot(), RetTy, FTy, isTailCall, Callee, Args, DAG, local
5320 assert((isTailCall || Result.second.getNode()) &&
5682 LowerCallTo(&I, Callee, I.isTailCall());
5216 LowerCallTo(ImmutableCallSite CS, SDValue Callee, bool isTailCall, MachineBasicBlock *LandingPad) argument
|
| /external/llvm/lib/IR/ |
| H A D | Core.cpp | 1782 return unwrap<CallInst>(Call)->isTailCall();
1785 void LLVMSetTailCall(LLVMValueRef Call, LLVMBool isTailCall) { argument
1786 unwrap<CallInst>(Call)->setTailCall(isTailCall);
|
| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 1708 /*isTailCall=*/false,
2892 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall, argument
2895 if (!isTailCall) return 0;
3100 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3105 if (!isTailCall) {
3152 SDValue &Chain, SDLoc dl, int SPDiff, bool isTailCall,
3303 if (isTailCall)
3313 if (isTailCall)
3382 bool isTailCall, bool isVarArg,
3394 isTailCall, RegsToPas
3098 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue Arg, SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64, bool isTailCall, bool isVector, SmallVectorImpl<SDValue> &MemOpChains, SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments, SDLoc dl) argument
3151 PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag, SDValue &Chain, SDLoc dl, int SPDiff, bool isTailCall, SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass, SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys, const PPCSubtarget &PPCSubTarget) argument
3381 FinishCall(CallingConv::ID CallConv, SDLoc dl, bool isTailCall, bool isVarArg, SelectionDAG &DAG, SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, SDValue InFlag, SDValue Chain, SDValue &Callee, int SPDiff, unsigned NumBytes, const SmallVectorImpl<ISD::InputArg> &Ins, SmallVectorImpl<SDValue> &InVals) const argument
3486 bool &isTailCall = CLI.IsTailCall; local
3511 LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
3746 LowerCall_64SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
4118 LowerCall_Darwin(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
[all...] |
| /external/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 2072 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2479 bool &isTailCall = CLI.IsTailCall; local
2490 isTailCall = false;
2492 if (isTailCall) {
2494 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2501 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2504 if (isTailCall)
2533 if (isTailCall && !IsSibcall) {
2552 if (isTailCall && FPDiff)
2553 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
[all...] |