/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | AMDGPUISelLowering.cpp | 1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===// 53 DebugLoc DL, SelectionDAG &DAG, 70 DebugLoc DL, SelectionDAG &DAG) const 72 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain); 79 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) 88 // AMDIL DAG lowering 89 case ISD::SDIV: return LowerSDIV(Op, DAG); 90 case ISD::SREM: return LowerSREM(Op, DAG); 91 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 92 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG); 48 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 313 CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const argument [all...] |
H A D | R600ISelLowering.h | 1 //===-- R600ISelLowering.h - R600 DAG Lowering Interface -*- C++ -*--------===// 10 // R600 DAG Lowering interface definition 29 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 38 SDValue LowerImplicitParameter(SelectionDAG &DAG, EVT VT, 44 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 47 SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const; 49 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 50 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
|
H A D | AMDGPUISelLowering.h | 27 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 28 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const; 33 /// of the DAG's MachineFunction. This returns a Register SDNode representing 35 SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, 47 DebugLoc DL, SelectionDAG &DAG, 54 DebugLoc DL, SelectionDAG &DAG) const; 56 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 57 SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const; 58 SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const; 70 const SelectionDAG &DAG, [all...] |
/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDGPUISelLowering.cpp | 1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===// 53 DebugLoc DL, SelectionDAG &DAG, 70 DebugLoc DL, SelectionDAG &DAG) const 72 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain); 79 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) 88 // AMDIL DAG lowering 89 case ISD::SDIV: return LowerSDIV(Op, DAG); 90 case ISD::SREM: return LowerSREM(Op, DAG); 91 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 92 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG); 48 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 313 CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const argument [all...] |
H A D | R600ISelLowering.h | 1 //===-- R600ISelLowering.h - R600 DAG Lowering Interface -*- C++ -*--------===// 10 // R600 DAG Lowering interface definition 29 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 38 SDValue LowerImplicitParameter(SelectionDAG &DAG, EVT VT, 44 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 47 SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const; 49 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 50 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
|
H A D | AMDGPUISelLowering.h | 27 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 28 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const; 33 /// of the DAG's MachineFunction. This returns a Register SDNode representing 35 SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, 47 DebugLoc DL, SelectionDAG &DAG, 54 DebugLoc DL, SelectionDAG &DAG) const; 56 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 57 SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const; 58 SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const; 70 const SelectionDAG &DAG, [all...] |
/external/llvm/lib/Target/R600/ |
H A D | R600ISelLowering.h | 1 //===-- R600ISelLowering.h - R600 DAG Lowering Interface -*- C++ -*--------===// 11 /// \brief R600 DAG Lowering interface definition 29 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 33 SelectionDAG &DAG) const; 39 SDLoc DL, SelectionDAG &DAG, 48 SDValue LowerImplicitParameter(SelectionDAG &DAG, EVT VT, 53 SDValue OptimizeSwizzle(SDValue BuildVector, SDValue Swz[], SelectionDAG &DAG) const; 56 SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const; 58 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 59 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) cons [all...] |
H A D | AMDGPUISelLowering.h | 28 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 29 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const; 33 /// \brief Helper function that adds Reg to the LiveIn list of the DAG's 37 virtual SDValue CreateLiveInRegister(SelectionDAG &DAG, 41 SelectionDAG &DAG) const; 59 SDLoc DL, SelectionDAG &DAG) const; 66 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 67 SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const; 68 SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const; 69 SDValue LowerMinMax(SDValue Op, SelectionDAG &DAG) cons [all...] |
H A D | SIISelLowering.h | 1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===// 11 /// \brief SI DAG Lowering interface definition 24 SDValue LowerParameter(SelectionDAG &DAG, EVT VT, SDLoc DL, 26 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 27 SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const; 28 SDValue LowerZERO_EXTEND(SDValue Op, SelectionDAG &DAG) const; 29 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 33 const TargetRegisterClass *getRegClassForNode(SelectionDAG &DAG, 35 bool fitsRegClass(SelectionDAG &DAG, const SDValue &Op, 37 void ensureSRegLimit(SelectionDAG &DAG, SDValu [all...] |
H A D | AMDGPUISelLowering.cpp | 1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===// 163 SDLoc DL, SelectionDAG &DAG) const { 164 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain); 171 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) 179 // AMDIL DAG lowering 180 case ISD::SDIV: return LowerSDIV(Op, DAG); 181 case ISD::SREM: return LowerSREM(Op, DAG); 182 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG); 183 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 184 // AMDGPU DAG lowerin 469 CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const argument [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86SelectionDAGInfo.cpp | 30 X86SelectionDAGInfo::EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl, argument 57 Type *IntPtrTy = getDataLayout()->getIntPtrType(*DAG.getContext()); 66 CallLoweringInfo CLI(Chain, Type::getVoidTy(*DAG.getContext()), 70 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, 71 DAG, dl); 113 Count = DAG.getIntPtrConstant(SizeVal); 119 Count = DAG.getIntPtrConstant(SizeVal / UBytes); 123 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT), 128 Count = DAG 178 EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument [all...] |
H A D | X86ISelLowering.h | 1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===// 11 // selection DAG. 29 // X86 Specific DAG Nodes 521 SelectionDAG &DAG) const; 563 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 569 SelectionDAG &DAG) const; 592 /// DAG node. 604 const SelectionDAG &DAG, 615 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const; 635 SelectionDAG &DAG) cons [all...] |
/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZSelectionDAGInfo.cpp | 29 EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc DL, SDValue Chain, argument 41 return DAG.getNode(SystemZISD::MVC, DL, MVT::Other, 51 static SDValue memsetStore(SelectionDAG &DAG, SDLoc DL, SDValue Chain, argument 58 return DAG.getStore(Chain, DL, 59 DAG.getConstant(StoreVal, MVT::getIntegerVT(Size * 8)), 64 EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc DL, SDValue Chain, argument 88 SDValue Chain1 = memsetStore(DAG, DL, Chain, Dst, ByteVal, Size1, 92 Dst = DAG.getNode(ISD::ADD, DL, DstVT, Dst, 93 DAG.getConstant(Size1, DstVT)); 95 SDValue Chain2 = memsetStore(DAG, D [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.h | 1 //===-- HexagonISelLowering.h - Hexagon DAG Lowering Interface --*- C++ -*-===// 11 // selection DAG. 93 SelectionDAG& DAG) const; 100 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 103 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 104 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 105 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const; 106 SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const; 107 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const; 111 SDLoc dl, SelectionDAG &DAG, [all...] |
/external/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.h | 1 //===-- MSP430ISelLowering.h - MSP430 DAG Lowering Interface ----*- C++ -*-===// 11 // selection DAG. 79 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 82 /// DAG node. 85 SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const; 86 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 87 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 88 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const; 89 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 90 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) cons [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.h | 1 //==-- AArch64ISelLowering.h - AArch64 DAG Lowering Interface ----*- C++ -*-==// 11 // selection DAG. 49 // load instruction. This prevents the DAG combiner folding a truncate to 64 /// these are pre-encoded since DAG matching can't cope with combining LSB 101 /// these are pre-encoded since DAG matching can't cope with combining LSB 154 SDLoc dl, SelectionDAG &DAG, 161 SDLoc dl, SelectionDAG &DAG) const; 169 SDLoc dl, SelectionDAG &DAG, 172 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, 175 void SaveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, SDLo [all...] |
H A D | AArch64ISelLowering.cpp | 1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation -----===// 11 // selection DAG. 878 AArch64TargetLowering::SaveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, argument 880 MachineFunction &MF = DAG.getMachineFunction(); 897 SDValue FIN = DAG.getFrameIndex(GPRIdx, getPointerTy()); 901 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64); 902 SDValue Store = DAG.getStore(Val.getValue(1), DL, Val, FIN, 906 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN, 907 DAG.getConstant(8, getPointerTy())); 916 SDValue FIN = DAG 947 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 1137 SelectionDAG &DAG = CLI.DAG; local 1399 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 1562 addTokenForArgument(SDValue Chain, SelectionDAG &DAG, MachineFrameInfo *MFI, int ClobberedFI) const argument 1622 getSelectableIntSetCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &A64cc, SelectionDAG &DAG, SDLoc &dl) const argument 1823 LowerF128ToCall(SDValue Op, SelectionDAG &DAG, RTLIB::Libcall Call) const argument 1892 LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, bool IsSigned) const argument 2168 LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG, bool IsSigned) const argument 2290 LowerVectorSETCC(SDValue Op, SelectionDAG &DAG) argument 2676 isNeonModifiedImm(uint64_t SplatBits, uint64_t SplatUndef, unsigned SplatBitSize, SelectionDAG &DAG, bool is128Bits, NeonModImmType type, EVT &VT, unsigned &Imm, unsigned &OpCmode) argument 2817 SelectionDAG &DAG = DCI.DAG; local 2856 getLSBForBFI(SelectionDAG &DAG, SDLoc DL, EVT VT, SDValue &MaskedVal, uint64_t Mask) argument 2931 SelectionDAG &DAG = DCI.DAG; local 3012 SelectionDAG &DAG = DCI.DAG; local 3094 SelectionDAG &DAG = DCI.DAG; local 3138 SelectionDAG &DAG = DCI.DAG; local 3205 SelectionDAG &DAG = DCI.DAG; local 3275 LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, const AArch64Subtarget *ST) const argument [all...] |
/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 1 //===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===// 11 // selection DAG. 167 SDLoc DL, SelectionDAG &DAG) const { 169 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG); 170 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG); 178 SDLoc DL, SelectionDAG &DAG) const { 179 MachineFunction &MF = DAG.getMachineFunction(); 185 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 186 DAG.getTarget(), RVLocs, *DAG 313 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 331 LowerFormalArguments_32(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 531 LowerFormalArguments_64(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 655 SelectionDAG &DAG = CLI.DAG; local 912 getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const argument 1407 computeMaskedBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth) const argument 1552 LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) argument 1560 LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) argument 1568 LowerBR_CC(SDValue Op, SelectionDAG &DAG) argument 1597 LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) argument 1625 LowerVASTART(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI) argument 1645 LowerVAARG(SDValue Op, SelectionDAG &DAG) argument 1668 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) argument 1687 getFLUSHW(SDValue Op, SelectionDAG &DAG) argument 1694 LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) argument 1725 LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI) argument 1762 LowerF64Op(SDValue Op, SelectionDAG &DAG) argument [all...] |
/external/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.h | 1 //===-- XCoreISelLowering.h - XCore DAG Lowering Interface ------*- C++ -*-===// 11 // selection DAG. 90 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 96 SelectionDAG &DAG) const; 99 // DAG node. 118 SDLoc dl, SelectionDAG &DAG, 126 SDLoc dl, SelectionDAG &DAG, 131 SDLoc dl, SelectionDAG &DAG, 133 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const; 135 SelectionDAG &DAG) cons [all...] |
H A D | XCoreISelLowering.cpp | 1 //===-- XCoreISelLowering.cpp - XCore DAG Lowering Implementation ---------===// 170 LowerOperation(SDValue Op, SelectionDAG &DAG) const { 173 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 174 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 175 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 176 case ISD::BR_JT: return LowerBR_JT(Op, DAG); 177 case ISD::LOAD: return LowerLOAD(Op, DAG); 178 case ISD::STORE: return LowerSTORE(Op, DAG); 179 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 180 case ISD::VAARG: return LowerVAARG(Op, DAG); 262 BuildGetId(SelectionDAG &DAG, SDLoc dl) argument 366 isWordAligned(SDValue Value, SelectionDAG &DAG) argument 851 SelectionDAG &DAG = CLI.DAG; local 882 LowerCCCCallTo(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 1008 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 1042 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 1066 LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 1363 SelectionDAG &DAG = DCI.DAG; local 1555 computeMaskedBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth) const argument [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 1 //===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===// 143 SelectionDAG &DAG) const { 145 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG); 146 case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG); 147 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG); 148 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG); 149 case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG); 150 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG); 152 DAG); 153 case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG); 312 performADDECombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget *Subtarget) argument 325 performSUBECombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget *Subtarget) argument 338 genConstMult(SDValue X, uint64_t C, SDLoc DL, EVT VT, EVT ShiftTy, SelectionDAG &DAG) argument 376 performMULCombine(SDNode *N, SelectionDAG &DAG, const TargetLowering::DAGCombinerInfo &DCI, const MipsSETargetLowering *TL) argument 389 performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty, SelectionDAG &DAG, const MipsSubtarget *Subtarget) argument 410 performSHLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget *Subtarget) argument 421 performSRACombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget *Subtarget) argument 433 performSRLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget *Subtarget) argument 462 performSETCCCombine(SDNode *N, SelectionDAG &DAG) argument 475 performVSELECTCombine(SDNode *N, SelectionDAG &DAG) argument 493 SelectionDAG &DAG = DCI.DAG; local 591 initAccumulator(SDValue In, SDLoc DL, SelectionDAG &DAG) argument 599 extractLOHI(SDValue Op, SDLoc DL, SelectionDAG &DAG) argument 619 lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) argument [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMSelectionDAGInfo.cpp | 29 ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, argument 66 Loads[i] = DAG.getLoad(VT, dl, Chain, 67 DAG.getNode(ISD::ADD, dl, MVT::i32, Src, 68 DAG.getConstant(SrcOff, MVT::i32)), 74 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i); 78 TFOps[i] = DAG.getStore(Chain, dl, Loads[i], 79 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst, 80 DAG.getConstant(DstOff, MVT::i32)), 85 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i); 105 Loads[i] = DAG 143 EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo) const argument [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeVectorOps.cpp | 36 SelectionDAG& DAG; member in class:__anon22136::VectorLegalizer 84 DAG(dag), TLI(dag.getTargetLoweringInfo()), Changed(false) {} 90 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 91 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I) { 113 DAG.AssignTopologicalOrder(); 114 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 115 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I) 119 SDValue OldRoot = DAG.getRoot(); 121 DAG.setRoot(LegalizedNodes[OldRoot]); 126 DAG [all...] |
/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.h | 1 //===-- NVPTXISelLowering.h - NVPTX DAG Lowering Interface ------*- C++ -*-===// 11 // selection DAG. 82 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 84 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 86 SelectionDAG &DAG) const; 117 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, 132 SelectionDAG &DAG) const; 136 SelectionDAG &DAG) const; 148 SDValue getExtSymb(SelectionDAG &DAG, const char *name, int idx, 150 SDValue getParamSymbol(SelectionDAG &DAG, in [all...] |
H A D | NVPTXISelLowering.cpp | 10 // selection DAG. 337 NVPTXTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { 340 Op = DAG.getTargetGlobalAddress(GV, dl, getPointerTy()); 341 return DAG.getNode(NVPTXISD::Wrapper, dl, getPointerTy(), Op); 494 SelectionDAG &DAG = CLI.DAG; local 511 MachineFunction &MF = DAG.getMachineFunction(); 516 DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(uniqueCallSite, true), 546 SDVTList DeclareParamVTs = DAG 1308 getExtSymb(SelectionDAG &DAG, const char *inname, int idx, EVT v) const argument 1318 getParamSymbol(SelectionDAG &DAG, int idx, EVT v) const argument 1330 getParamHelpSymbol(SelectionDAG &DAG, int idx) argument 1360 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 2020 ReplaceLoadVector(SDNode *N, SelectionDAG &DAG, SmallVectorImpl<SDValue> &Results) argument 2112 ReplaceINTRINSIC_W_CHAIN(SDNode *N, SelectionDAG &DAG, SmallVectorImpl<SDValue> &Results) argument [all...] |