Searched refs:FSQRT (Results 1 - 18 of 18) sorted by relevance

/external/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h441 /// FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW,
445 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, enumerator in enum:llvm::ISD::NodeType
/external/valgrind/main/none/tests/ppc32/
H A Dround.c33 FMSUB, FNMADD, FNMSUB, FSQRT enumerator in enum:__anon28695
899 for (s = (op != FSQRT ? -1 : 1); s < 2; s += 2)
1007 case FSQRT:
1112 case FSQRT:
1181 for (op = FADD; op <= FSQRT; op++) {
/external/valgrind/main/none/tests/ppc64/
H A Dround.c33 FMSUB, FNMADD, FNMSUB, FSQRT enumerator in enum:__anon28738
899 for (s = (op != FSQRT ? -1 : 1); s < 2; s += 2)
1007 case FSQRT:
1112 case FSQRT:
1181 for (op = FADD; op <= FSQRT; op++) {
/external/llvm/lib/Target/PowerPC/
H A DPPCCTRLoops.cpp256 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
295 Opcode = ISD::FSQRT; break;
H A DPPCISelLowering.cpp145 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
150 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
402 setOperationAction(ISD::FSQRT, VT, Expand);
473 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
535 setTargetDAGCombine(ISD::FSQRT);
7008 if (N->getOperand(1).getOpcode() == ISD::FSQRT) {
7017 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
7030 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
7054 case ISD::FSQRT: {
/external/llvm/lib/CodeGen/
H A DBasicTargetTransformInfo.cpp437 case Intrinsic::sqrt: ISD = ISD::FSQRT; break;
/external/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp136 case ISD::FSQRT: return "fsqrt";
H A DLegalizeVectorOps.cpp230 case ISD::FSQRT:
H A DLegalizeFloatTypes.cpp92 case ISD::FSQRT: R = SoftenFloatRes_FSQRT(N); break;
821 case ISD::FSQRT: ExpandFloatRes_FSQRT(N, Lo, Hi); break;
H A DLegalizeVectorTypes.cpp87 case ISD::FSQRT:
544 case ISD::FSQRT:
1511 case ISD::FSQRT:
H A DSelectionDAGBuilder.cpp4909 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
5620 if (visitUnaryFloatCall(I, ISD::FSQRT))
H A DLegalizeDAG.cpp3148 case ISD::FSQRT:
/external/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1109 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
1110 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
/external/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp165 setOperationAction(ISD::FSQRT, MVT::f32, Legal);
166 setOperationAction(ISD::FSQRT, MVT::f64, Legal);
229 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
/external/chromium_org/third_party/mesa/src/src/mesa/x86/
H A Dassyntax.h767 #define FSQRT CHOICE(fsqrt, fsqrt, fsqrt) macro
1488 #define FSQRT fsqrt macro
/external/mesa3d/src/mesa/x86/
H A Dassyntax.h767 #define FSQRT CHOICE(fsqrt, fsqrt, fsqrt) macro
1488 #define FSQRT fsqrt macro
/external/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp823 setOperationAction(ISD::FSQRT, VT, Expand);
917 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
952 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
1131 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1144 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1320 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1327 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
11080 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
/external/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp491 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
509 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
526 setOperationAction(ISD::FSQRT, MVT::v2f32, Expand);

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