/external/valgrind/main/VEX/priv/ |
H A D | host_amd64_defs.h | 175 } Imm; member in union:__anon30778::__anon30779 210 } Imm; member in union:__anon30784::__anon30785
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H A D | host_x86_defs.h | 163 } Imm; member in union:__anon31260::__anon31261 197 } Imm; member in union:__anon31266::__anon31267
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H A D | host_ppc_defs.h | 249 } Imm; member in union:__anon31099::__anon31100 277 ULong Imm; member in union:__anon31104::__anon31105
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/external/llvm/lib/Target/AArch64/AsmParser/ |
H A D | AArch64AsmParser.cpp | 240 struct ImmOp Imm; member in union:__anon25114::AArch64Operand::__anon25115 268 Imm = o.Imm; 323 return Imm.Val; 1086 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) { 1102 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) { 1515 unsigned Imm = local 1517 Inst.addOperand(MCOperand::CreateImm(Imm)); 1524 unsigned Imm = AArch64_AM::getArithExtendImm(ET, getShiftExtendAmount()); local 1525 Inst.addOperand(MCOperand::CreateImm(Imm)); 1532 unsigned Imm = AArch64_AM::getArithExtendImm(ET, getShiftExtendAmount()); local 2168 const MCExpr *Imm; local 3097 uint64_t Imm = (cast<MCConstantExpr>(SubExprVal))->getValue(); local [all...] |
/external/llvm/lib/Target/Mips/AsmParser/ |
H A D | MipsAsmParser.cpp | 375 struct ImmOp Imm; member in union:__anon25200::MipsOperand::__anon25201 701 return Imm.Val; 793 Op->Imm.Val = Val; 868 OS << "Imm<"; 869 Imm.Val->print(OS); 1922 int64_t Imm; local 1923 if (IdVal->EvaluateAsAbsolute(Imm)) 1924 IdVal = MCConstantExpr::Create(Imm, getContext());
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/external/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 3254 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { argument 3257 if (Imm.isNegZero()) 3259 return Imm.isZero();
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 337 bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { argument 339 return Imm.isZero() || Imm.isNegZero();
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/external/llvm/lib/Transforms/Scalar/ |
H A D | LoopStrengthReduce.cpp | 3461 int64_t Imm = ExtractImmediate(G, SE); local 3462 if (G->isZero() || Imm == 0) 3465 F.BaseOffset = (uint64_t)F.BaseOffset + Imm; 3683 int64_t Imm; member in struct:__anon25465::WorkItem 3687 : LUIdx(LI), Imm(I), OrigReg(R) {} 3697 << " , add offset " << Imm; local 3718 int64_t Imm = ExtractImmediate(Reg, SE); local 3723 Pair.first->second.insert(std::make_pair(Imm, *I)); 3773 int64_t Imm = (uint64_t)JImm - M->first; local 3777 if (UniqueItems.insert(std::make_pair(LUIdx, Imm))) 3794 int64_t Imm = WI.Imm; local [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAG.cpp | 1030 APInt Imm = APInt::getLowBitsSet(BitWidth, local 1033 getConstant(Imm, Op.getValueType()));
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H A D | DAGCombiner.cpp | 8797 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); local 8799 Imm ^= APInt::getAllOnesValue(BitWidth); 8800 if (Imm == 0 || Imm.isAllOnesValue()) 8802 unsigned ShAmt = Imm.countTrailingZeros(); 8803 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 8821 if ((Imm & Mask) == Imm) { 8822 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW);
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/external/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 3646 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { argument 3648 if (Imm.bitwiseIsEqual(LegalFPImmediates[i])) 3656 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm, argument 4239 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) { argument 4247 *Imm = 1; 4253 *Imm = 0; 6942 unsigned Imm = 0; local 6943 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0; 6944 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2; 6945 Imm | [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 3784 bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { argument 3787 if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32)) 3791 return AArch64_AM::getFP64Imm(Imm) != -1; 3793 return AArch64_AM::getFP32Imm(Imm) != -1; 4225 unsigned Imm = VEXTOffsets[i] * getExtFactor(VEXTSrc1); local 4227 DAG.getConstant(Imm, MVT::i32)); 4261 static bool isSingletonEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) { argument 4268 Imm = M[0]; 4273 unsigned ExpectedElt = Imm; 4293 unsigned &Imm) { 4292 isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT, unsigned &Imm) argument 4615 unsigned Imm = (OpNum - OP_VEXT1 + 1) * getExtFactor(OpLHS); local 4774 unsigned Imm; local 6297 shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const argument [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 4418 unsigned OpCmode, Imm; local 4435 Imm = SplatBits; 4445 Imm = SplatBits; 4451 Imm = SplatBits >> 8; 4465 Imm = SplatBits; 4471 Imm = SplatBits >> 8; 4477 Imm = SplatBits >> 16; 4483 Imm = SplatBits >> 24; 4494 Imm = SplatBits >> 8; 4502 Imm 4632 isSingletonVEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) argument 4661 isVEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseVEXT, unsigned &Imm) argument 5276 unsigned Imm, WhichResult; local 5456 unsigned Imm; local 9054 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); local 10646 isFPImmLegal(const APFloat &Imm, EVT VT) const argument 10768 shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const argument [all...] |
/external/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 486 unsigned Imm; member in struct:__anon25150::ARMOperand::ShifterImmOp 503 unsigned Imm; member in struct:__anon25150::ARMOperand::RotImmOp 524 struct ImmOp Imm; member in union:__anon25150::ARMOperand::__anon25151 572 Imm = o.Imm; 654 return Imm.Val; 695 if (isa<MCSymbolRefExpr>(Imm.Val)) return true; 696 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) { 709 if (isa<MCSymbolRefExpr>(Imm.Val)) return true; 710 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm 1761 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm); local 1882 unsigned Imm = CE->getValue(); local 1983 int32_t Imm = Memory.OffsetImm->getValue(); local 2296 int Imm = CE->getValue(); local 2307 int Imm = CE->getValue(); local 2327 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm, local 2461 unsigned Imm = 0; local 2564 CreateShifterImm(bool isASR, unsigned Imm, SMLoc S, SMLoc E) argument 2574 CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) argument 2968 int64_t Imm = 0; local [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 1184 static bool isIntS16Immediate(SDNode *N, short &Imm) { argument 1188 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue(); 1190 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue(); 1192 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue(); 1194 static bool isIntS16Immediate(SDValue Op, short &Imm) { argument 1195 return isIntS16Immediate(Op.getNode(), Imm); 1344 short Imm; local 1345 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) { 1346 Disp = DAG.getTargetConstant(Imm, C 8900 shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const argument [all...] |