| cd81d94322a39503e4a3e87b6ee03d4fcb3465fb |
21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
PCMCCodeEmitter.cpp
PCMCExpr.cpp
PCMCExpr.h
|
| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
PCAsmBackend.cpp
PCELFObjectWriter.cpp
PCMCAsmInfo.cpp
PCMCAsmInfo.h
PCMCCodeEmitter.cpp
PCMCExpr.cpp
PCMCExpr.h
PCMCTargetDesc.cpp
PCMachObjectWriter.cpp
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
MakeLists.txt
PCAsmBackend.cpp
PCELFObjectWriter.cpp
PCMCAsmInfo.cpp
PCMCAsmInfo.h
PCMCCodeEmitter.cpp
PCMCExpr.cpp
PCMCExpr.h
PCMCTargetDesc.cpp
PCMCTargetDesc.h
PCPredicates.cpp
PCPredicates.h
|
| 354362524a72b3fa43a6c09380b7ae3b2380cbba |
19-Nov-2013 |
Juergen Ributzka <juergen@apple.com> |
[weak vtables] Remove a bunch of weak vtables
This patch removes most of the trivial cases of weak vtables by pinning them to
a single object file. The memory leaks in this version have been fixed. Thanks
Alexey for pointing them out.
Differential Revision: http://llvm-reviews.chandlerc.com/D2068
Reviewed by Andy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195064 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCTargetDesc.cpp
|
| b21ab43cfc3fa0dacf5c95f04e58b6d804b59a16 |
18-Nov-2013 |
Alexey Samsonov <samsonov@google.com> |
Revert r194865 and r194874.
This change is incorrect. If you delete virtual destructor of both a base class
and a subclass, then the following code:
Base *foo = new Child();
delete foo;
will not cause the destructor for members of Child class. As a result, I observe
plently of memory leaks. Notable examples I investigated are:
ObjectBuffer and ObjectBufferStream, AttributeImpl and StringSAttributeImpl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194997 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCTargetDesc.cpp
|
| 5a364c5561ec04e33a6f5d52c14f1bac6f247ea0 |
15-Nov-2013 |
Juergen Ributzka <juergen@apple.com> |
[weak vtables] Remove a bunch of weak vtables
This patch removes most of the trivial cases of weak vtables by pinning them to
a single object file.
Differential Revision: http://llvm-reviews.chandlerc.com/D2068
Reviewed by Andy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194865 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCTargetDesc.cpp
|
| 06957f43f6051901590b318c10b1a0a5c7f898d4 |
16-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add a MCAsmInfoELF class and factor some code into it.
We had a MCAsmInfoCOFF, but no common class for all the ELF MCAsmInfos before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192760 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCAsmInfo.cpp
PCMCAsmInfo.h
|
| 320296a4cfe414ce59f406b8a5ce15272f563103 |
08-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add a MCTargetStreamer interface.
This patch fixes an old FIXME by creating a MCTargetStreamer interface
and moving the target specific functions for ARM, Mips and PPC to it.
The ARM streamer is still declared in a common place because it is
used from lib/CodeGen/ARMException.cpp, but the Mips and PPC are
completely hidden in the corresponding Target directories.
I will send an email to llvmdev with instructions on how to use this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192181 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCTargetDesc.cpp
|
| 9637da60835a60f8ccd8289d04c60b2dcd4b9b5a |
26-Sep-2013 |
David Majnemer <david.majnemer@gmail.com> |
PPC: Allow partial fills in writeNopData()
When asked to pad an irregular number of bytes, we should fill with
zeros. This is consistent with the behavior specified in the AIX
Assembler Language Reference as well as other LLVM and binutils
assemblers.
N.B. There is a small deviation from binutils' PPC assembler:
when handling pads which are greater than 4 bytes but not mod 4,
binutils will not emit any NOP sequences at all and only use zeros.
This may or may not be a bug but there is no excellent rationale as to
why that behavior is important to emulate. If that behavior is needed,
we can change writeNopData() to behave in the same way.
This fixes PR17352.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191426 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
|
| 3f22cc1df64a6dd6a3ecc5e7e261f15af083f806 |
25-Sep-2013 |
David Majnemer <david.majnemer@gmail.com> |
MC: Add support for treating $ as a reference to the PC
The binutils assembler supports a mode called DOLLAR_DOT which treats
the dollar sign token as a reference to the current program counter if
the dollar sign doesn't precede a constant or identifier.
This commit adds a new MCAsmInfo flag stating whether or not a given
target supports this interpretation of the dollar sign token; by
default, this flag is not enabled.
Further, enable this flag for PPC. The system assembler for AIX and
binutils both support using the dollar sign in this manner.
This fixes PR17353.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191368 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCAsmInfo.cpp
|
| 8ba3f9c9008223136207295b48b53c8aefffa178 |
25-Sep-2013 |
David Majnemer <david.majnemer@gmail.com> |
MC: Remove vestigial PCSymbol field from AsmInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191362 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCAsmInfo.cpp
|
| 5c616f91a5136295bf83850bc3610bd28756e58e |
16-Sep-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
[PowerPC] Fix PR17155 - Ignore COPY_TO_REGCLASS during emit.
Fast-isel generates a COPY_TO_REGCLASS for widening f32 to f64, which
is a nop on PPC64. This is needed to keep the register class system
happy, but on the fast-isel path it is not removed before emit as it
is for DAG select. Ignore this op when emitting instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190795 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCCodeEmitter.cpp
|
| c3cee57f7d20f69a84fd88464ed8cf050e63c7ad |
09-Sep-2013 |
Bill Wendling <isanbard@gmail.com> |
Generate compact unwind encoding from CFI directives.
We used to generate the compact unwind encoding from the machine
instructions. However, this had the problem that if the user used `-save-temps'
or compiled their hand-written `.s' file (with CFI directives), we wouldn't
generate the compact unwind encoding.
Move the algorithm that generates the compact unwind encoding into the
MCAsmBackend. This way we can generate the encoding whether the code is from a
`.ll' or `.s' file.
<rdar://problem/13623355>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190290 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
PCMCTargetDesc.h
|
| 5510728d28bb1ee04abc32da3d21b7df12948053 |
01-Sep-2013 |
Charles Davis <cdavis5x@gmail.com> |
Move everything depending on Object/MachOFormat.h over to Support/MachO.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189728 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
PCMachObjectWriter.cpp
|
| ead2d5a4be3012699252e015ce774733590bf9b0 |
28-Aug-2013 |
Alexey Samsonov <samsonov@google.com> |
Fix use of uninitialized value added in r189400 (found by MemorySanitizer)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189456 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCExpr.cpp
|
| 66b7139b1be1ddce410d97499d5831231c6be267 |
27-Aug-2013 |
Joerg Sonnenberger <joerg@bec.de> |
Given target assembler parsers a chance to handle variant expressions
first. Use this to turn the PPC modifiers into PPC specific expressions,
allowing them to work on constants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189400 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCExpr.cpp
|
| f69a29b23a116a3520f185054290c445abf9aa62 |
27-Aug-2013 |
Charles Davis <cdavis5x@gmail.com> |
Revert "Fix the build broken by r189315." and "Move everything depending on Object/MachOFormat.h over to Support/MachO.h."
This reverts commits r189319 and r189315. r189315 broke some tests on what I
believe are big-endian platforms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189321 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
PCMachObjectWriter.cpp
|
| 9c3dd1b0d1e96ef408b68da3b06c6ebd6c943601 |
27-Aug-2013 |
Charles Davis <cdavis5x@gmail.com> |
Move everything depending on Object/MachOFormat.h over to Support/MachO.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189315 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
PCMachObjectWriter.cpp
|
| d76adee1b214fe1f5a26b8ffaec3e461beda6c88 |
08-Aug-2013 |
David Fang <fang@csl.cornell.edu> |
cast fix to appease buildbot
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188014 91177308-0d34-0410-b5e6-96231b3b80d8
PCMachObjectWriter.cpp
|
| d4f9d05fde4b2cfd202a5852ec1ec3e960ef53ed |
08-Aug-2013 |
David Fang <fang@csl.cornell.edu> |
initial draft of PPCMachObjectWriter.cpp
this records relocation entries in the mach-o object file
for PIC code generation.
tested on powerpc-darwin8, validated against darwin otool -rvV
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188004 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
PCAsmBackend.cpp
PCMCTargetDesc.h
PCMachObjectWriter.cpp
|
| f38cc38fa647d4e72c053c39bbe0cdec1342535f |
26-Jul-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
[PowerPC] Support powerpc64le as a syntax-checking target.
This patch provides basic support for powerpc64le as an LLVM target.
However, use of this target will not actually generate little-endian
code. Instead, use of the target will cause the correct little-endian
built-in defines to be generated, so that code that tests for
__LITTLE_ENDIAN__, for example, will be correctly parsed for
syntax-only testing. Code generation will otherwise be the same as
powerpc64 (big-endian), for now.
The patch leaves open the possibility of creating a little-endian
PowerPC64 back end, but there is no immediate intent to create such a
thing.
The LLVM portions of this patch simply add ppc64le coverage everywhere
that ppc64 coverage currently exists. There is nothing of any import
worth testing until such time as little-endian code generation is
implemented. In the corresponding Clang patch, there is a new test
case variant to ensure that correct built-in defines for little-endian
code are generated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187179 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
PCMCTargetDesc.cpp
PCMCTargetDesc.h
|
| 7a34599db017a5486cf7cd11eb124984acec8286 |
09-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Revert r185476 and fix up TLS variant kinds
In the commit message to r185476 I wrote:
>The PowerPC-specific modifiers VK_PPC_TLSGD and VK_PPC_TLSLD
>correspond exactly to the generic modifiers VK_TLSGD and VK_TLSLD.
>This causes some confusion with the asm parser, since VK_PPC_TLSGD
>is output as @tlsgd, which is then read back in as VK_TLSGD.
>
>To avoid this confusion, this patch removes the PowerPC-specific
>modifiers and uses the generic modifiers throughout. (The only
>drawback is that the generic modifiers are printed in upper case
>while the usual convention on PowerPC is to use lower-case modifiers.
>But this is just a cosmetic issue.)
This was unfortunately incorrect, there is is fact another,
serious drawback to using the default VK_TLSLD/VK_TLSGD
variant kinds: using these causes ELFObjectWriter::RelocNeedsGOT
to return true, which in turn causes the ELFObjectWriter to emit
an undefined reference to _GLOBAL_OFFSET_TABLE_.
This is a problem on powerpc64, because it uses the TOC instead
of the GOT, and the linker does not provide _GLOBAL_OFFSET_TABLE_,
so the symbol remains undefined. This means shared libraries
using TLS built with the integrated assembler are currently
broken.
While the whole RelocNeedsGOT / _GLOBAL_OFFSET_TABLE_ situation
probably ought to be properly fixed at some point, for now I'm
simply reverting the r185476 commit. Now this in turn exposes
the breakage of handling @tlsgd/@tlsld in the asm parser that
this check-in was originally intended to fix.
To avoid this regression, I'm also adding a different fix for
this problem: while common code now parses @tlsgd as VK_TLSGD,
a special hack in the asm parser translates this code to the
platform-specific VK_PPC_TLSGD that the back-end now expects.
While this is not really pretty, it's self-contained and
shouldn't hurt anything else for now. One the underlying
problem is fixed, this hack can be reverted again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185945 91177308-0d34-0410-b5e6-96231b3b80d8
PCELFObjectWriter.cpp
|
| a68f58ab2bec6a024afae498e4082ddd8b01f178 |
08-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Always use "assembler dialect" 1
A setting in MCAsmInfo defines the "assembler dialect" to use. This is used
by common code to choose between alternatives in a multi-alternative GNU
inline asm statement like the following:
__asm__ ("{sfe|subfe} %0,%1,%2" : "=r" (out) : "r" (in1), "r" (in2));
The meaning of these dialects is platform specific, and GCC defines those
for PowerPC to use dialect 0 for old-style (POWER) mnemonics and 1 for
new-style (PowerPC) mnemonics, like in the example above.
To be compatible with inline asm used with GCC, LLVM ought to do the same.
Specifically, this means we should always use assembler dialect 1 since
old-style mnemonics really aren't supported on any current platform.
However, the current LLVM back-end uses:
AssemblerDialect = 1; // New-Style mnemonics.
in PPCMCAsmInfoDarwin, and
AssemblerDialect = 0; // Old-Style mnemonics.
in PPCLinuxMCAsmInfo.
The Linux setting really isn't correct, we should be using new-style
mnemonics everywhere. This is changed by this commit.
Unfortunately, the setting of this variable is overloaded in the back-end
to decide whether or not we are on a Darwin target. This is done in
PPCInstPrinter (the "SyntaxVariant" is initialized from the MCAsmInfo
AssemblerDialect setting), and also in PPCMCExpr. Setting AssemblerDialect
to 1 for both Darwin and Linux no longer allows us to make this distinction.
Instead, this patch uses the MCSubtargetInfo passed to createPPCMCInstPrinter
to distinguish Darwin targets, and ignores the SyntaxVariant parameter.
As to PPCMCExpr, this patch adds an explicit isDarwin argument that needs
to be passed in by the caller when creating a target MCExpr. (To do so
this patch implicitly also reverts commit 184441.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185858 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCAsmInfo.cpp
PCMCExpr.cpp
PCMCExpr.h
PCMCTargetDesc.cpp
|
| 457571ed6977f78ca8d30b993fa7e86e2d7ad8d5 |
05-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add some special @got@tprel fixup cases
When a target@got@tprel or target@got@tprel@l symbol variant is used in
a fixup_ppc_half16 (*not* fixup_ppc_half16ds) context, we currently fail,
since the corresponding R_PPC64_GOT_TPREL16 / R_PPC64_GOT_TPREL16_LO
relocation types do not exist.
However, since such symbol variants resolve to GOT offsets which are
always 4-aligned, we can simply instead use the _DS variants of the
relocation types, which *do* exist.
The same applies for the @got@dtprel variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185700 91177308-0d34-0410-b5e6-96231b3b80d8
PCELFObjectWriter.cpp
|
| 23a72c8f7e46618ff8dbdbba4e8c1a2c4e44e3df |
05-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support @tls in the asm parser
This adds support for the last missing construct to parse TLS-related
assembler code:
add 3, 4, symbol@tls
The ADD8TLS currently hard-codes the @tls into the assembler string.
This cannot be handled by the asm parser, since @tls is parsed as
a symbol variant. This patch changes ADD8TLS to have the @tls suffix
printed as symbol variant on output too, which allows us to remove
the isCodeGenOnly marker from ADD8TLS. This in turn means that we
can add a AsmOperand to accept @tls marked symbols on input.
As a side effect, this means that the fixup_ppc_tlsreg fixup type
is no longer necessary and can be merged into fixup_ppc_nofixup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185692 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
PCELFObjectWriter.cpp
PCFixupKinds.h
PCMCCodeEmitter.cpp
|
| 972befb3f281f0f9ce08d7cf27b4e879327676b0 |
04-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Implement writeNopData
This implements a proper PPCAsmBackend::writeNopData routine
that actually writes PowerPC nop instructions.
This fixes the last remaining difference in object file output
(text section) between the integrated assembler and GNU as
that I've seen anywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185662 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
|
| 33efedc0481c4b0d9866ff526eb1161372b5919f |
03-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Use mtocrf when available
Just as with mfocrf, it is also preferable to use mtocrf instead of
mtcrf when only a single CR register is to be written.
Current code however always emits mtcrf. This probably does not matter
when using an external assembler, since the GNU assembler will in fact
automatically replace mtcrf with mtocrf when possible. It does create
inefficient code with the integrated assembler, however.
To fix this, this patch adds MTOCRF/MTOCRF8 instruction patterns and
uses those instead of MTCRF/MTCRF8 everything. Just as done in the
MFOCRF patch committed as 185556, these patterns will be converted
back to MTCRF if MTOCRF is not available on the machine.
As a side effect, this allows to modify the MTCRF pattern to accept
the full range of mask operands for the benefit of the asm parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185561 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCCodeEmitter.cpp
|
| 965b20e39c7fd73846e9b6ed55ba90e032ae3b1b |
03-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Always use mfocrf if available
When accessing just a single CR register, it is always preferable to
use mfocrf instead of mfcr, if the former is available on the CPU.
Current code makes that distinction in many, but not all places
where a single CR register value is retrieved. One missing
location is PPCRegisterInfo::lowerCRSpilling.
To fix this and make this simpler in the future, this patch changes
the bulk of the back-end to always assume mfocrf is available and
simply generate it when needed.
On machines that actually do not support mfocrf, the instruction
is replaced by mfcr at the very end, in EmitInstruction.
This has the additional benefit that we no longer need the
MFCRpseud hack, since before EmitInstruction we always have
a MFOCRF instruction pattern, which already models data flow
as required.
The patch also adds the MFOCRF8 version of the instruction,
which was missing so far.
Except for the PPCRegisterInfo::lowerCRSpilling case, no change
in generated code intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185556 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCCodeEmitter.cpp
|
| a17a7e1868076a4430cfa16694bcb42884130928 |
02-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Rework TLS call operand processing
As part of the global-dynamic and local-dynamic TLS sequences, we need
to use a special form of the call instruction:
bl __tls_get_addr(sym@tlsld)
bl __tls_get_addr(sym@tlsgd)
which generates two fixups. The current implementation of this causes
problems with recognizing this form in the asm parser. To fix this,
this patch reworks operand processing for this special form by using
a single operand to hold both __tls_get_addr and sym@tlsld and defining
a print method to output the above form, and an encoding method to
generate the two fixups.
As a side simplification, the patch replaces the two instruction
patterns BL8_NOP_TLSGD and BL8_NOP_TLSLD by a single BL8_NOP_TLS,
since the patterns already operate in an identical fashion (whether
we have a local-dynamic or global-dynamic symbol is already encoded
in the symbol modifier).
No change in code generation intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185477 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCCodeEmitter.cpp
|
| 58fc1f52ce070003acbdfedc85d52ba999a2bd11 |
02-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Remove VK_PPC_TLSGD and VK_PPC_TLSLD
The PowerPC-specific modifiers VK_PPC_TLSGD and VK_PPC_TLSLD
correspond exactly to the generic modifiers VK_TLSGD and VK_TLSLD.
This causes some confusion with the asm parser, since VK_PPC_TLSGD
is output as @tlsgd, which is then read back in as VK_TLSGD.
To avoid this confusion, this patch removes the PowerPC-specific
modifiers and uses the generic modifiers throughout. (The only
drawback is that the generic modifiers are printed in upper case
while the usual convention on PowerPC is to use lower-case modifiers.
But this is just a cosmetic issue.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185476 91177308-0d34-0410-b5e6-96231b3b80d8
PCELFObjectWriter.cpp
|
| 228e0afcfd0d5f167a95c6ddbec2c6a4a90b6d2b |
02-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add support for TLS data relocations
This adds support for TLS data relocations and modifiers:
.quad target@dtpmod
.quad target@tprel
.quad target@dtprel
Currently exploited by the asm parser only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185394 91177308-0d34-0410-b5e6-96231b3b80d8
PCELFObjectWriter.cpp
|
| 222e781d92541017c3a9c5dd40cb52e334cdb86f |
01-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Fix @got references to local symbols
A @got reference must always result in a relocation, so that
the linker has a chance to set up the GOT entry, even if the
symbol happens to be local.
Add a PPCELFObjectWriter::ExplicitRelSym routine that enforces
a relocation to be emitted for GOT references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185353 91177308-0d34-0410-b5e6-96231b3b80d8
PCELFObjectWriter.cpp
|
| 0b8594268feb1c804370541c7853e658caee0ae5 |
26-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support symbolic u16imm operands
Currently, all instructions taking s16imm operands support symbolic
operands. However, for u16imm operands, we only support actual
immediate integers. This causes the assembler to reject code like
ori %r5, %r5, symbol@l
This patch changes the u16imm operand definition to likewise
accept symbolic operands. In fact, s16imm and u16imm can
share the same encoding routine, now renamed to getImm16Encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184944 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCCodeEmitter.cpp
|
| 5de735a962a255676cf3a9bc255579d465670633 |
25-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support @got modifier
Add VK_... values and relocation types necessary to support
the @got family of modifiers. Used by the asm parser only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184860 91177308-0d34-0410-b5e6-96231b3b80d8
PCELFObjectWriter.cpp
|
| 2e8bd8950345b0857130dd0f4068222a79c103f2 |
24-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add predicted forms of branches
This adds support for the predicted forms of branches (+/-).
There are three cases to consider:
- Branches using a PPC::Predicate code
For these, I've added new PPC::Predicate codes corresponding
to the BO values for predicted branch forms, and updated insn
printing to print them correctly. I've also added new aliases
for the asm parser matching the new forms.
- bt/bf
I've added new aliases matching to gBC etc.
- bd(n)z variants
I've added new instruction patterns for the predicted forms.
In all cases, the new patterns are used for the asm parser only.
(The new infrastructure ought to be sufficient to allow use by
the compiler too at some point.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184754 91177308-0d34-0410-b5e6-96231b3b80d8
PCPredicates.cpp
PCPredicates.h
|
| 9679c47a07386cbf3547a0927609c7ee080b2aab |
24-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support absolute branches
There is currently only limited support for the "absolute" variants
of branch instructions. This patch adds support for the absolute
variants of all branches that are currently otherwise supported.
This requires adding new fixup types so that the correct variant
of relocation type can be selected by the object writer.
While the compiler will continue to usually choose the relative
branch variants, this will allow the asm parser to fully support
the absolute branches, with either immediate (numerical) or
symbolic target addresses.
No change in code generation intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184721 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
PCELFObjectWriter.cpp
PCFixupKinds.h
PCMCCodeEmitter.cpp
|
| 84569698f01bcb49afe5b6140bf0d61cf4f3cf5a |
21-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support R_PPC_REL16 family of relocations
The GNU assembler supports (as extension to the ABI) use of PC-relative
relocations in half16 fields, which allows writing code like:
li 1, base-.
This patch adds support for those relocation types in the assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184552 91177308-0d34-0410-b5e6-96231b3b80d8
PCELFObjectWriter.cpp
|
| cab0a1933875935c717136d251e2af9749533ba8 |
21-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support various tls-related modifiers
The current code base only supports the minimum set of tls-related
relocations and @modifiers that are necessary to support compiler-
generated code. This patch extends this to the full set defined
in the ABI (and supported by the GNU assembler) for the benefit
of the assembler parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184551 91177308-0d34-0410-b5e6-96231b3b80d8
PCELFObjectWriter.cpp
|
| f7c1ee79fe90353fcd3f545f9d45a01a837bbf4b |
21-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support @higher et.al. modifiers
This adds support for the @higher, @highera, @highest, and @highesta
modifers, including some missing relocation types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184550 91177308-0d34-0410-b5e6-96231b3b80d8
PCELFObjectWriter.cpp
PCMCExpr.cpp
PCMCExpr.h
|
| f8f87dcfceadd1b842d130303a7091ad7d7d67d0 |
21-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support @toc@h modifier
This adds the relocation type and other necessary infrastructure
to use the @toc@h modifier in the assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184549 91177308-0d34-0410-b5e6-96231b3b80d8
PCELFObjectWriter.cpp
|
| d2849572463da994c685b3bd7a60d5a7566c01e3 |
21-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support @h modifier
This adds necessary infrastructure to support the @h modifier.
Note that all required relocation types were already present
(and unused).
This patch provides support for using @h in the assembler;
it would also be possible to now use this feature in code
generated by the compiler, but this is not done yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184548 91177308-0d34-0410-b5e6-96231b3b80d8
PCELFObjectWriter.cpp
PCMCExpr.cpp
PCMCExpr.h
|
| 92cfa61c50d01307d658753f8d47f4e8555a6fa9 |
21-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Rename some more VK_PPC_ enums
This renames more VK_PPC_ enums, to make them more closely reflect
the @modifier string they represent. This also prepares for adding
a bunch of new VK_PPC_ enums in upcoming patches.
For consistency, some MO_ flags related to VK_PPC_ enums are
likewise renamed.
No change in behaviour.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184547 91177308-0d34-0410-b5e6-96231b3b80d8
PCELFObjectWriter.cpp
PCMCExpr.cpp
PCMCExpr.h
|
| 846565924a6f2932efc75c249b29c3619e587bbb |
21-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Clean up VK_PPC_TOC... names
This is another minor cleanup; to bring enum names in line
with the corresponding @modifier names, this renames:
VK_PPC_TOC -> VK_PPC_TOCBASE
VK_PPC_TOC_ENTRY -> VK_PPC_TOC16
No code change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184491 91177308-0d34-0410-b5e6-96231b3b80d8
PCELFObjectWriter.cpp
|
| 769accfb4d71caff9152309eaa5e704e065b5846 |
21-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Minor cleanup in PPCELFObjectWriter::getRelocTypeInner
This just re-sorts the big switch statement in
PPCELFObjectWriter::getRelocTypeInner to follow
the (numerical) order of the reloc types, and
fixes a couple of whitespace issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184485 91177308-0d34-0410-b5e6-96231b3b80d8
PCELFObjectWriter.cpp
|
| 027e94479c9e69eb3c3c5536fa9990d0b96e9510 |
20-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Optimize @ha/@l constructs
This patch adds support for having the assembler optimize fixups
to constructs like "symbol@ha" or "symbol@l" if "symbol" can be
resolved at assembler time.
This optimization is already present in the PPCMCExpr.cpp code
for handling PPC_HA16/PPC_LO16 target expressions. However,
those target expression were used only on Darwin targets.
This patch changes target expression code so that they are
usable also with the GNU assembler (using the @ha / @l syntax
instead of the ha16() / lo16() syntax), and changes the
MCInst lowering code to generate those target expressions
where appropriate.
It also changes the asm parser to generate HA16/LO16 target
expressions when parsing assembler source that uses the
@ha / @l modifiers. The effect is that now the above-
mentioned optimization automatically becomes available
for those situations too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184436 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCExpr.cpp
PCMCExpr.h
|
| 99cb622041a0839c7dfcf0263c5102a305a0fdb5 |
18-Jun-2013 |
Bill Wendling <isanbard@gmail.com> |
Use pointers to the MCAsmInfo and MCRegInfo.
Someone may want to do something crazy, like replace these objects if they
change or something.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184175 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCCodeEmitter.cpp
|
| 7e17024400941889b6fe1b178e5374f75c34d9ab |
12-Jun-2013 |
David Blaikie <dblaikie@gmail.com> |
Revert r183854 (PPC: Fix switch warnings from r183841)
Now that the PRED_BAD has been removed, this is failing the Clang
-Werror build due to -Wcovered-switch-default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183863 91177308-0d34-0410-b5e6-96231b3b80d8
PCPredicates.cpp
|
| 628953385396cfa4f59b6ccb56ee3b10d6b5f865 |
12-Jun-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
[PowerPC] Remove PRED_BAD from PPC::Predicate enumeration.
I'm taking David Blaikie's suggestion to use an
Optional<PPC::Predicate> return value instead. That's the right
solution for this problem. Thanks for pointing out that possibility!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183858 91177308-0d34-0410-b5e6-96231b3b80d8
PCPredicates.h
|
| dab366bf25ef00a37e5d9306c6dcbbb7c1d3e19a |
12-Jun-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
[PowerPC] Fix switch warnings from r183841.
Introducing PRED_BAD caused some unexpected warnings that are now
suppressed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183854 91177308-0d34-0410-b5e6-96231b3b80d8
PCPredicates.cpp
|
| f69ead465110efd53cc838191080bc0f2d71c345 |
12-Jun-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Add artificial PRED_BAD to PPC::Predicate enumeration.
Allows returning a PPC::Predicate from a function with a no-predicate
value possible. Preparatory patch for fast-isel on PPC64 ELF. No
behavioral change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183841 91177308-0d34-0410-b5e6-96231b3b80d8
PCPredicates.h
|
| c1f4a4b2640dfc871bacacef53a95f1c96a9fe48 |
12-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[MC/DWARF] Support .debug_frame / .debug_line code alignment factors
I've been comparing the object file output of LLVM's integrated
assembler against the external assembler on PowerPC, and one
area where differences still remain are in DWARF sections.
In particular, the GNU assembler generates .debug_frame and
.debug_line sections using a code alignment factor of 4, since
all PowerPC instructions have size 4 and must be aligned to a
multiple of 4. However, current MC code hard-codes a code
alignment factor of 1.
This patch changes this by adding a "minimum instruction alignment"
data element to MCAsmInfo and using this as code alignment factor.
This requires passing a MCContext into MCDwarfLineAddr::Encode
and MCDwarfLineAddr::EncodeAdvanceLoc. Note that one caller,
MCDwarfLineAddr::Write, didn't actually have that information
available. However, it turns out that this routine is in fact
never used in the whole code base, so the patch simply removes
it. If it turns out to be needed again at a later time, it
could be re-added with an updated interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183834 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCAsmInfo.cpp
|
| edaa58ee66699b99841ee5dfdd485aedbae3bf90 |
24-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Clean up generation of ha16() / lo16() markers
When targeting the Darwin assembler, we need to generate markers ha16() and
lo16() to designate the high and low parts of a (symbolic) immediate. This
is necessary not just for plain symbols, but also for certain symbolic
expression, typically along the lines of ha16(A - B). The latter doesn't
work when simply using VariantKind flags on the symbol reference.
This is why the current back-end uses hacks (explicitly called out as such
via multiple FIXMEs) in the symbolLo/symbolHi print methods.
This patch uses target-defined MCExpr codes to represent the Darwin
ha16/lo16 constructs, following along the lines of the equivalent solution
used by the ARM back end to handle their :upper16: / :lower16: markers.
This allows us to get rid of special handling both in the symbolLo/symbolHi
print method and in the common code MCExpr::print routine. Instead, the
ha16 / lo16 markers are printed simply in a custom print routine for the
target MCExpr types. (As a result, the symbolLo/symbolHi print methods
can now replaced by a single printS16ImmOperand routine that also handles
symbolic operands.)
The patch also provides a EvaluateAsRelocatableImpl routine to handle
ha16/lo16 constructs. This is not actually used at the moment by any
in-tree code, but is provided as it makes merging into David Fang's
out-of-tree Mach-O object writer simpler.
Since there is no longer any need to treat VK_PPC_GAS_HA16 and
VK_PPC_DARWIN_HA16 differently, they are merged into a single
VK_PPC_ADDR16_HA (and likewise for the _LO16 types).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182616 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
PCELFObjectWriter.cpp
PCMCExpr.cpp
PCMCExpr.h
|
| 4456a8ec76bba1148f64bb2707e18b980eda291e |
17-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Fix hi/lo encoding in old-style code emitter
This patch implements the equivalent change to r182091/r182092
in the old-style code emitter. Instead of having two separate
16-bit immediate encoding routines depending on the instruction,
this patch introduces a single encoder that checks the machine
operand flags to decide whether the low or high half of a
symbol address is required.
Since now both encoders make no further distinction between
"symbolLo" and "symbolHi", the .td operand can now use a
single getS16ImmEncoding method.
Tested by running the old-style JIT tests on 32-bit Linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182097 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCCodeEmitter.cpp
|
| e152eac63efa836cbb109d79e4307516fa16f1a6 |
17-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Merge/rename PPC fixup types
Now that fixup_ppc_ha16 and fixup_ppc_lo16 are being treated exactly
the same everywhere, it no longer makes sense to have two fixup types.
This patch merges them both into a single type fixup_ppc_half16,
and renames fixup_ppc_lo16_ds to fixup_ppc_half16ds for consistency.
(The half16 and half16ds names are taken from the description of
relocation types in the PowerPC ABI.)
No change in code generation expected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182092 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
PCELFObjectWriter.cpp
PCFixupKinds.h
PCMCCodeEmitter.cpp
|
| c299ad32c8e59ceea05ede15e1c59ac787d17feb |
17-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Fix processing of ha16/lo16 fixups
The current PowerPC MC back end distinguishes between fixup_ppc_ha16
and fixup_ppc_lo16, which are determined by the instruction the fixup
applies to, and uses this distinction to decide whether a fixup ought
to resolve to the high or the low part of a symbol address.
This isn't quite correct, however. It is valid -if unusual- assembler
to use, e.g.
li 1, symbol@ha
or
lis 1, symbol@l
Whether the high or the low part of the address is used depends solely
on the @ suffix, not on the instruction.
In addition, both
li 1, symbol
and
lis 1, symbol
are valid, assuming the symbol address fits into 16 bits; again, both
will then refer to the actual symbol value (so li will load the value
itself, while lis will load the value shifted by 16).
To fix this, two places need to be adapted. If the fixup cannot be
resolved at assembler time, a relocation needs to be emitted via
PPCELFObjectWriter::getRelocType. This routine already looks at
the VK_ type to determine the relocation. The only problem is that
will reject any _LO modifier in a ha16 fixup and vice versa. This
is simply incorrect; any of those modifiers ought to be accepted
for either fixup type.
If the fixup *can* be resolved at assembler time, adjustFixupValue
currently selects the high bits of the symbol value if the fixup
type is ha16. Again, this is incorrect; see the above example
lis 1, symbol
Now, in theory we'd have to respect a VK_ modifier here. However,
in fact common code never even attempts to resolve symbol references
using any nontrivial VK_ modifier at assembler time; it will always
fall back to emitting a reloc and letting the linker handle it.
If this ever changes, presumably there'd have to be a target callback
to resolve VK_ modifiers. We'd then have to handle @ha etc. there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182091 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
PCELFObjectWriter.cpp
|
| 347a5079e18278803bc05b197d325b8580e95610 |
16-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Use true offset value in "memrix" machine operands
This is the second part of the change to always return "true"
offset values from getPreIndexedAddressParts, tackling the
case of "memrix" type operands.
This is about instructions like LD/STD that only have a 14-bit
field to encode immediate offsets, which are implicitly extended
by two zero bits by the machine, so that in effect we can access
16-bit offsets as long as they are a multiple of 4.
The PowerPC back end currently handles such instructions by
carrying the 14-bit value (as it will get encoded into the
actual machine instructions) in the machine operand fields
for such instructions. This means that those values are
in fact not the true offset, but rather the offset divided
by 4 (and then truncated to an unsigned 14-bit value).
Like in the case fixed in r182012, this makes common code
operations on such offset values not work as expected.
Furthermore, there doesn't really appear to be any strong
reason why we should encode machine operands this way.
This patch therefore changes the encoding of "memrix" type
machine operands to simply contain the "true" offset value
as a signed immediate value, while enforcing the rules that
it must fit in a 16-bit signed value and must also be a
multiple of 4.
This change must be made simultaneously in all places that
access machine operands of this type. However, just about
all those changes make the code simpler; in many cases we
can now just share the same code for memri and memrix
operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182032 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCCodeEmitter.cpp
|
| 4ef61f2ad4ff509ee05c7051d359009511f81226 |
15-May-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Cleanup relocation sorting for ELF.
We want the order to be deterministic on all platforms. NAKAMURA Takumi
fixed that in r181864. This patch is just two small cleanups:
* Move the function to the cpp file. It is only passed to array_pod_sort.
* Remove the ppc implementation which is now redundant
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181910 91177308-0d34-0410-b5e6-96231b3b80d8
PCELFObjectWriter.cpp
|
| 9122396a4dea52cf917062782fc2f39c7dc698bb |
15-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Remove need for adjustFixupOffst hack
Now that applyFixup understands differently-sized fixups, we can define
fixup_ppc_lo16/fixup_ppc_lo16_ds/fixup_ppc_ha16 to properly be 2-byte
fixups, applied at an offset of 2 relative to the start of the
instruction text.
This has the benefit that if we actually need to generate a real
relocation record, its address will come out correctly automatically,
without having to fiddle with the offset in adjustFixupOffset.
Tested on both 64-bit and 32-bit PowerPC, using external and
integrated assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181894 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
PCELFObjectWriter.cpp
PCMCCodeEmitter.cpp
|
| b1cf8de85af10ff3d4ded6431be1cebd6133fd54 |
15-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Correctly handle fixups of other than 4 byte size
The PPCAsmBackend::applyFixup routine handles the case where a
fixup can be resolved within the same object file. However,
this routine is currently hard-coded to assume the size of
any fixup is always exactly 4 bytes.
This is sort-of correct for fixups on instruction text; even
though it only works because several of what really would be
2-byte fixups are presented as 4-byte fixups instead (requiring
another hack in PPCELFObjectWriter::adjustFixupOffset to clean
it up).
However, this assumption breaks down completely for fixups
on data, which legitimately can be of any size (1, 2, 4, or 8).
This patch makes applyFixup aware of fixups of varying sizes,
introducing a new helper routine getFixupKindNumBytes (along
the lines of what the ARM back end does). Note that in order
to handle fixups of size 8, we also need to fix the return type
of adjustFixupValue to uint64_t to avoid truncation.
Tested on both 64-bit and 32-bit PowerPC, using external and
integrated assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181891 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
|
| 4a971705bc6030dc2e4338b3cd5cffa2e0f88b7b |
13-May-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove the MachineMove class.
It was just a less powerful and more confusing version of
MCCFIInstruction. A side effect is that, since MCCFIInstruction uses
dwarf register numbers, calls to getDwarfRegNum are pushed out, which
should allow further simplifications.
I left the MachineModuleInfo::addFrameMove interface unchanged since
this patch was already fairly big.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181680 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCTargetDesc.cpp
|
| 6e53180db120b30f600ac31611a9dd47ef7f4921 |
10-May-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove unused argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181618 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCTargetDesc.cpp
|
| a3967b6844f4be588c724ada3692e734bba65cf1 |
08-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Fix regression in generating @ha/@l relocs
The patch I committed as revision 167864 introduced a regression that
causes LLVM to no longer generate appropriate relocs for @ha/@l symbol
references (but fail an assertion instead).
This is fixed here by re-enabling support for the VK_PPC_GAS_HA16/
VK_PPC_GAS_LO16 variant kinds (and their Darwin variants) in
PPCELFObjectWriter.cpp.
Tested by running projects/test-suite in -m32 mode with the integrated
assembler forced on. A standalone test case will be committed shortly
as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181450 91177308-0d34-0410-b5e6-96231b3b80d8
PCELFObjectWriter.cpp
|
| 8ade90930863acf94fbb2ccd91acefcf114c1f3e |
26-Apr-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
PowerPC: Support PC-relative fixup_ppc_brcond14.
When testing the asm parser, I ran into an error when using a conditional
branch to an external symbol (this doesn't occur in compiler-generated
code) due to missing support in PPCELFObjectWriter::getRelocTypeInner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180605 91177308-0d34-0410-b5e6-96231b3b80d8
PCELFObjectWriter.cpp
|
| abe64dc6f7363c7e6170568e382fb06d81d62f51 |
20-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Move PPC getSwappedPredicate for reuse
The getSwappedPredicate function can be used in other places (such as in
improvements to the PPCCTRLoops pass). Instead of trapping it as a static
function in PPCInstrInfo, move it into PPCPredicates with other
predicate-related things.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179926 91177308-0d34-0410-b5e6-96231b3b80d8
PCPredicates.cpp
PCPredicates.h
|
| aa6047d23d8ed55abd8545f5cbe82cd13cbd756a |
26-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Use HWEncoding and TRI->getEncodingValue
As pointed out by Jakob, we don't need to maintain a separate
register-numbering table. Instead we should let TableGen generate the table for
us from the information (already present) in PPCRegisterInfo.td.
TRI->getEncodingValue is now used to access register-encoding values.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178067 91177308-0d34-0410-b5e6-96231b3b80d8
PCBaseInfo.h
PCMCCodeEmitter.cpp
|
| d6f5a581ab968a2618b0c5a8472ea2ab37797916 |
26-Mar-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
Remove default case from fully covered switch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178025 91177308-0d34-0410-b5e6-96231b3b80d8
PCPredicates.cpp
|
| 65e90c036472380bba160c349412f37128608e1c |
26-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
PowerPC: Simplify handling of fixups.
MCTargetDesc/PPCMCCodeEmitter.cpp current has code like:
if (isSVR4ABI() && is64BitMode())
Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
(MCFixupKind)PPC::fixup_ppc_toc16));
else
Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
(MCFixupKind)PPC::fixup_ppc_lo16));
This is a problem for the asm parser, since it requires knowledge of
the ABI / 64-bit mode to be set up. However, more fundamentally,
at this point we shouldn't make such distinctions anyway; in an assembler
file, it always ought to be possible to e.g. generate TOC relocations even
when the main ABI is one that doesn't use TOC.
Fortunately, this is actually completely unnecessary; that code was added
to decide whether to generate TOC relocations, but that information is in
fact already encoded in the VariantKind of the underlying symbol.
This commit therefore merges those fixup types into one, and then decides
which relocation to use based on the VariantKind.
No changes in generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178007 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
PCELFObjectWriter.cpp
PCFixupKinds.h
PCMCCodeEmitter.cpp
|
| 3b2552933642c19ce5e8836d82c26c562910e239 |
26-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
PowerPC: Simplify BLR pattern.
The BLR pattern cannot be recognized by the asm parser in its current form.
This complexity is due to an apparent attempt to enable conditional BLR
variants. However, none of those can ever be generated by current code;
the pattern is only ever created using the default "pred" operand.
To simplify the pattern and allow it to be recognized by the parser,
this commit removes those attempts at conditional BLR support.
When we later come back to actually add real conditional BLR, this
should probably be done via a fully generic conditional branch pattern.
No change in generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178002 91177308-0d34-0410-b5e6-96231b3b80d8
PCPredicates.h
|
| 526d6c451bf7cbffdb6976f551c42607680c1e3a |
23-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC ZERO register needs a register number of 0.
In order for the new ZERO register to be used with MC, etc. we need to specify
its register number (0).
Thanks to Kai for reporting the problem!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177833 91177308-0d34-0410-b5e6-96231b3b80d8
PCBaseInfo.h
|
| 86765fbe170198e7bb40fd8499d1354f4c786f60 |
22-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Remove ABI-duplicated call instruction patterns.
We currently have a duplicated set of call instruction patterns depending
on the ABI to be followed (Darwin vs. Linux). This is a bit odd; while the
different ABIs will result in different instruction sequences, the actual
instructions themselves ought to be independent of the ABI. And in fact it
turns out that the only nontrivial difference between the two sets of
patterns is that in the PPC64 Linux ABI, the instruction used for indirect
calls is marked to take X11 as extra input register (which is indeed used
only with that ABI to hold an incoming environment pointer for nested
functions). However, this does not need to be hard-coded at the .td
pattern level; instead, the C++ code expanding calls can simply add that
use, just like it adds uses for argument registers anyway.
No change in generated code expected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177735 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCCodeEmitter.cpp
|
| 53856be683113838cc112331adca3717d4a520cc |
17-Mar-2013 |
Sylvestre Ledru <sylvestre@debian.org> |
To avoid symbol clash, undefine PPC here. PPC may be predefined on some hosts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177234 91177308-0d34-0410-b5e6-96231b3b80d8
PCFixupKinds.h
PCMCTargetDesc.h
PCPredicates.h
|
| fc7695a653323071ec141aee994e4188592ad1f5 |
25-Feb-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Fix missing relocation for TLS addressing peephole optimization.
Report and fix due to Kai Nacke. Testcase update by me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176029 91177308-0d34-0410-b5e6-96231b3b80d8
PCELFObjectWriter.cpp
|
| 06ab2c828a5605abec36eb0d6749940fa6eb7391 |
21-Feb-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Relocation enablement for PPC DAG postprocessing pass
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175693 91177308-0d34-0410-b5e6-96231b3b80d8
PCELFObjectWriter.cpp
|
| e807d1ea1e05fea895ba90dd4da8c91026ba1f29 |
23-Jan-2013 |
Eli Bendersky <eliben@google.com> |
Fix powerpc test failure - forgot to initialize stack slot size for PPCLinuxMCAsmInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173275 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCAsmInfo.cpp
|
| e752feee5228bfa33acee35ef9c606ce12f0f173 |
23-Jan-2013 |
Eli Bendersky <eliben@google.com> |
Clean up assignment of CalleeSaveStackSlotSize: get rid of the default and explicitly set this in every target that needs to change it from the default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173270 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCAsmInfo.cpp
|
| 251040bc18eedfa56d01fe92836e55cfd8c5d990 |
08-Jan-2013 |
Eli Bendersky <eliben@google.com> |
Renamed MCInstFragment to MCRelaxableFragment and added some comments.
No change in functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171822 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
|
| 7b449889e7886b263718b5103538970f287bc37e |
04-Jan-2013 |
Adhemerval Zanella <azanella@linux.vnet.ibm.com> |
PowerPC: Fix eh_frame relocation for PIC
This patch fixes the PPC eh_frame definitions for the personality and
frame unwinding for PIC objects. It makes PIC build correctly creates
relative relocations in the '.rela.eh_frame' segments and thus avoiding
a text relocation that generates a DT_TEXTREL segments in link phase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171506 91177308-0d34-0410-b5e6-96231b3b80d8
PCELFObjectWriter.cpp
|
| 399532b25a939d8c653fd453137bb8e01dc4b8fc |
20-Dec-2012 |
Rafael Espindola <rafael.espindola@gmail.com> |
Undefine PPC harder.
This was causing a build failure while trying to build on ppc ubuntu 12.10 with
cmake.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170668 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCTargetDesc.h
PCPredicates.h
|
| d3eb4f46f011f5880e09862559c17f03e38bef39 |
14-Dec-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch removes some nondeterminism from direct object file output
for TLS dynamic models on 64-bit PowerPC ELF. The default sort routine
for relocations only sorts on the r_offset field; but with TLS, there
can be two relocations with the same r_offset. For PowerPC, this patch
sorts secondarily on descending r_type, which matches the behavior
expected by the linker.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170237 91177308-0d34-0410-b5e6-96231b3b80d8
PCELFObjectWriter.cpp
|
| b453e16855f347e300f1dc0cd0dfbdd65c27b0d2 |
14-Dec-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch improves the 64-bit PowerPC InitialExec TLS support by providing
for a wider range of GOT entries that can hold thread-relative offsets.
This matches the behavior of GCC, which was not documented in the PPC64 TLS
ABI. The ABI will be updated with the new code sequence.
Former sequence:
ld 9,x@got@tprel(2)
add 9,9,x@tls
New sequence:
addis 9,2,x@got@tprel@ha
ld 9,x@got@tprel@l(9)
add 9,9,x@tls
Note that a linker optimization exists to transform the new sequence into
the shorter sequence when appropriate, by replacing the addis with a nop
and modifying the base register and relocation type of the ld.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170209 91177308-0d34-0410-b5e6-96231b3b80d8
PCELFObjectWriter.cpp
PCMCCodeEmitter.cpp
|
| 349c2787cf9e174c8aa955bf8e3b09a405b2aece |
12-Dec-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch implements local-dynamic TLS model support for the 64-bit
PowerPC target. This is the last of the four models, so we now have
full TLS support.
This is mostly a straightforward extension of the general dynamic model.
I had to use an additional Chain operand to tie ADDIS_DTPREL_HA to the
register copy following ADDI_TLSLD_L; otherwise everything above the
ADDIS_DTPREL_HA appeared dead and was removed.
As before, there are new test cases to test the assembly generation, and
the relocations output during integrated assembly. The expected code
gen sequence can be read in test/CodeGen/PowerPC/tls-ld.ll.
There are a couple of things I think can be done more efficiently in the
overall TLS code, so there will likely be a clean-up patch forthcoming;
but for now I want to be sure the functionality is in place.
Bill
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170003 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
PCELFObjectWriter.cpp
PCFixupKinds.h
PCMCCodeEmitter.cpp
|
| 57ac1f458a754f30cf500410b438fb260f9b8fe5 |
11-Dec-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch implements the general dynamic TLS model for 64-bit PowerPC.
Given a thread-local symbol x with global-dynamic access, the generated
code to obtain x's address is:
Instruction Relocation Symbol
addis ra,r2,x@got@tlsgd@ha R_PPC64_GOT_TLSGD16_HA x
addi r3,ra,x@got@tlsgd@l R_PPC64_GOT_TLSGD16_L x
bl __tls_get_addr(x@tlsgd) R_PPC64_TLSGD x
R_PPC64_REL24 __tls_get_addr
nop
<use address in r3>
The implementation borrows from the medium code model work for introducing
special forms of ADDIS and ADDI into the DAG representation. This is made
slightly more complicated by having to introduce a call to the external
function __tls_get_addr. Using the full call machinery is overkill and,
more importantly, makes it difficult to add a special relocation. So I've
introduced another opcode GET_TLS_ADDR to represent the function call, and
surrounded it with register copies to set up the parameter and return value.
Most of the code is pretty straightforward. I ran into one peculiarity
when I introduced a new PPC opcode BL8_NOP_ELF_TLSGD, which is just like
BL8_NOP_ELF except that it takes another parameter to represent the symbol
("x" above) that requires a relocation on the call. Something in the
TblGen machinery causes BL8_NOP_ELF and BL8_NOP_ELF_TLSGD to be treated
identically during the emit phase, so this second operand was never
visited to generate relocations. This is the reason for the slightly
messy workaround in PPCMCCodeEmitter.cpp:getDirectBrEncoding().
Two new tests are included to demonstrate correct external assembly and
correct generation of relocations using the integrated assembler.
Comments welcome!
Thanks,
Bill
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169910 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
PCELFObjectWriter.cpp
PCFixupKinds.h
PCMCCodeEmitter.cpp
|
| d7802bf0ddcac16ee910105922492aee86a53e1b |
04-Dec-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch introduces initial-exec model support for thread-local storage
on 64-bit PowerPC ELF.
The patch includes code to handle external assembly and MC output with the
integrated assembler. It intentionally does not support the "old" JIT.
For the initial-exec TLS model, the ABI requires the following to calculate
the address of external thread-local variable x:
Code sequence Relocation Symbol
ld 9,x@got@tprel(2) R_PPC64_GOT_TPREL16_DS x
add 9,9,x@tls R_PPC64_TLS x
The register 9 is arbitrary here. The linker will replace x@got@tprel
with the offset relative to the thread pointer to the generated GOT
entry for symbol x. It will replace x@tls with the thread-pointer
register (13).
The two test cases verify correct assembly output and relocation output
as just described.
PowerPC-specific selection node variants are added for the two
instructions above: LD_GOT_TPREL and ADD_TLS. These are inserted
when an initial-exec global variable is encountered by
PPCTargetLowering::LowerGlobalTLSAddress(), and later lowered to
machine instructions LDgotTPREL and ADD8TLS. LDgotTPREL is a pseudo
that uses the same LDrs support added for medium code model's LDtocL,
with a different relocation type.
The rest of the processing is straightforward.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169281 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
PCELFObjectWriter.cpp
PCFixupKinds.h
PCMCCodeEmitter.cpp
|
| d04a8d4b33ff316ca4cf961e06c9e312eff8e64f |
03-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.
Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
PCELFObjectWriter.cpp
PCMCCodeEmitter.cpp
PCMCTargetDesc.cpp
|
| 781dfbd482c5177215ae7a43c9483e641eeb0d47 |
28-Nov-2012 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Fix initial frame state on powerpc64.
The createPPCMCAsmInfo routine used PPC::R1 as the initial frame
pointer register, but on PPC64 the 32-bit R1 register does not
have a corresponding DWARF number, causing invalid CIE initial
frame state to be emitted. Fix by using PPC::X1 instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168799 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCTargetDesc.cpp
|
| daa65f5e08e19b1fac5f476cef45223b1b4e5a8e |
28-Nov-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch makes medium code model the default for 64-bit PowerPC ELF.
When the CodeGenInfo is to be created for the PPC64 target machine,
a default code-model selection is converted to CodeModel::Medium
provided we are not targeting the Darwin OS. Defaults for Darwin
are unaffected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168747 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCTargetDesc.cpp
|
| 34a9d4b3b9b7858b729a1af67afa721c048fe5e7 |
27-Nov-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch implements medium code model support for 64-bit PowerPC.
The default for 64-bit PowerPC is small code model, in which TOC entries
must be addressable using a 16-bit offset from the TOC pointer. Additionally,
only TOC entries are addressed via the TOC pointer.
With medium code model, TOC entries and data sections can all be addressed
via the TOC pointer using a 32-bit offset. Cooperation with the linker
allows 16-bit offsets to be used when these are sufficient, reducing the
number of extra instructions that need to be executed. Medium code model
also does not generate explicit TOC entries in ".section toc" for variables
that are wholly internal to the compilation unit.
Consider a load of an external 4-byte integer. With small code model, the
compiler generates:
ld 3, .LC1@toc(2)
lwz 4, 0(3)
.section .toc,"aw",@progbits
.LC1:
.tc ei[TC],ei
With medium model, it instead generates:
addis 3, 2, .LC1@toc@ha
ld 3, .LC1@toc@l(3)
lwz 4, 0(3)
.section .toc,"aw",@progbits
.LC1:
.tc ei[TC],ei
Here .LC1@toc@ha is a relocation requesting the upper 16 bits of the
32-bit offset of ei's TOC entry from the TOC base pointer. Similarly,
.LC1@toc@l is a relocation requesting the lower 16 bits. Note that if
the linker determines that ei's TOC entry is within a 16-bit offset of
the TOC base pointer, it will replace the "addis" with a "nop", and
replace the "ld" with the identical "ld" instruction from the small
code model example.
Consider next a load of a function-scope static integer. For small code
model, the compiler generates:
ld 3, .LC1@toc(2)
lwz 4, 0(3)
.section .toc,"aw",@progbits
.LC1:
.tc test_fn_static.si[TC],test_fn_static.si
.type test_fn_static.si,@object
.local test_fn_static.si
.comm test_fn_static.si,4,4
For medium code model, the compiler generates:
addis 3, 2, test_fn_static.si@toc@ha
addi 3, 3, test_fn_static.si@toc@l
lwz 4, 0(3)
.type test_fn_static.si,@object
.local test_fn_static.si
.comm test_fn_static.si,4,4
Again, the linker may replace the "addis" with a "nop", calculating only
a 16-bit offset when this is sufficient.
Note that it would be more efficient for the compiler to generate:
addis 3, 2, test_fn_static.si@toc@ha
lwz 4, test_fn_static.si@toc@l(3)
The current patch does not perform this optimization yet. This will be
addressed as a peephole optimization in a later patch.
For the moment, the default code model for 64-bit PowerPC will remain the
small code model. We plan to eventually change the default to medium code
model, which matches current upstream GCC behavior. Note that the different
code models are ABI-compatible, so code compiled with different models will
be linked and execute correctly.
I've tested the regression suite and the application/benchmark test suite in
two ways: Once with the patch as submitted here, and once with additional
logic to force medium code model as the default. The tests all compile
cleanly, with one exception. The mandel-2 application test fails due to an
unrelated ABI compatibility with passing complex numbers. It just so happens
that small code model was incredibly lucky, in that temporary values in
floating-point registers held the expected values needed by the external
library routine that was called incorrectly. My current thought is to correct
the ABI problems with _Complex before making medium code model the default,
to avoid introducing this "regression."
Here are a few comments on how the patch works, since the selection code
can be difficult to follow:
The existing logic for small code model defines three pseudo-instructions:
LDtoc for most uses, LDtocJTI for jump table addresses, and LDtocCPT for
constant pool addresses. These are expanded by SelectCodeCommon(). The
pseudo-instruction approach doesn't work for medium code model, because
we need to generate two instructions when we match the same pattern.
Instead, new logic in PPCDAGToDAGISel::Select() intercepts the TOC_ENTRY
node for medium code model, and generates an ADDIStocHA followed by either
a LDtocL or an ADDItocL. These new node types correspond naturally to
the sequences described above.
The addis/ld sequence is generated for the following cases:
* Jump table addresses
* Function addresses
* External global variables
* Tentative definitions of global variables (common linkage)
The addis/addi sequence is generated for the following cases:
* Constant pool entries
* File-scope static global variables
* Function-scope static variables
Expanding to the two-instruction sequences at select time exposes the
instructions to subsequent optimization, particularly scheduling.
The rest of the processing occurs at assembly time, in
PPCAsmPrinter::EmitInstruction. Each of the instructions is converted to
a "real" PowerPC instruction. When a TOC entry needs to be created, this
is done here in the same manner as for the existing LDtoc, LDtocJTI, and
LDtocCPT pseudo-instructions (I factored out a new routine to handle this).
I had originally thought that if a TOC entry was needed for LDtocL or
ADDItocL, it would already have been generated for the previous ADDIStocHA.
However, at higher optimization levels, the ADDIStocHA may appear in a
different block, which may be assembled textually following the block
containing the LDtocL or ADDItocL. So it is necessary to include the
possibility of creating a new TOC entry for those two instructions.
Note that for LDtocL, we generate a new form of LD called LDrs. This
allows specifying the @toc@l relocation for the offset field of the LD
instruction (i.e., the offset is replaced by a SymbolLo relocation).
When the peephole optimization described above is added, we will need
to do similar things for all immediate-form load and store operations.
The seven "mcm-n.ll" test cases are kept separate because otherwise the
intermingling of various TOC entries and so forth makes the tests fragile
and hard to understand.
The above assumes use of an external assembler. For use of the
integrated assembler, new relocations are added and used by
PPCELFObjectWriter. Testing is done with "mcm-obj.ll", which tests for
proper generation of the various relocations for the same sequences
tested with the external assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168708 91177308-0d34-0410-b5e6-96231b3b80d8
PCELFObjectWriter.cpp
|
| d3022b894691017169ff0681c6bea18725330cd1 |
24-Nov-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
PPC: Reinstate the fatal error when trying to emit a macho file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168543 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
|
| e8ca482c9734a556f3b66d44ba27e23a1d00b1e0 |
24-Nov-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
PPC: Share applyFixup between ELF and Darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168540 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
|
| ba6086818d9c5070061f74ac9944666b4312c6f0 |
13-Nov-2012 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Add (some) PowerPC TLS relocation types to ELF.h and
generate them from PPCELFObjectWriter::getRelocTypeInner
as appropriate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167864 91177308-0d34-0410-b5e6-96231b3b80d8
PCELFObjectWriter.cpp
|
| 18560fae0bb122857a61bb36f22628901cdc3dde |
25-Oct-2012 |
Adhemerval Zanella <azanella@linux.vnet.ibm.com> |
This patch fixes the MC object emission of 'nop' for external function calls
and also fixes the R_PPC64_TOC16 and R_PPC64_TOC16_DS relocation offset.
The 'nop' is needed so a restore TOC instruction (ld r2,40(r1)) can be placed
by the linker to correct restore the TOC of previous function.
Current code has two issues: it defines in PPCInstr64Bit.td file a LDinto_toc
and LDtoc_restore as a DSForm_1 with DS_RA=0 where it should be
DS=2 (the 8 bytes displacement of the TOC saving). It also wrongly emits a
MC intruction using an uint32_t value while the PPC::BL8_NOP_ELF
and PPC::BLA8_NOP_ELF are both uint64_t (because of the following 'nop').
This patch corrects the remaining ExecutionEngine using MCJIT:
ExecutionEngine/2002-12-16-ArgTest.ll
ExecutionEngine/2003-05-07-ArgumentTest.ll
ExecutionEngine/2005-12-02-TailCallBug.ll
ExecutionEngine/hello.ll
ExecutionEngine/hello2.ll
ExecutionEngine/test-call.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166682 91177308-0d34-0410-b5e6-96231b3b80d8
PCELFObjectWriter.cpp
PCMCCodeEmitter.cpp
|
| aa71428378c1cb491ca60041d8ba7aa110bc963d |
25-Oct-2012 |
Adhemerval Zanella <azanella@linux.vnet.ibm.com> |
Initial TOC support for PowerPC64 object creation
This patch adds initial PPC64 TOC MC object creation using the small mcmodel
(a single 64K TOC) adding the some TOC relocations (R_PPC64_TOC,
R_PPC64_TOC16, and R_PPC64_TOC16DS).
The addition of 'undefinedExplicitRelSym' hook on 'MCELFObjectTargetWriter'
is meant to avoid the creation of an unreferenced ".TOC." symbol (used in
the .odp creation) as well to set the R_PPC64_TOC relocation target as the
temporary ".TOC." symbol. On PPC64 ABI, the R_PPC64_TOC relocation should
not point to any symbol.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166677 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
PCELFObjectWriter.cpp
PCFixupKinds.h
PCMCCodeEmitter.cpp
|
| cd585084e500a36208a7185edf62cb279f83c26b |
08-Oct-2012 |
Adhemerval Zanella <azanella@linux.vnet.ibm.com> |
PowerPC: Fix object creation with PPC::MTCRF8 instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165411 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCCodeEmitter.cpp
|
| 536a88ad5bf160232205192a7ce72e50bfadbded |
18-Sep-2012 |
Roman Divacky <rdivacky@freebsd.org> |
When creating MCAsmBackend pass the CPU string as well. In X86AsmBackend
store this and use it to not emit long nops when the CPU is geode which
doesnt support them.
Fixes PR11212.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164132 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
PCMCTargetDesc.h
|
| 86a1c32e67b23c5e9e42dff9eb86e99ba15bb42f |
15-Sep-2012 |
Craig Topper <craig.topper@gmail.com> |
Use LLVM_DELETED_FUNCTION in place of 'DO NOT IMPLEMENT' comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163974 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCCodeEmitter.cpp
|
| ba9d069d797fbe204470c18a5f15e7f3cf763e0b |
12-Sep-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Enable exceptions handling on PPC64 now that cr misaligned spilling
was fixed in r163713.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163715 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCAsmInfo.cpp
|
| 39646d96e76aea5d20bffb386233a0dbb5932a21 |
07-Sep-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
MC: Overhaul handling of .lcomm
- Darwin lied about not supporting .lcomm and turned it into zerofill in the
asm parser. Push the zerofill-conversion down into macho-specific code.
- This makes the tri-state LCOMMType enum superfluous, there are no targets
without .lcomm.
- Do proper error reporting when trying to use .lcomm with alignment on a target
that doesn't support it.
- .comm and .lcomm alignment was parsed in bytes on COFF, should be power of 2.
- Fixes PR13755 (.lcomm crashes on ELF).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163395 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCAsmInfo.cpp
|
| 05b2bc8781d9af403a257599613e12cb8fef19e8 |
16-Aug-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Revert r162034, r162035 and r162037.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162039 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
PCFixupKinds.h
|
| e88d17de99c5f46bc8104bc777f657d0299fd0e6 |
16-Aug-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Define and handle additional fixup kinds. By Adhemerval Zanella.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162037 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
PCFixupKinds.h
|
| 918f55fe239f00651e396be841f2b3b6e242f98d |
15-May-2012 |
Jim Grosbach <grosbach@apple.com> |
Allow MCCodeEmitter access to the target MCRegisterInfo.
Add the MCRegisterInfo to the factories and constructors.
Patch by Tom Stellard <Tom.Stellard@amd.com>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156828 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCCodeEmitter.cpp
PCMCTargetDesc.h
|
| 17463b3ef1a3d39b10619254f12e806c8c43f9e7 |
02-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Make MCInstrInfo available to the MCInstPrinter. This will be used to remove getInstructionName and the static data it contains since the same tables are already in MCInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153860 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCTargetDesc.cpp
|
| f1d0f7781e766df878bec4e7977fa3204374f394 |
26-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Prune some includes and forward declarations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153429 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
|
| 79aa3417eb6f58d668aadfedf075240a41d35a26 |
17-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152997 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
|
| c6449b636f4984be88f128d0375c056ad05e7e8f |
05-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
Make MCRegisterInfo available to the the MCInstPrinter.
Used to allow context sensitive printing of super-register or sub-register
references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152043 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCTargetDesc.cpp
|
| 31d157ae1ac2cd9c787dc3c1d28e64c682803844 |
18-Feb-2012 |
Jia Liu <proljc@gmail.com> |
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
PCBaseInfo.h
PCMCAsmInfo.cpp
PCMCAsmInfo.h
PCMCTargetDesc.cpp
|
| bc2198133a1836598b54b943420748e75d5dea94 |
07-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Convert assert(0) to llvm_unreachable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149961 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
|
| 655b8de7b2ab773a977e0c524307e71354d8af29 |
05-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Convert assert(0) to llvm_unreachable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149814 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCTargetDesc.cpp
|
| 4f8dc7b17accf4f2ec953b80b2cc79786207492e |
24-Jan-2012 |
Owen Anderson <resistor@mac.com> |
Widen the instruction encoder that TblGen emits to a 64 bits, which should accomodate every target I can think of offhand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148833 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCCodeEmitter.cpp
|
| bc3af9b618c061294c7df00f3313f9c5234b8450 |
18-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. 80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148401 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
|
| ec3433852dd11e8ff60c9610b4c84468e5935f2b |
18-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. MCAsmBackend naming conventions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148400 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
|
| f51e95a9f2ce10ca0eb8a353e1fc1d9d49ec130c |
22-Dec-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix an incomplete refactoring of the ppc backend. Thanks to rdivacky for reporting
it. It does need some some tests...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147154 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
PCELFObjectWriter.cpp
|
| dcc557f1463107d0f2f6b0099c99593b8fce4e36 |
22-Dec-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix cmake.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147126 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| f3a86fb03d196994dc7923351f15d8ed9343013e |
22-Dec-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Move PPC bits to lib/Target/PowerPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147124 91177308-0d34-0410-b5e6-96231b3b80d8
PCELFObjectWriter.cpp
PCMCTargetDesc.h
|
| dc9a8a378daf432d8dcfc178507afe149706f9a6 |
21-Dec-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Reduce the exposure of Triple::OSType in the ELF object writer. This will
avoid including ADT/Triple.h in many places when the target specific bits are
moved.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147059 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
|
| 2d24e2a396a1d211baaeedf32148a3b657240170 |
20-Dec-2011 |
David Blaikie <dblaikie@gmail.com> |
Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146960 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCAsmInfo.cpp
PCMCAsmInfo.h
|
| 4ab406d7fc06b1272d02cd8be46f0c5ebe51a3da |
12-Dec-2011 |
Daniel Dunbar <daniel@zuster.org> |
LLVMBuild: Remove trailing newline, which irked me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146409 91177308-0d34-0410-b5e6-96231b3b80d8
LVMBuild.txt
|
| 6482e9114954def43fc08e83aadec1aadfc64200 |
06-Dec-2011 |
NAKAMURA Takumi <geek4civic@gmail.com> |
MipsAsmBackend.cpp, PPCAsmBackend.cpp: Fix -Asserts build to appease msvc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145894 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
|
| 370b78d795154899a22ca2b4674e890661ff1d59 |
06-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Move target-specific logic out of generic MCAssembler.
Whether a fixup needs relaxation for the associated instruction is a
target-specific function, as the FIXME indicated. Create a hook for that
and use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145881 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
|
| d782bae970e888572f0458ac05369bbd7752f05a |
29-Nov-2011 |
Daniel Dunbar <daniel@zuster.org> |
build/CMake: Finish removal of add_llvm_library_dependencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145420 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| b95fc31aa2e5a0a0b9ee1909d1cb949577c5aa16 |
16-Nov-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sink codegen optimization level into MCCodeGenInfo along side relocation model
and code model. This eliminates the need to pass OptLevel flag all over the
place and makes it possible for any codegen pass to use this information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144788 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCTargetDesc.cpp
|
| a3a2dfd4a2a8265a9a0c962cb776e2e6ba123956 |
03-Nov-2011 |
Daniel Dunbar <daniel@zuster.org> |
build: Add initial cut at LLVMBuild.txt files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143634 91177308-0d34-0410-b5e6-96231b3b80d8
LVMBuild.txt
|
| b950585cc5a0d665e9accfe5ce490cd269756f2e |
07-Sep-2011 |
James Molloy <james.molloy@arm.com> |
Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= handling to llvm-mc. Reviewed by Owen Anderson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139237 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCTargetDesc.cpp
|
| 36a16015ac108e2f0dd2d6d96a6d364bc74c50d7 |
02-Sep-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Don't drop alignment info on local common symbols.
- On COFF the .lcomm directive has an alignment argument.
- On ELF we fall back to .local + .comm
Based on a patch by NAKAMURA Takumi.
Fixes PR9337, PR9483 and PR10128.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138976 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCAsmInfo.cpp
|
| 3e74d6fdd248e20a280f1dff3da9a6c689c2c4c3 |
24-Aug-2011 |
Evan Cheng <evan.cheng@apple.com> |
Move TargetRegistry and TargetSelect from Target to Support where they belong.
These are strictly utilities for registering targets and components.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138450 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
PCMCTargetDesc.cpp
|
| 7801136b95d1fbe515b9655b73ada39b05a33559 |
23-Aug-2011 |
Evan Cheng <evan.cheng@apple.com> |
Some refactoring so TargetRegistry.h no longer has to include any files
from MC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138367 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCTargetDesc.cpp
|
| 29630ff214085365d11f1a58251ba07326e21398 |
02-Aug-2011 |
Roman Divacky <rdivacky@freebsd.org> |
Remove trailing semicolon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136690 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCTargetDesc.cpp
|
| 2c0d69fad0e658117922f3d96d9b732bedf9fd47 |
02-Aug-2011 |
Roman Divacky <rdivacky@freebsd.org> |
Sketch out PowerPC ELF writer. This is enough to get clang -integrated-as
to compile a working hello world on FreeBSD/PPC32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136689 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
PCMCTargetDesc.cpp
|
| 8ead80db20ec05fd8e613084abfdb8714703fc5f |
01-Aug-2011 |
Evan Cheng <evan.cheng@apple.com> |
Set endianess and pointer size for PPC Linux. Bug noticed by Roman Divacky.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136639 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCAsmInfo.cpp
|
| ac03e736c77bcf7e8deb515fc16a7e55d343dc8d |
29-Jul-2011 |
Chandler Carruth <chandlerc@gmail.com> |
Rewrite the CMake build to use explicit dependencies between libraries,
specified in the same file that the library itself is created. This is
more idiomatic for CMake builds, and also allows us to correctly specify
dependencies that are missed due to bugs in the GenLibDeps perl script,
or change from compiler to compiler. On Linux, this returns CMake to
a place where it can relably rebuild several targets of LLVM.
I have tried not to change the dependencies from the ones in the current
auto-generated file. The only places I've really diverged are in places
where I was seeing link failures, and added a dependency. The goal of
this patch is not to start changing the dependencies, merely to move
them into the correct location, and an explicit form that we can control
and change when necessary.
This also removes a serialization point in the build because we don't
have to scan all the libraries before we begin building various tools.
We no longer have a step of the build that regenerates a file inside the
source tree. A few other associated cleanups fall out of this.
This isn't really finished yet though. After talking to dgregor he urged
switching to a single CMake macro to construct libraries with both
sources and dependencies in the arguments. Migrating from the two macros
to that style will be a follow-up patch.
Also, llvm-config is still generated with GenLibDeps.pl, which means it
still has slightly buggy dependencies. The internal CMake
'llvm-config-like' macro uses the correct explicitly specified
dependencies however. A future patch will switch llvm-config generation
(when using CMake) to be based on these deps as well.
This may well break Windows. I'm getting a machine set up now to dig
into any failures there. If anyone can chime in with problems they see
or ideas of how to solve them for Windows, much appreciated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136433 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 4ebc5916e9b3a43af8aff8e1b8744b1644457a4b |
28-Jul-2011 |
Oscar Fuentes <ofv@wanadoo.es> |
Explicitly declare a library dependency of LLVM*Desc to
LLVM*AsmPrinter.
GenLibDeps.pl fails to detect vtable references. As this is the only
referenced symbol from LLVM*Desc to LLVM*AsmPrinter on optimized
builds, the algorithm that creates the list of libraries to be linked
into tools doesn't know about the dependency and sometimes places the
libraries on the wrong order, yielding error messages like this:
../../lib/libLLVMARMDesc.a(ARMMCTargetDesc.cpp.o): In function
`llvm::ARMInstPrinter::ARMInstPrinter(llvm::MCAsmInfo const&)':
ARMMCTargetDesc.cpp:(.text._ZN4llvm14ARMInstPrinterC1ERKNS_9MCAsmInfoE
[llvm::ARMInstPrinter::ARMInstPrinter(llvm::MCAsmInfo
const&)]+0x2a): undefined reference to `vtable for
llvm::ARMInstPrinter'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136328 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 28c85a81a17dd719a254dc00cbeb484774893197 |
26-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename createCodeEmitter to createMCCodeEmitter; createObjectStreamer to createMCObjectStreamer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136031 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCTargetDesc.cpp
|
| 94b9550a32d189704a8eae55505edf62662c0534 |
26-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename TargetAsmParser to MCTargetAsmParser and TargetAsmLexer to MCTargetAsmLexer; rename createAsmLexer to createMCAsmLexer and createAsmParser to createMCAsmParser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136027 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
PCPredicates.cpp
PCPredicates.h
|
| b35552d440581265a982d7523c33e7466437bfb0 |
26-Jul-2011 |
Chandler Carruth <chandlerc@gmail.com> |
Clean up a pile of hacks in our CMake build relating to TableGen.
The first problem to fix is to stop creating synthetic *Table_gen
targets next to all of the LLVM libraries. These had no real effect as
CMake specifies that add_custom_command(OUTPUT ...) directives (what the
'tablegen(...)' stuff expands to) are implicitly added as dependencies
to all the rules in that CMakeLists.txt.
These synthetic rules started to cause problems as we started more and
more heavily using tablegen files from *subdirectories* of the one where
they were generated. Within those directories, the set of tablegen
outputs was still available and so these synthetic rules added them as
dependencies of those subdirectories. However, they were no longer
properly associated with the custom command to generate them. Most of
the time this "just worked" because something would get to the parent
directory first, and run tablegen there. Once run, the files existed and
the build proceeded happily. However, as more and more subdirectories
have started using this, the probability of this failing to happen has
increased. Recently with the MC refactorings, it became quite common for
me when touching a large enough number of targets.
To add insult to injury, several of the backends *tried* to fix this by
adding explicit dependencies back to the parent directory's tablegen
rules, but those dependencies didn't work as expected -- they weren't
forming a linear chain, they were adding another thread in the race.
This patch removes these synthetic rules completely, and adds a much
simpler function to declare explicitly that a collection of tablegen'ed
files are referenced by other libraries. From that, we can add explicit
dependencies from the smaller libraries (such as every architectures
Desc library) on this and correctly form a linear sequence. All of the
backends are updated to use it, sometimes replacing the existing attempt
at adding a dependency, sometimes adding a previously missing dependency
edge.
Please let me know if this causes any problems, but it fixes a rather
persistent and problematic source of build flakiness on our end.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136023 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 78c10eeaa57d1c6c4b7781d3c0bcb0cfbbc43b5c |
26-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename TargetAsmBackend to MCAsmBackend; rename createAsmBackend to createMCAsmBackend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136010 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
PCMCTargetDesc.cpp
PCMCTargetDesc.h
|
| 4b64e8a9e13ba782da2034e1dee52f077bdb759c |
25-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Separate MCInstPrinter registration from AsmPrinter registration.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135974 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCTargetDesc.cpp
|
| 54134708f5debe1631f9ea9b232f78758a2151e4 |
25-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Code clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135954 91177308-0d34-0410-b5e6-96231b3b80d8
PCBaseInfo.h
|
| b024572444d19a6e06624328ea6a75a2f3342eaf |
25-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Missed a file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135943 91177308-0d34-0410-b5e6-96231b3b80d8
PCBaseInfo.h
|
| 966aeb5788c242cfaca35c56c0ddc0ff778d4376 |
25-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Refactor PPC target to separate MC routines from Target routines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135942 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
PCAsmBackend.cpp
PCFixupKinds.h
PCMCCodeEmitter.cpp
PCMCTargetDesc.cpp
PCMCTargetDesc.h
|
| 7f8dff65717b1e4090ba4a648f9ec4f037a66c1e |
23-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
createXXXMCCodeGenInfo should be static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135826 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCTargetDesc.cpp
|
| e78085a3c03de648a481e9751c3094c517bd7123 |
22-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Combine all MC initialization routines into one. e.g. InitializeX86MCAsmInfo,
InitializeX86MCInstrInfo, etc. are combined into InitializeX86TargetMC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135812 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCTargetDesc.cpp
|
| 34ad6db8b958fdc0d38e122edf753b5326e69b03 |
20-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Move CodeModel from a TargetMachine global option to MCCodeGenInfo.
- Introduce JITDefault code model. This tells targets to set different default
code model for JIT. This eliminates the ugly hack in TargetMachine where
code model is changed after construction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135580 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCTargetDesc.cpp
|
| 439661395fd2a2a832dba01c65bc88718528313c |
19-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Introduce MCCodeGenInfo, which keeps information that can affect codegen
(including compilation, assembly). Move relocation model Reloc::Model from
TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135468 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCTargetDesc.cpp
|
| 2d28617de2b0b731c08d1af9e830f31e14ac75b4 |
19-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions for
better location welcome).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135438 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCTargetDesc.cpp
|
| 0e6a052331f674dd70e28af41f654a7874405eab |
18-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down
to MCRegisterInfo. Also initialize the mapping at construction time.
This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step
towards fixing the layering violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135424 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCTargetDesc.cpp
|
| 1be0e271a07925b928ba89848934f1ea6f1854e2 |
15-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Move some parts of TargetAsmInfo down to MCAsmInfo. This is not the greatest
solution but it is a small step towards removing the horror that is
TargetAsmInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135237 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCAsmInfo.cpp
|
| 1abf2cb59b8d63415780a03329307c0997b2670c |
15-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename createAsmInfo to createMCAsmInfo and move registration code to MCTargetDesc to prepare for next round of changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135219 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
PCMCAsmInfo.cpp
PCMCAsmInfo.h
PCMCTargetDesc.cpp
|
| c60f9b752381baa6c4b80c0739034660f1748c84 |
14-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Next round of MC refactoring. This patch factor MC table instantiations, MC
registeration and creation code into XXXMCDesc libraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135184 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
akefile
PCMCTargetDesc.cpp
PCMCTargetDesc.h
|