| 9a548c27aa704236cc1d8a5d4ebf68cea9c5c99c |
|
12-Jan-2012 |
Brian Paul <brianp@vmware.com> |
mesa: remove _mesa_ffs(), implement ffs() for non-GNU platforms
Call ffs() and ffsll() everywhere. Define our own ffs(), ffsll()
functions when the platform doesn't have them.
v2: remove #ifdef _WIN32, __IBMC__, __IBMCPP_ tests inside ffs()
implementation. The #else clause was recursive.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Alexander von Gluck <kallisti5@unixzen.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 1b05fc7cdd0e5d77b50bc8ee2f2c851da5884d72 |
|
07-Dec-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Factor out texturing related data from brw_wm_prog_key.
The idea is to reuse this for the VS and (in the future) GS as well.
v2: Include yuvtex data since we're not dropping GL_MESA_ycbycr.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net> [v1]
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| f98bfb5d68423a4e57f78091c70288c0b558b8bd |
|
22-Nov-2011 |
Eric Anholt <eric@anholt.net> |
i965: Fix EXT_texture_swizzle with a writemask in the FFFS/FP backend.
I tripped over this bug in the next commit, relying on our
EXT_texture_swizzle to do some shadow sampler-related swizzling. If a
writemask was masking out a channel of the destination that was a live
channel of the texture swizzle, it would read undefined values.
Fixes piglit ARB_fragment_program_shadow/masked.
Reviewed-by: Ian Romanick <idr@freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 26cfca825d7cdba753d138172285b5c2adf25c4b |
|
22-Oct-2011 |
Eric Anholt <eric@anholt.net> |
i965: Remove some old texturing debug code.
It caught one possible bug I recall in my time working on the driver,
and we haven't been setting it for non-fixed-function since the new FS
backend came along. The bug it caught was likely a confusion about
sampler mappings, which we have tests for these days.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 2e5a1a254ed81b1d3efa6064f48183eefac784d0 |
|
07-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
intel: Convert from GLboolean to 'bool' from stdbool.h.
I initially produced the patch using this bash command:
for file in {intel,i915,i965}/*.{c,cpp,h}; do [ ! -h $file ] && sed -i
's/GLboolean/bool/g' $file && sed -i 's/GL_TRUE/true/g' $file && sed -i
's/GL_FALSE/false/g' $file; done
Then I manually added #include <stdbool.h> to fix compilation errors,
and converted a few functions back to GLboolean that were used in core
Mesa's function pointer table to avoid "incompatible pointer" warnings.
Finally, I cleaned up some whitespace issues introduced by the change.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chad Versace <chad@chad-versace.us>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 9d4b98eb9eadecc17cd1cda0074b420a39e74647 |
|
17-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/gen6+: Use non-normalized coordinates for GL_TEXTURE_RECTANGLE.
Improves performance of a GL_TEXTURE_RECTANGLE microbenchmark by 1.84%
+/- .15% (n=3)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| a9e97d022cb68266639eb54947517454c8ffe45e |
|
05-Aug-2011 |
Eric Anholt <eric@anholt.net> |
intel: Fix warnings from gl_constant_parameter changes.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 46a7639174d2c55c30ec24b179cbef059fb3ca43 |
|
08-Jul-2011 |
Eric Anholt <eric@anholt.net> |
i965: Fix fp-dst-aliasing-[12].vpfp.
There's no pretty way to avoid the overwriting of the src operands, so
just use a temporary destination and rely on the MOV optimization.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| e3ea5bc08e32119d05bce543c07c61ce93869e60 |
|
08-Jul-2011 |
Eric Anholt <eric@anholt.net> |
i965: Fix fp-lit-src-equals-dst.
We were stomping over the source for the body of the LIT instruction
when doing the MOV of 1.0 to the uninteresting channels.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| f147599ef4b0d14c25a7e0d3f9f1c9b0229bb6fc |
|
19-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Remove linear_color for GL_PERSPECTIVE_CORRECTION_HINT.
From the GL 2.1 spec:
"Required perspective-correct interpolation for all fragment
attributes except depth in sections 3.4.1 and 3.5.1, effectively
making GL PERSPECTIVE CORRECT HINT a no-op."
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 79bde19ef9e13d5db30d0516d9e7eae6a3a8d32a |
|
21-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965: Don't double-emit fragment.color writes for MRT with ARB_fp.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| fa0d5a2c5bfb6109d365a6f0b9bee53dfee50325 |
|
07-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Always hand the absolute value to RSQ.
gen6 builtin RSQ apparently clamps negative values to 0 instead of
returning the RSQ of the absolute value like ARB_fragment_program
desires and pre-gen6 apparently does.
Fixes:
glean/fp1-RSQ test 2 (reciprocal square root of negative value)
glean/vp1-RSQ test 2 (reciprocal square root of negative value)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| ad35528944960f1619e0a9491164c848b333e6cf |
|
13-Nov-2010 |
Eric Anholt <eric@anholt.net> |
i965: Provide delta_xy reg to gen6 non-GLSL path PINTERP.
Fixes many assertion failures in that path.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 3168c6ff1a239d089180be77a5774b566aade1e9 |
|
05-Nov-2010 |
Vinson Lee <vlee@vmware.com> |
i965: Silence uninitialized variable warning.
Silences this GCC warning.
brw_wm_fp.c: In function 'brw_wm_pass_fp':
brw_wm_fp.c:966: warning: 'last_inst' may be used uninitialized in this function
brw_wm_fp.c:966: note: 'last_inst' was declared here
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 03577f8250cc7c8cdbd6ce1e166d9c1315c15280 |
|
05-Nov-2010 |
Vinson Lee <vlee@vmware.com> |
i965: Silence uninitialized variable warning.
Silences this GCC warning.
brw_wm_fp.c: In function 'precalc_tex':
brw_wm_fp.c:666: warning: 'tmpcoord.Index' may be used uninitialized in this function
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| bb1540835056cdea5db6f55b19c0c87358f14cd1 |
|
03-Nov-2010 |
Eric Anholt <eric@anholt.net> |
intel: Annotate debug printout checks with unlikely().
This provides the optimizer with hints about code hotness, which we're
quite certain about for debug printouts (or, rather, while we
developers often hit the checks for debug printouts, we don't care
about performance while doing so).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| e7843363a5cb1a7e6c206e2bc79f03bd58312820 |
|
09-Oct-2010 |
Vinson Lee <vlee@vmware.com> |
i965: Initialize member variables.
Fixes these GCC warnings.
brw_wm_fp.c: In function 'search_or_add_const4f':
brw_wm_fp.c:92: warning: 'reg.Index2' is used uninitialized in this function
brw_wm_fp.c:84: note: 'reg.Index2' was declared here
brw_wm_fp.c:92: warning: 'reg.RelAddr2' is used uninitialized in this function
brw_wm_fp.c:84: note: 'reg.RelAddr2' was declared here
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 5b24d69fcd6359dc959ec465c7e77b4626a27e72 |
|
08-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Handle swizzles in the addition of YUV texture constants.
If someone happened to land a set in a different swizzle order, we
would have assertion failed.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 0534e958c9d7fc854b64ad38964863e895e5a317 |
|
08-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Drop the check for YUV constants in the param list.
_mesa_add_unnamed_constant() already does that.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| fa8aba9da429e12fe77c0c78b6945d6ed1d7057c |
|
08-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Drop the check for duplicate _mesa_add_state_reference.
_mesa_add_state_reference does that check for us anyway.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| f1dba030564e66ca52f4ed44172681e7d2e90ad2 |
|
28-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix all non-snb regression in the snb attribute interpolation commit.
This apparently had never been tested elsewhere before being merged to
master.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| a66e9a4d86d227b65874c43fbf9e299c7a26389f |
|
26-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for attribute interpolation on Sandybridge.
Things are simpler these days thanks to barycentric interpolation
parameters being handed in in the payload.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 72fd0568db0ce5f25a1eee0266ec1e7cb3dafab0 |
|
05-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Settle on printing our program debug to stdout.
Mixing stderr (_mesa_print_program, _mesa_print_instruction,
_mesa_print_alu) with stdout means that when writing both to a file,
there isn't a consistent ordering between the two.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| b10bb527eaf39378da25dd4ad21b1c68ceaa1e2d |
|
03-Aug-2010 |
Eric Anholt <eric@anholt.net> |
Initialize a couple of HasIndex2 fields on Mesa IR src regs.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| ec2b92f98c2e7f161521b447cc1d9a36bce3707c |
|
11-Jun-2010 |
Brian Paul <brianp@vmware.com> |
mesa: rename src/mesa/shader/ to src/mesa/program/
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 298be2b028263b2c343a707662c6fbfa18293cb2 |
|
19-Feb-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
Replace the _mesa_*printf() wrappers with the plain libc versions
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 15fa484f514726a29bbf24df33c0551844f878d0 |
|
18-Nov-2009 |
Eric Anholt <eric@anholt.net> |
mesa: Remove gratuitous padding in prog_dst_register.
The padding was there to indicate the amount of space left from the
number of expected bytes in the struct minus allocated bits. But
uint bitfields get packed so that they don't cross uint boundaries, and we
ended up allocating an extra dword to hold the pad field!
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 5606dfb572bf4b89b4882265924705bacc8c182b |
|
18-Nov-2009 |
Ian Romanick <ian.d.romanick@intel.com> |
Merge branch 'outputswritten64'
Add a GLbitfield64 type and several macros to operate on 64-bit
fields. The OutputsWritten field of gl_program is changed to use that
type. This results in a fair amount of fallout in drivers that use
programs.
No changes are strictly necessary at this point as all bits used are
below the 32-bit boundary. Fairly soon several bits will be added for
clip distances written by a vertex shader. This will cause several
bits used for varyings to be pushed above the 32-bit boundary. This
will affect any drivers that support GLSL.
At this point, only the i965 driver has been modified to support this
eventuality.
I did this as a "squash" merge. There were several places through the
outputswritten64 branch where things were broken. I foresee this
causing difficulties later for bisecting. The history is still
available in the branch.
Conflicts:
src/mesa/drivers/dri/i965/brw_wm.h
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| c5413839b3e99c7b162f1260142f3c175502b0ce |
|
11-Nov-2009 |
Eric Anholt <eric@anholt.net> |
i965: avoid memsetting all the BRW_WM_MAX_INSN arrays for every compile.
For an app that's blowing out the state cache, like sauerbraten, the
memset of the giant arrays ended up taking 11% of the CPU even when only a
"few" of the entries got used. With this, the WM program compile drops back
down to 1% of CPU time.
Bug #24981 (bisected to BRW_WM_MAX_INSN increase).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| cfa927766ab610a9a76730d337d77008d876ebbd |
|
19-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Share emit_fb_write() between brw_wm_emit.c and brw_wm_glsl.c
This should fix issues with antialiased lines in GLSL.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 2bc8bcdcd334db715f8916f80ef4f4bc5f9a170d |
|
04-Nov-2009 |
Eric Anholt <eric@anholt.net> |
i965: Remove an XXX comment for testing some code that seems to work.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| cb132406ded760a622513cd1ab86bf83bb945671 |
|
30-Oct-2009 |
Eric Anholt <eric@anholt.net> |
i965: Add an index assert on get_fp_inst array like other compiler arrays.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 7648c80ac8dd0631c5a0f86ad03347675a48eee6 |
|
29-Oct-2009 |
Brian Paul <brianp@vmware.com> |
i965: remove unused var
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 9ef33b86855c4d000271774030bd1b19b6d79687 |
|
29-Oct-2009 |
Brian Paul <brianp@vmware.com> |
i965: don't use context state in emit_fb_write()
Put the state that we care about in the hash key.
Issue spotted by Keith Whitwell.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| a8d233e509a2c1aada7cd4e83b126ba06cb90565 |
|
29-Oct-2009 |
Brian Paul <brianp@vmware.com> |
i965: use macros to get/set prog_instruction::Aux field
This makes things a bit easier to remember/understand.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| a0959bcee5df4272db40a56c468f8c7cc299d5ef |
|
29-Oct-2009 |
Brian Paul <brianp@vmware.com> |
i965: minor code reformatting
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 57d16c4cc37689710f951cb13981e2efc160cd23 |
|
11-Sep-2009 |
Eric Anholt <eric@anholt.net> |
i965: Move OPCODE_DDX/DDY to brw_wm_emit.c and make it actually work.
Previously, it was trying to mess around with the varying's
WM setup data to produce a result. Along with not actually working when
passed a varying, this wouldn't work if you did dFd[xy]() on a temporary.
Instead, just calculate the derivative using the neighbors in the subspan.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| b2b220e6225fdd673ea7b9fdda00e98423263fc3 |
|
26-Aug-2009 |
Brian Paul <brianp@vmware.com> |
i965: init the tex_units_used field
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 34da6024e3097684110cd1fd4da0f25adc415cd6 |
|
26-Aug-2009 |
Brian Paul <brianp@vmware.com> |
i965: keep track of which texture units the fragment shader accesses
We'll use this for debug/sanity checking.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| b7d2023cf99319c71a929c35478dff07d35df392 |
|
26-Aug-2009 |
Brian Paul <brianp@vmware.com> |
i965: add some texture unit/target assertions
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| f3b215cba2bca92d6582cc0c34702b73289f909c |
|
13-Aug-2009 |
Brian Paul <brianp@vmware.com> |
Merge branch 'new-frag-attribs'
This branch introduces new FRAG_ATTRIB_FACE and FRAG_ATTRIB_PNTC fragment
program inputs for GLSL gl_FrontFacing and gl_PointCoord. Before, these
attributes were packed with the FOG attribute. That made things
complicated elsewhere.
|
| d64649a316858a390bafe2aa619be3cf2c98ffde |
|
12-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Make the cube mapping RCP use a writemask.
Fixes cube mapping since the scalar changes.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 536476f2432168fb15ac06b52c953a594ad851ad |
|
12-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Handle scalar result swizzling in shared GLSL/non-GLSL code.
This is preparation for merging of brw_wm_glsl.c and
brw_wm_emit.c, and glsl.c doesn't swizzle channel results around.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 191e028de20b2f954621b652aa77b06d0e93652a |
|
04-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Fix RECT shadow sampling by not losing the other texcoords.
Bug #20821
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 9d0b8d72d8d704ff4d8e10448b60cbb42f07eecb |
|
30-Jul-2009 |
Brian Paul <brianp@vmware.com> |
mesa: add new FRAG_ATTRIB_FACE and FRAG_ATTRIB_PNTC fragment program inputs
Previously, the FOGC attribute contained the fragment fog coord, front/back-
face flag and the gl_PointCoord.xy values. Now each of those things are
separate fragment program attributes. This simplifies quite a few things in
Mesa and gallium.
Need to test i965 driver and fix up point coord handling in the gallium/draw
module...
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 8d482227915552c414e13743652e6794c4313ae2 |
|
17-Jun-2009 |
Brian Paul <brianp@vmware.com> |
Merge branch 'mesa_7_5_branch'
Conflicts:
src/mesa/main/api_validate.c
|
| 6b917d0b1787280f976c2f0d1ead0e5d7587a3e9 |
|
17-Jun-2009 |
Brian Paul <brianp@vmware.com> |
i965: fix bugs in projective texture coordinates
For the TXP instruction we check if the texcoord is really a 4-component
atttibute which requires the divide by W step. This check involved the
projtex_mask field. However, the projtex_mask field was being miscalculated
because of some confusion between vertex program outputs and fragment
program inputs.
1. Rework the size_masks calculation so we correctly set bits corresponding
to fragment program input attributes.
2. Rename projtex_mask to proj_attrib_mask since we're interested in more
than just texcoords (generic varying vars too).
3. Simply the indexing of the size_masks and proj_attrib_mask fields.
4. The tracker::active[] array was mis-dimensioned. Use MAX_PROGRAM_TEMPS
instead of a magic number.
5. Update comments, add new assertions.
With these changes the Lightsmark demo/benchmark renders correctly, until
we eventually hit a GPU lockup...
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 18af7c384cf663533f210d95d074c244d4214f29 |
|
13-Jun-2009 |
Brian Paul <brianp@vmware.com> |
i965: interpolate colors with perspective correction by default
...rather than with linear interpolation. Modern hardware should use
perspective-corrected interpolation for colors (as for texcoords).
glHint(GL_PERSPECTIVE_CORRECTION_HINT, mode) can be used to get
linear interpolation if mode = GL_FASTEST.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 7db7ff878d3e5a6b345228e6eaee4797bb68b360 |
|
15-Apr-2009 |
Brian Paul <brianp@vmware.com> |
mesa: merge the prog_src_register::NegateBase and NegateAbs fields
There's really no need for two negation fields. This came from the
GL_NV_fragment_program extension. The new, unified Negate bitfield applies
after the absolute value step.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 699db6d842c52d0b3b98b320f8ef1104a65fa783 |
|
24-Mar-2009 |
Eric Anholt <eric@anholt.net> |
i965: Fix glFrontFacing in twoside GLSL demo.
This also cuts instructions by just using the existing bit in the payload
rather than computing it from the determinant in the SF unit and passing it
as a varying down to the WM. Something still goes wrong with getting the
backface color right, but a simpler shader appears to get the right result.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 411d913ccea362dbd75411266d7abb685214ee93 |
|
24-Mar-2009 |
Eric Anholt <eric@anholt.net> |
i965: Fix fog coordinate g,b,a values when glFrontFacing isn't used.
Previously, we would sample (f,glFrontFacing,undef,undef) instead of the
(f,0,0,1) that fragment.fogcoord is supposed to return. Due to
glFrontFacing's presence in FOGC.y, we'll still give bad results there when
glFrontFacing is used.
Bug #19122, piglit testcase fp-fog.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| b013f945d8514ed827183a4cbfbc4dccc100704f |
|
24-Mar-2009 |
Eric Anholt <eric@anholt.net> |
i965: Clean up a bit of mess with unneeded variables in emit_interp.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 20f49252e1fe2e72bb620c26292f33d5315452a1 |
|
05-Mar-2009 |
Brian Paul <brianp@vmware.com> |
i965: init dest reg CondMask = COND_TR (the proper default)
Plus fix up a debug printf.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 8d475822e6e19fa79719c856a2db5b6a205db1b9 |
|
28-Feb-2009 |
Brian Paul <brianp@vmware.com> |
mesa: rename, reorder FRAG_RESULT_x tokens
s/FRAG_RESULT_DEPR/FRAG_RESULT_DEPTH/
s/FRAG_RESULT_COLR/FRAG_RESULT/COLOR/
Remove FRAG_RESULT_COLH (NV half-precision) output since we never used it.
Next, we might merge the COLOR and DATA outputs (COLOR0, COLOR1, etc).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| cdc63901df6af3b370935bd4997e3c9c4eb4b933 |
|
26-Feb-2009 |
root <root@i965.localnet.net> |
i965: rename draw_regions -> color_regions
Be a little more specific about what these are.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 8ae7e7749b708fc5a46180d3de2503ba7e2ab1f3 |
|
24-Feb-2009 |
Brian Paul <brianp@vmware.com> |
mesa: replace old prog_instruction::Sampler field with Aux field
The i965 driver needs an extra instruction field for color output information.
It was using the Sampler field for this. Use the Aux field instead. This
will probaby be revisited at some point...
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 9b78d9f65178648b1888f98153a2f738a281cb84 |
|
24-Feb-2009 |
Brian Paul <brianp@vmware.com> |
i965: whitespace/indentation fixes
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| e0d907308150b4863cc4f24543e70e14207e966a |
|
20-Feb-2009 |
Brian Paul <brianp@vmware.com> |
i965: use the new prog_instruction::TexShadow field
GLSL shadow() sampler calls are properly propogated down to the driver now.
The glean glsl1 shadow() tests work (except for the alpha channel).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| a79186e29efebed04c927d024b013435e7ff5725 |
|
20-Feb-2009 |
Brian Paul <brianp@vmware.com> |
i965: separate emit_op() and emit_tex_op() functions
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| c51c822ee02cb47ddba46da668577d51b7c02831 |
|
14-Feb-2009 |
Brian Paul <brianp@vmware.com> |
i965: rewrite the code for handling shader subroutine calls
Previously, the prog_instruction::Data field was used to map original Mesa
instructions to brw instructions in order to resolve subroutine calls. This
was a rather tangled mess. Plus it's an obstacle to implementing dynamic
allocation/growing of the instruction buffer (it's still a fixed size).
Mesa's GLSL compiler emits a label for each subroutine and CAL instruction.
Now we use those labels to patch the subroutine calls after code generation
has been done. We just keep a list of all CAL instructions that needs patching
and a list of all subroutine labels. It's a simple matter to resolve them.
This also consolidates some redundant post-emit code between brw_vs_emit.c and
brw_wm_glsl.c and removes some loops that cleared the prog_instruction::Data
fields at the end.
Plus, a bunch of new comments.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 2f78d4a2cd009d8d6a5f470d5738586b7f89f3d9 |
|
12-Feb-2009 |
Brian Paul <brianp@vmware.com> |
i965: code clean-ups, comments, and minor refactoring
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 3dcc48e6882385f58ec9b19a3a7d5307ef9fc976 |
|
28-Jan-2009 |
Brian Paul <brianp@vmware.com> |
i965: minor tweak: replace OPCODE_MOV with OPCODE_SWZ
Just to reinforce the understanding that an extended swizzle with 0 and 1
terms is possible there.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| c0d3b7679aa90e1a0dca2db152205efaec088b90 |
|
28-Jan-2009 |
Brian Paul <brianp@vmware.com> |
i965: implement GL_EXT_texture_swizzle
If the texture swizzle is not XYZW (no-op) add an extra MOV instruction
after the TEX instruction to rearrange the components.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 9e7903e492ad842481a166484e0474dd4f3100ba |
|
28-Jan-2009 |
Brian Paul <brianp@vmware.com> |
i965: minor clean-up, comments, etc.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| fc3971d80051b34836716579fd060dbb122d036b |
|
09-Jan-2009 |
Eric Anholt <eric@anholt.net> |
i965: Remove gratuitous whitespace in INTEL_DEBUG=wm output.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| de35989cdec9807c60b2b4389e5988037ce23d95 |
|
09-Jan-2009 |
Brian Paul <brianp@vmware.com> |
i965: fix broken ARB fp fog options
Just call _mesa_append_fog_code() if the fragment program's FogOption is
not GL_NONE.
This allows us to remove some unnecessary i965 fog code.
Note, the arbfplight.c demo can be used to test this (see DO_FRAGMENT_FOG).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| f68f94c2bc950405d4c91a1e5582a35ff4b15bdf |
|
08-Jan-2009 |
Brian Paul <brianp@vmware.com> |
i965: allow gl_FragData[0] usage when there's only one color buffer
If gl_FragData[0] is written but not gl_FragCOlor, use the former.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 95fa98d61a857448e690a0671b2e1e1d2873f0ec |
|
07-Jan-2009 |
Brian Paul <brianp@vmware.com> |
i965: init dst reg RelAddr field to zero
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 264cba6f70eacd9e04646104d10ba63c248d7b83 |
|
03-Dec-2008 |
Eric Anholt <eric@anholt.net> |
i965: Fix failure to upload new constant data when changing programs.
This is fallout from the ffvertex_prog.c work. It doesn't call
ProgramStringNotify, so we don't set param_state, so we wouldn't track when
VP parameters changed, and constants wouldn't get uploaded. Instead, remove
param_state entirely and just use the real value that we want to be tracking.
Fixes rendering in openarena since BRW_NEW_BATCH got disentangled from
BRW_NEW_INDICES.
Bug #18822.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| ecadb51bbcb972a79f3ed79e65a7986b9396e757 |
|
18-Sep-2008 |
Brian Paul <brian.paul@tungstengraphics.com> |
mesa: added "main/" prefix to includes, remove some -I paths from Makefile.template
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| c20a1736566d301f38cc1271284b1fde9adb2741 |
|
06-Aug-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: update TexSrcUnit for OPCODE_TXB
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| a3024caff1c790cf9f24476926aa62198f1e7b53 |
|
05-Aug-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: Use program->SamplerUnits[] to get the appropriate texture unit.
inst->TexSrcUnit is used as an index into program->SamplerUnits[] since
the commit ade508312c701ce89d3c2cd717994dbbabb4f207, and program->SamplerUnits
is a sampler-to-texture-unit mapping.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 28c28f72fd9ed192467a3cf913b344951d0bc805 |
|
08-Jun-2008 |
Roland Scheidegger <sroland@tungstengraphics.com> |
i965: fix OPCODE_TEX when additional ops are needed
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| b4cbf6983e0e6d6502c1260f60c463841ab74590 |
|
26-Mar-2008 |
Eric Anholt <eric@anholt.net> |
[965] Don't let the negate flags of src0 affect 1 constants in precalc_dst/lit
This patch is a variant of a submission by Michal Wajdeczko to fix
oglconform fpalu failures.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 7936c614abc165270852bc5e7e316747a9cacdfb |
|
21-Mar-2008 |
Zou Nan hai <nanhai.zou@intel.com> |
[i965] multiple rendering target fix
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 3105bc1d885ea8ce083d2be85cbeac46d4d873a1 |
|
17-Mar-2008 |
Andrzej Trznadel <Andrzej.Trznadel@intel.com> |
[965] Fix fp temp reg release code to not usually release all temps.
Also, use wrapped ffs() instead of native.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| fcb7cb9e72ecac7c165a3a6ed7a033e2e6793a26 |
|
13-Mar-2008 |
Zou Nan hai <nanhai.zou@intel.com> |
[i965] multiple rendering target support
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 7676980d38cff417015bca8d23549d567d74228b |
|
07-Mar-2008 |
Zou Nan hai <nanhai.zou@intel.com> |
[i965] fix fd.o bug #11471 and #11478
1. Follow EXT_texture_rectangle with YCbCr texture
2. swap UV component for MESA_FORMAT_YCBCR
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 7eca6be25f31cbbe5b72a70bf6b1e17c0e6df34d |
|
01-Feb-2008 |
Eric Anholt <eric@anholt.net> |
[965] Replace XXX comment about constant swizzle with an assert.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 6ef27b88e6f767cd476676b33cb7c4ea6922234e |
|
26-Oct-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
Merge branch '965-glsl'
Conflicts:
src/mesa/drivers/dri/i965/brw_sf.h
src/mesa/drivers/dri/i965/intel_context.c
|
| 175db68db59c6b917306adff98442d590df9af06 |
|
26-Sep-2007 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: The cube map texture coordinates must be devided by the
component with the largest absolute value before they are
delivered. fix bug #12421
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 88451b04e9cd39db9cc9315aaf69e074614f22f9 |
|
13-Aug-2007 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: fix projtex_mask
projtex_mask is only an 8bit field, and wm.input_size_masks includes
other attributes' information, therefore right shift is needed.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| c702a7100e2aa83241e89850a97bcc23e1c6fedb |
|
24-Jul-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
DDX DDY support, not very accurate
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| d19d0596daf004b56d80f78fa1a329b43c2ebf94 |
|
21-Jun-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
support branch and loop in pixel shader
most of the sample working with some small modification
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| d619cceea47dc3070ebb7f7ea4f8b6b31a672d38 |
|
26-Mar-2007 |
Brian <brian@yutani.localnet.net> |
merge of glsl-compiler-1 branch
|
| 01b7f2ab2e7a9291bf54475e816e88804ee7cd53 |
|
22-Mar-2007 |
Xiang, Haihao <haihao.xiang@intel.com> |
fix for bug#10339
StateFlags has been updated in _mesa_add_state_reference
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 064ae479a770bf434958d673baf6f7530f642697 |
|
23-Feb-2007 |
Brian <brian@yutani.localnet.net> |
Update DRI drivers for new glsl compiler.
Mostly:
- update #includes
- update STATE_* token code
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 0c6723aee564a7b320ca122c3c9b003c863cc714 |
|
16-Nov-2006 |
Brian Paul <brian.paul@tungstengraphics.com> |
Add a size parameter to _mesa_add_unnamed_constant() and
_mesa_add_named_constant() to indicate vector size (1, 2, 3 or 4).
Always 4 for now...
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| e7b0ec9ae79d4ec4aba402b9124fde55d914da92 |
|
05-Oct-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
Quieten debug message.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| e38114a5e4492684333251eb22bc60ee1038de55 |
|
20-Sep-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
Support ARB_texture_rectangle.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| cb54c056a6d46d03bfa0c4927f5ac8843feab8cd |
|
20-Sep-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
restore debug output after brw_wm_fp compilation stage
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 133f14168009393c5f396d218521625cb79b653f |
|
07-Sep-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
Make sure bmBufferOffset is called for all active buffers every time
we render. Currenly requires that some state be re-examined after
every LOCK_HARDWARE().
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|
| 9f344b3e7d6e23674dd4747faec253f103563b36 |
|
09-Aug-2006 |
Eric Anholt <anholt@FreeBSD.org> |
Add Intel i965G/Q DRI driver.
This driver comes from Tungsten Graphics, with a few further modifications by
Intel.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_fp.c
|