/external/llvm/lib/Target/Mips/ |
H A D | MipsISelDAGToDAG.h | 84 virtual bool selectVSplat(SDNode *N, APInt &Imm) const; 86 virtual bool selectVSplatUimm1(SDValue N, SDValue &Imm) const; 88 virtual bool selectVSplatUimm2(SDValue N, SDValue &Imm) const; 90 virtual bool selectVSplatUimm3(SDValue N, SDValue &Imm) const; 92 virtual bool selectVSplatUimm4(SDValue N, SDValue &Imm) const; 94 virtual bool selectVSplatUimm5(SDValue N, SDValue &Imm) const; 96 virtual bool selectVSplatUimm6(SDValue N, SDValue &Imm) const; 98 virtual bool selectVSplatUimm8(SDValue N, SDValue &Imm) const; 100 virtual bool selectVSplatSimm5(SDValue N, SDValue &Imm) const; 102 virtual bool selectVSplatUimmPow2(SDValue N, SDValue &Imm) cons 118 getImm(const SDNode *Node, uint64_t Imm) argument [all...] |
H A D | MipsAnalyzeImmediate.cpp | 29 void MipsAnalyzeImmediate::GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize, argument 31 GetInstSeqLs((Imm + 0x8000ULL) & 0xffffffffffff0000ULL, RemSize, SeqLs); 32 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL)); 35 void MipsAnalyzeImmediate::GetInstSeqLsORi(uint64_t Imm, unsigned RemSize, argument 37 GetInstSeqLs(Imm & 0xffffffffffff0000ULL, RemSize, SeqLs); 38 AddInstr(SeqLs, Inst(ORi, Imm & 0xffffULL)); 41 void MipsAnalyzeImmediate::GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize, argument 43 unsigned Shamt = countTrailingZeros(Imm); 44 GetInstSeqLs(Imm >> Shamt, RemSize - Shamt, SeqLs); 48 void MipsAnalyzeImmediate::GetInstSeqLs(uint64_t Imm, unsigne argument 125 Analyze(uint64_t Imm, unsigned Size, bool LastInstrIsADDiu) argument [all...] |
/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelDAGToDAG.h | 77 inline SDValue getI32Imm(unsigned Imm) { argument 78 return CurDAG->getTargetConstant(Imm, MVT::i32);
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ExpandPseudoInsts.cpp | 65 static uint64_t getChunk(uint64_t Imm, unsigned ChunkIdx) { argument 68 return (Imm >> (ChunkIdx * 16)) & 0xFFFF; 73 static uint64_t replicateChunk(uint64_t Imm, unsigned FromIdx, unsigned ToIdx) { argument 78 const uint64_t Chunk = getChunk(Imm, FromIdx) << ShiftAmt; 80 Imm &= ~(0xFFFFLL << ShiftAmt); 82 return Imm | Chunk; 245 static uint64_t updateImm(uint64_t Imm, unsigned Idx, bool Clear) { 250 Imm &= ~(Mask << (Idx * 16)); 253 Imm |= Mask << (Idx * 16); 255 return Imm; [all...] |
H A D | AArch64TargetTransformInfo.cpp | 77 unsigned getIntImmCost(const APInt &Imm, Type *Ty) const override; 78 unsigned getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, 80 unsigned getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, 158 unsigned AArch64TTI::getIntImmCost(const APInt &Imm, Type *Ty) const { argument 166 APInt ImmVal = Imm; 168 ImmVal = Imm.sext((BitSize + 63) & ~0x3fU); 183 const APInt &Imm, Type *Ty) const { 240 unsigned Cost = AArch64TTI::getIntImmCost(Imm, Ty); 244 return AArch64TTI::getIntImmCost(Imm, Ty); 248 const APInt &Imm, Typ 182 getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty) const argument 247 getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty) const argument [all...] |
/external/llvm/lib/Target/SystemZ/InstPrinter/ |
H A D | SystemZInstPrinter.cpp | 162 uint64_t Imm = MI->getOperand(OpNum).getImm(); local 163 assert(Imm > 0 && Imm < 15 && "Invalid condition"); 164 O << CondNames[Imm - 1];
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/external/llvm/lib/Target/NVPTX/InstPrinter/ |
H A D | NVPTXInstPrinter.cpp | 99 int64_t Imm = MO.getImm(); local 103 if (Imm & NVPTX::PTXCvtMode::FTZ_FLAG) 107 if (Imm & NVPTX::PTXCvtMode::SAT_FLAG) 111 switch (Imm & NVPTX::PTXCvtMode::BASE_MASK) { 149 int64_t Imm = MO.getImm(); local 153 if (Imm & NVPTX::PTXCmpMode::FTZ_FLAG) 156 switch (Imm & NVPTX::PTXCmpMode::BASE_MASK) { 223 int Imm = (int) MO.getImm(); local 225 if (Imm) 228 switch (Imm) { [all...] |
/external/llvm/lib/Target/R600/MCTargetDesc/ |
H A D | SIMCCodeEmitter.cpp | 88 IntFloatUnion Imm; local 90 Imm.I = MO.getImm(); 92 Imm.F = MO.getFPImm(); 96 if (Imm.I >= 0 && Imm.I <= 64) 97 return 128 + Imm.I; 99 if (Imm.I >= -16 && Imm.I <= -1) 100 return 192 + abs(Imm.I); 102 if (Imm 157 IntFloatUnion Imm; local [all...] |
/external/llvm/lib/Target/X86/InstPrinter/ |
H A D | X86ATTInstPrinter.cpp | 65 int64_t Imm = MI->getOperand(Op).getImm() & 0xf; local 66 switch (Imm) { 89 int64_t Imm = MI->getOperand(Op).getImm() & 0x1f; local 90 switch (Imm) { 129 int64_t Imm = MI->getOperand(Op).getImm() & 0x3; local 130 switch (Imm) {
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H A D | X86IntelInstPrinter.cpp | 55 int64_t Imm = MI->getOperand(Op).getImm() & 0xf; local 56 switch (Imm) { 79 int64_t Imm = MI->getOperand(Op).getImm() & 0x1f; local 80 switch (Imm) { 119 int64_t Imm = MI->getOperand(Op).getImm() & 0x3; local 120 switch (Imm) {
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/external/llvm/lib/Target/X86/Utils/ |
H A D | X86ShuffleDecode.cpp | 24 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { argument 32 unsigned ZMask = Imm & 15; 33 unsigned CountD = (Imm >> 4) & 3; 34 unsigned CountS = (Imm >> 6) & 3; 65 void DecodePALIGNRMask(MVT VT, unsigned Imm, argument 68 unsigned Offset = Imm * (VT.getVectorElementType().getSizeInBits() / 8); 86 void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { argument 92 unsigned NewImm = Imm; 98 if (NumLaneElts == 4) NewImm = Imm; // reload imm 102 void DecodePSHUFHWMask(MVT VT, unsigned Imm, argument 118 DecodePSHUFLWMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument 137 DecodeSHUFPMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument 196 DecodeVPERM2X128Mask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument 212 DecodeVPERMMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86FrameLowering.cpp | 59 static unsigned getSUBriOpcode(unsigned IsLP64, int64_t Imm) { argument 61 if (isInt<8>(Imm)) 65 if (isInt<8>(Imm)) 71 static unsigned getADDriOpcode(unsigned IsLP64, int64_t Imm) { argument 73 if (isInt<8>(Imm)) 77 if (isInt<8>(Imm))
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H A D | X86RegisterInfo.cpp | 515 int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm()); local 516 int Offset = FIOffset + Imm; 517 assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | AMDILISelDAGToDAG.cpp | 48 inline SDValue getSmallIPtrImm(unsigned Imm); 96 SDValue AMDGPUDAGToDAGISel::getSmallIPtrImm(unsigned int Imm) { argument 97 return CurDAG->getTargetConstant(Imm, MVT::i32);
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/ |
H A D | SIMCCodeEmitter.cpp | 245 } Imm; local 248 Imm.f = MO.getFPImm(); 249 Value |= ((uint64_t)Imm.i) << 32;
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/external/llvm/lib/CodeGen/ |
H A D | StackMaps.cpp | 90 int64_t Imm = (++MOI)->getImm(); local 91 Locs.push_back(Location(StackMaps::Location::Direct, Size, Reg, Imm)); 98 int64_t Imm = (++MOI)->getImm(); local 99 Locs.push_back(Location(StackMaps::Location::Indirect, Size, Reg, Imm)); 105 int64_t Imm = MOI->getImm(); local 106 Locs.push_back(Location(Location::Constant, sizeof(int64_t), 0, Imm));
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/external/llvm/lib/Target/ARM/ |
H A D | ARMTargetTransformInfo.cpp | 77 unsigned getIntImmCost(const APInt &Imm, Type *Ty) const override; 151 unsigned ARMTTI::getIntImmCost(const APInt &Imm, Type *Ty) const { argument 158 int32_t SImmVal = Imm.getSExtValue(); 159 uint32_t ZImmVal = Imm.getZExtValue();
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H A D | Thumb1RegisterInfo.cpp | 235 // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7) 301 unsigned DestReg, int Imm, 305 bool isSub = Imm < 0; 306 if (isSub) Imm = -Imm; 309 int ThisVal = (Imm > Chunk) ? Chunk : Imm; 310 Imm -= ThisVal; 314 if (Imm > 0) 315 emitThumbRegPlusImmediate(MBB, MBBI, dl, DestReg, DestReg, Imm, TI 299 emitThumbConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, unsigned DestReg, int Imm, const TargetInstrInfo &TII, const Thumb1RegisterInfo& MRI, DebugLoc dl) argument [all...] |
/external/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMAddressingModes.h | 112 static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { 113 return ShOp | (Imm << 3); 124 static inline unsigned getSOImmValImm(unsigned Imm) { 125 return Imm & 0xFF; 129 static inline unsigned getSOImmValRot(unsigned Imm) { 130 return (Imm >> 8) * 2; 133 /// getSOImmValRotate - Try to handle Imm with an immediate shifter operand, 137 static inline unsigned getSOImmValRotate(unsigned Imm) { argument 140 if ((Imm & ~255U) == 0) return 0; 143 unsigned TZ = countTrailingZeros(Imm); 218 getThumbImmValShift(unsigned Imm) argument 237 getThumbImm16ValShift(unsigned Imm) argument 271 unsigned u, Vs, Imm; local 335 isT2SOImmTwoPartVal(unsigned Imm) argument 362 getT2SOImmTwoPartFirst(unsigned Imm) argument 379 getT2SOImmTwoPartSecond(unsigned Imm) argument [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCTargetTransformInfo.cpp | 75 unsigned getIntImmCost(const APInt &Imm, Type *Ty) const override; 77 unsigned getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, 79 unsigned getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, 138 unsigned PPCTTI::getIntImmCost(const APInt &Imm, Type *Ty) const { argument 140 return TargetTransformInfo::getIntImmCost(Imm, Ty); 148 if (Imm == 0) 151 if (Imm.getBitWidth() <= 64) { 152 if (isInt<16>(Imm.getSExtValue())) 155 if (isInt<32>(Imm.getSExtValue())) { 157 if ((Imm 167 getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty) const argument 191 getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty) const argument [all...] |
/external/llvm/lib/Target/R600/InstPrinter/ |
H A D | AMDGPUInstPrinter.cpp | 113 void AMDGPUInstPrinter::printImmediate(uint32_t Imm, raw_ostream &O) { argument 114 int32_t SImm = static_cast<int32_t>(Imm); 120 if (Imm == FloatToBits(1.0f) || 121 Imm == FloatToBits(-1.0f) || 122 Imm == FloatToBits(0.5f) || 123 Imm == FloatToBits(-0.5f) || 124 Imm == FloatToBits(2.0f) || 125 Imm == FloatToBits(-2.0f) || 126 Imm == FloatToBits(4.0f) || 127 Imm 175 unsigned Imm = MI->getOperand(OpNum).getImm(); local 219 int32_t Imm = MI->getOperand(OpNo).getImm(); local [all...] |
/external/llvm/lib/Target/XCore/ |
H A D | XCoreISelDAGToDAG.cpp | 52 inline SDValue getI32Imm(unsigned Imm) { argument 53 return CurDAG->getTargetConstant(Imm, MVT::i32);
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/external/llvm/utils/TableGen/ |
H A D | PseudoLoweringEmitter.cpp | 28 enum MapKind { Operand, Imm, Reg }; enumerator in enum:__anon26603::PseudoLoweringEmitter::OpData::MapKind 32 uint64_t Imm; // Integer immedate value. member in union:__anon26603::PseudoLoweringEmitter::OpData::__anon26604 105 OperandMap[BaseIdx + i].Kind = OpData::Imm; 106 OperandMap[BaseIdx + i].Data.Imm = II->getValue(); 234 case OpData::Imm: 236 << Expansion.OperandMap[MIOpNo + i].Data.Imm << "));\n";
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/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDILISelDAGToDAG.cpp | 48 inline SDValue getSmallIPtrImm(unsigned Imm); 96 SDValue AMDGPUDAGToDAGISel::getSmallIPtrImm(unsigned int Imm) { argument 97 return CurDAG->getTargetConstant(Imm, MVT::i32);
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/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
H A D | SIMCCodeEmitter.cpp | 245 } Imm; local 248 Imm.f = MO.getFPImm(); 249 Value |= ((uint64_t)Imm.i) << 32;
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