| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonFrameLowering.cpp | 215 unsigned SuperReg = *SRI; local
218 return SuperReg;
247 unsigned SuperReg = uniqueSuperReg(Reg, TRI); local
253 SuperRegClass = TRI->getMinimalPhysRegClass(SuperReg);
254 CanUseDblStore = (SuperRegNext == SuperReg);
259 TII.storeRegToStackSlot(MBB, MI, SuperReg, true,
261 MBB.addLiveIn(SuperReg);
302 unsigned SuperReg = uniqueSuperReg(Reg, TRI); local
307 SuperRegClass = TRI->getMinimalPhysRegClass(SuperReg);
308 CanUseDblLoad = (SuperRegNext == SuperReg);
[all...] |
| /external/llvm/lib/CodeGen/ |
| H A D | ScheduleDAGInstrs.cpp | 1090 const unsigned SuperReg = MO.getReg(); local
1092 for (MCSubRegIterator SubRegs(SuperReg, TRI); SubRegs.isValid(); ++SubRegs) {
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| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 1005 SDValue SuperReg = SDValue(Ld, 0); local
1008 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg));
1036 SDValue SuperReg = SDValue(Ld, 1); local
1038 ReplaceUses(SDValue(N, 0), SuperReg); local
1042 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg));
1152 SDValue SuperReg = SDValue(Ld, 0); local
1158 SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT, SuperReg);
1204 SDValue SuperReg = SDValue(Ld, 1); local
1207 Narrow ? NarrowVector(SuperReg, *CurDAG) : SuperReg);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 698 unsigned SuperReg = local
701 if (VSXSelfCopyCrash && SrcReg == SuperReg)
704 DestReg = SuperReg;
707 unsigned SuperReg = local
710 if (VSXSelfCopyCrash && SrcReg == SuperReg)
713 DestReg = SuperReg;
716 unsigned SuperReg = local
719 if (VSXSelfCopyCrash && DestReg == SuperReg)
722 SrcReg = SuperReg;
725 unsigned SuperReg local
[all...] |
| /external/llvm/lib/Target/R600/ |
| H A D | SIISelLowering.cpp | 470 unsigned SuperReg = MI->getOperand(0).getReg(); local
486 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SuperReg)
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| H A D | SIInstrInfo.cpp | 780 MachineOperand &SuperReg,
785 assert(SuperReg.isReg());
796 .addOperand(SuperReg);
778 buildExtractSubReg(MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const argument
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1891 SDValue SuperReg = SDValue(VLd, 0);
1897 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
2124 SDValue SuperReg; local
2129 SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0);
2131 SuperReg = SDValue(createQRegPairNode(MVT::v4i64, V0, V1), 0);
2138 SuperReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
2140 SuperReg = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);
2142 Ops.push_back(SuperReg);
2156 SuperReg = SDValue(VLdLn, 0);
2162 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
2211 SDValue SuperReg; local
[all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 5556 unsigned SuperReg = MRI->getMatchingSuperReg( local
5559 assert(SuperReg && "expected register pair");
5561 unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1);
|