Searched refs:CPU (Results 51 - 75 of 352) sorted by relevance

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/external/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCTargetDesc.h47 StringRef CPU);
50 StringRef CPU);
53 StringRef CPU);
56 StringRef CPU);
/external/llvm/lib/Target/PowerPC/
H A DPPCTargetStreamer.h21 virtual void emitMachine(StringRef CPU) = 0;
/external/llvm/test/MC/Mips/mips1/
H A Dinvalid-mips32.s9 sync 0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
/external/llvm/test/MC/Mips/mips3/
H A Dinvalid-mips32.s9 sync 0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
/external/llvm/test/MC/Mips/mips32/
H A Dinvalid-mips64.s8 dclo $s2,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 dclz $s0,$t9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
/external/llvm/test/MC/Mips/mips32r2/
H A Dinvalid-mips64r2.s8 dsbh $v1,$t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
/external/llvm/test/MC/Mips/mips32r6/
H A Dinvalid-mips5.s8 luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 suxc1 $f12,$k1($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
/external/llvm/test/MC/Mips/mips4/
H A Dinvalid-mips32.s9 sync 0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
H A Dinvalid-mips5.s8 luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 suxc1 $f12,$k1($t1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
/external/llvm/test/MC/Mips/mips5/
H A Dinvalid-mips32.s9 sync 0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
/external/mesa3d/src/gallium/drivers/radeon/
H A DAMDGPUSubtarget.cpp23 AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS) : argument
24 AMDGPUGenSubtargetInfo(TT, CPU, FS), mDumpCode(false) {
25 InstrItins = getInstrItineraryForCPU(CPU);
30 StringRef GPU = CPU;
H A DAMDGPUSubtarget.h43 AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS);
47 virtual void ParseSubtargetFeatures(llvm::StringRef CPU, llvm::StringRef FS);
/external/qemu/target-arm/
H A Dcpu-qom.h18 #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e))
H A Dqom-cpu.h18 #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e))
/external/qemu/target-i386/
H A Dcpu-qom.h18 #define ENV_GET_CPU(e) CPU(x86_env_get_cpu(e))
/external/qemu/target-mips/
H A Dcpu-qom.h19 #define ENV_GET_CPU(e) CPU(mips_env_get_cpu(e))
/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.h40 std::string ParseARMTriple(StringRef TT, StringRef CPU);
45 MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
67 StringRef TT, StringRef CPU,
71 StringRef TT, StringRef CPU);
74 StringRef TT, StringRef CPU);
77 StringRef TT, StringRef CPU);
80 StringRef TT, StringRef CPU);
/external/llvm/include/llvm/MC/
H A DMCSubtargetInfo.h44 uint64_t FeatureBits; // Feature bits for current CPU + FS
47 void InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS,
68 /// InitMCProcessorInfo - Set or change the CPU (optionally supplemented with
70 void InitMCProcessorInfo(StringRef CPU, StringRef FS);
72 /// InitCPUSchedModel - Recompute scheduling model based on CPU.
73 void InitCPUSchedModel(StringRef CPU);
83 /// getSchedModelForCPU - Get the machine model of a CPU.
85 const MCSchedModel *getSchedModelForCPU(StringRef CPU) const;
87 /// getSchedModel - Get the machine model for this subtarget's CPU.
129 /// getInstrItineraryForCPU - Get scheduling itinerary of a CPU
[all...]
/external/llvm/lib/Target/ARM/
H A DARMTargetMachine.cpp49 StringRef CPU, StringRef FS,
53 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
54 Subtarget(TT, CPU, FS, *this, isLittle, Options) {
73 ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT, StringRef CPU, argument
77 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle) {
80 report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
87 StringRef CPU, StringRef FS,
91 : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
96 StringRef CPU, StringRef FS,
100 : ARMTargetMachine(T, TT, CPU, F
48 ARMBaseTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle) argument
86 ARMLETargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
95 ARMBETargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
104 ThumbTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle) argument
116 ThumbLETargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
125 ThumbBETargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
[all...]
/external/chromium_org/base/
H A Dcpu_unittest.cc10 // Tests whether we can run extended instructions represented by the CPU
12 // MMX, SSE, etc.) supported by the CPU and sees we can run them without
15 TEST(CPU, RunExtendedInstructions) {
17 // Retrieve the CPU information.
18 base::CPU cpu;
/external/chromium_org/third_party/WebKit/Source/wtf/
H A DBitwiseOperations.h40 #include "wtf/CPU.h"
59 #if CPU(64BIT)
89 #if CPU(64BIT)
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DAMDGPUSubtarget.h43 AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS);
47 virtual void ParseSubtargetFeatures(llvm::StringRef CPU, llvm::StringRef FS);
/external/chromium_org/v8/src/base/
H A Dcpu-unittest.cc12 CPU cpu;
28 CPU cpu;
/external/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.h43 StringRef CPU);
46 StringRef CPU);
/external/llvm/lib/Target/XCore/
H A DXCoreSubtarget.h44 XCoreSubtarget(const std::string &TT, const std::string &CPU,
49 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);

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