Searched refs:brw (Results 26 - 50 of 188) sorted by relevance

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/external/mesa3d/src/mesa/drivers/dri/i965/
H A Dbrw_state_dump.c35 batch_out(struct brw_context *brw, const char *name, uint32_t offset,
39 batch_out(struct brw_context *brw, const char *name, uint32_t offset, argument
42 struct intel_context *intel = &brw->intel;
80 static void dump_vs_state(struct brw_context *brw, uint32_t offset) argument
82 struct intel_context *intel = &brw->intel;
86 batch_out(brw, name, offset, 0, "thread0\n");
87 batch_out(brw, name, offset, 1, "thread1\n");
88 batch_out(brw, name, offset, 2, "thread2\n");
89 batch_out(brw, name, offset, 3, "thread3\n");
90 batch_out(brw, nam
96 dump_gs_state(struct brw_context *brw, uint32_t offset) argument
112 dump_clip_state(struct brw_context *brw, uint32_t offset) argument
132 dump_sf_state(struct brw_context *brw, uint32_t offset) argument
149 dump_wm_state(struct brw_context *brw, uint32_t offset) argument
177 dump_surface_state(struct brw_context *brw, uint32_t offset) argument
201 dump_gen7_surface_state(struct brw_context *brw, uint32_t offset) argument
221 dump_sdc(struct brw_context *brw, uint32_t offset) argument
251 dump_sampler_state(struct brw_context *brw, uint32_t offset, uint32_t size) argument
274 dump_gen7_sampler_state(struct brw_context *brw, uint32_t offset, uint32_t size) argument
298 dump_sf_viewport_state(struct brw_context *brw, uint32_t offset) argument
320 dump_clip_viewport_state(struct brw_context *brw, uint32_t offset) argument
335 dump_sf_clip_viewport_state(struct brw_context *brw, uint32_t offset) argument
357 dump_cc_viewport_state(struct brw_context *brw, uint32_t offset) argument
366 dump_depth_stencil_state(struct brw_context *brw, uint32_t offset) argument
386 dump_cc_state_gen4(struct brw_context *brw, uint32_t offset) argument
400 dump_cc_state_gen6(struct brw_context *brw, uint32_t offset) argument
419 dump_blend_state(struct brw_context *brw, uint32_t offset) argument
428 dump_scissor(struct brw_context *brw, uint32_t offset) argument
441 dump_vs_constants(struct brw_context *brw, uint32_t offset, uint32_t size) argument
458 dump_wm_constants(struct brw_context *brw, uint32_t offset, uint32_t size) argument
474 dump_binding_table(struct brw_context *brw, uint32_t offset, uint32_t size) argument
491 dump_prog_cache(struct brw_context *brw) argument
545 dump_state_batch(struct brw_context *brw) argument
642 struct brw_context *brw = brw_context(&intel->ctx); local
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H A Dbrw_state_batch.c38 brw_track_state_batch(struct brw_context *brw, argument
43 struct intel_batchbuffer *batch = &brw->intel.batch;
45 if (!brw->state_batch_list) {
49 brw->state_batch_list = ralloc_size(brw, sizeof(*brw->state_batch_list) *
53 brw->state_batch_list[brw->state_batch_count].offset = offset;
54 brw->state_batch_list[brw
84 struct brw_context *brw = brw_context(&intel->ctx); local
120 brw_state_batch(struct brw_context *brw, enum state_struct_type type, int size, int alignment, uint32_t *out_offset) argument
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H A Dgen6_sol.c36 gen6_update_sol_surfaces(struct brw_context *brw) argument
38 struct gl_context *ctx = &brw->intel.ctx;
58 brw, xfb_obj->Buffers[buffer], &brw->gs.surf_offset[surf_index],
62 brw->gs.surf_offset[surf_index] = 0;
66 brw->state.dirty.brw |= BRW_NEW_SURFACES;
72 .brw = (BRW_NEW_BATCH |
84 brw_gs_upload_binding_table(struct brw_context *brw) argument
86 struct gl_context *ctx = &brw
134 gen6_update_sol_indices(struct brw_context *brw) argument
160 struct brw_context *brw = brw_context(ctx); local
203 struct brw_context *brw = brw_context(ctx); local
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H A Dgen7_vs_state.c33 upload_vs_state(struct brw_context *brw) argument
35 struct intel_context *intel = &brw->intel;
37 const int max_threads_shift = brw->intel.is_haswell ?
45 OUT_BATCH(brw->vs.bind_bo_offset);
51 OUT_BATCH(brw->sampler.offset);
54 if (brw->vs.push_const_size == 0) {
68 OUT_BATCH(brw->vs.push_const_size);
73 OUT_BATCH(brw->vs.push_const_offset);
88 OUT_BATCH(brw->vs.prog_offset);
90 ((ALIGN(brw
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H A Dgen6_vs_state.c37 gen6_upload_vs_push_constants(struct brw_context *brw) argument
39 struct intel_context *intel = &brw->intel;
43 brw_vertex_program_const(brw->vertex_program);
44 unsigned int nr_params = brw->vs.prog_data->nr_params / 4;
47 if (brw->vertex_program->IsNVProgram)
57 if (brw->vs.prog_data->nr_params == 0 && !ctx->Transform.ClipPlanesEnabled) {
58 brw->vs.push_const_size = 0;
64 param = brw_state_batch(brw, AUB_TRACE_VS_CONSTANTS,
67 32, &brw->vs.push_const_offset);
69 if (brw
131 upload_vs_state(struct brw_context *brw) argument
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H A Dgen7_wm_state.c35 upload_wm_state(struct brw_context *brw) argument
37 struct intel_context *intel = &brw->intel;
40 brw_fragment_program_const(brw->fragment_program);
68 dw1 |= brw->wm.prog_data->barycentric_interp_modes <<
77 if (brw_color_buffer_write_enabled(brw) || writes_depth ||
105 .brw = (BRW_NEW_FRAGMENT_PROGRAM |
113 upload_ps_state(struct brw_context *brw) argument
115 struct intel_context *intel = &brw->intel;
118 const int max_threads_shift = brw->intel.is_haswell ?
124 OUT_BATCH(brw
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H A Dbrw_tex.c46 void brw_validate_textures( struct brw_context *brw )
48 struct gl_context *ctx = &brw->intel.ctx;
49 struct intel_context *intel = &brw->intel;
H A Dbrw_clip_state.c37 brw_upload_clip_unit(struct brw_context *brw) argument
39 struct intel_context *intel = &brw->intel;
43 clip = brw_state_batch(brw, AUB_TRACE_CLIP_STATE,
44 sizeof(*clip), 32, &brw->clip.state_offset);
48 clip->thread0.grf_reg_count = (ALIGN(brw->clip.prog_data->total_grf, 16) /
51 brw_program_reloc(brw,
52 brw->clip.state_offset +
54 brw->clip.prog_offset +
60 clip->thread3.urb_entry_read_length = brw->clip.prog_data->urb_read_length;
62 brw
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H A Dbrw_gs.c47 static void compile_gs_prog( struct brw_context *brw, argument
50 struct intel_context *intel = &brw->intel;
59 c.vue_map = brw->vs.prog_data->vue_map;
66 brw_init_compile(brw, &c.func, mem_ctx);
145 brw_upload_cache(&brw->cache, BRW_GS_PROG,
149 &brw->gs.prog_offset, &brw->gs.prog_data);
153 static void populate_key( struct brw_context *brw, argument
163 struct gl_context *ctx = &brw->intel.ctx;
164 struct intel_context *intel = &brw
239 brw_upload_gs_prog(struct brw_context *brw) argument
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H A Dbrw_wm_state.c45 brw_color_buffer_write_enabled(struct brw_context *brw) argument
47 struct gl_context *ctx = &brw->intel.ctx;
48 const struct gl_fragment_program *fp = brw->fragment_program;
74 brw_upload_wm_unit(struct brw_context *brw) argument
76 struct intel_context *intel = &brw->intel;
78 const struct gl_fragment_program *fp = brw->fragment_program;
81 wm = brw_state_batch(brw, AUB_TRACE_WM_STATE,
82 sizeof(*wm), 32, &brw->wm.state_offset);
85 if (brw->wm.prog_data->prog_offset_16) {
90 assert(brw
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H A Dgen6_viewport_state.c43 gen6_upload_clip_vp(struct brw_context *brw) argument
47 vp = brw_state_batch(brw, AUB_TRACE_CLIP_VP_STATE,
48 sizeof(*vp), 32, &brw->clip.vp_offset);
55 brw->state.dirty.cache |= CACHE_NEW_CLIP_VP;
61 .brw = BRW_NEW_BATCH,
68 gen6_upload_sf_vp(struct brw_context *brw) argument
70 struct gl_context *ctx = &brw->intel.ctx;
77 sfv = brw_state_batch(brw, AUB_TRACE_SF_VP_STATE,
78 sizeof(*sfv), 32, &brw->sf.vp_offset);
98 brw
110 upload_viewport_state_pointers(struct brw_context *brw) argument
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H A Dbrw_primitive_restart.c81 struct brw_context *brw = brw_context(ctx); local
83 if (brw->sol.counting_primitives_generated ||
84 brw->sol.counting_primitives_written) {
135 struct brw_context *brw = brw_context(ctx); local
153 if (brw->prim_restart.in_progress) {
167 brw->prim_restart.in_progress = true;
172 brw->prim_restart.enable_cut_index = true;
174 brw->prim_restart.enable_cut_index = false;
182 brw->prim_restart.in_progress = false;
189 haswell_upload_cut_index(struct brw_context *brw) argument
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H A Dgen7_viewport_state.c31 gen7_upload_sf_clip_viewport(struct brw_context *brw) argument
33 struct intel_context *intel = &brw->intel;
41 vp = brw_state_batch(brw, AUB_TRACE_SF_VP_STATE,
42 sizeof(*vp), 64, &brw->sf.vp_offset);
44 brw->clip.vp_offset = brw->sf.vp_offset;
71 OUT_BATCH(brw->sf.vp_offset);
78 .brw = BRW_NEW_BATCH,
86 static void upload_cc_viewport_state_pointer(struct brw_context *brw) argument
88 struct intel_context *intel = &brw
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/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/
H A Dbrw_state_batch.c38 brw_track_state_batch(struct brw_context *brw, argument
43 struct intel_batchbuffer *batch = &brw->intel.batch;
45 if (!brw->state_batch_list) {
49 brw->state_batch_list = ralloc_size(brw, sizeof(*brw->state_batch_list) *
53 brw->state_batch_list[brw->state_batch_count].offset = offset;
54 brw->state_batch_list[brw
84 struct brw_context *brw = brw_context(&intel->ctx); local
120 brw_state_batch(struct brw_context *brw, enum state_struct_type type, int size, int alignment, uint32_t *out_offset) argument
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H A Dgen6_sol.c36 gen6_update_sol_surfaces(struct brw_context *brw) argument
38 struct gl_context *ctx = &brw->intel.ctx;
58 brw, xfb_obj->Buffers[buffer], &brw->gs.surf_offset[surf_index],
62 brw->gs.surf_offset[surf_index] = 0;
66 brw->state.dirty.brw |= BRW_NEW_SURFACES;
72 .brw = (BRW_NEW_BATCH |
84 brw_gs_upload_binding_table(struct brw_context *brw) argument
86 struct gl_context *ctx = &brw
134 gen6_update_sol_indices(struct brw_context *brw) argument
160 struct brw_context *brw = brw_context(ctx); local
203 struct brw_context *brw = brw_context(ctx); local
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H A Dgen7_vs_state.c33 upload_vs_state(struct brw_context *brw) argument
35 struct intel_context *intel = &brw->intel;
37 const int max_threads_shift = brw->intel.is_haswell ?
45 OUT_BATCH(brw->vs.bind_bo_offset);
51 OUT_BATCH(brw->sampler.offset);
54 if (brw->vs.push_const_size == 0) {
68 OUT_BATCH(brw->vs.push_const_size);
73 OUT_BATCH(brw->vs.push_const_offset);
88 OUT_BATCH(brw->vs.prog_offset);
90 ((ALIGN(brw
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H A Dgen6_vs_state.c37 gen6_upload_vs_push_constants(struct brw_context *brw) argument
39 struct intel_context *intel = &brw->intel;
43 brw_vertex_program_const(brw->vertex_program);
44 unsigned int nr_params = brw->vs.prog_data->nr_params / 4;
47 if (brw->vertex_program->IsNVProgram)
57 if (brw->vs.prog_data->nr_params == 0 && !ctx->Transform.ClipPlanesEnabled) {
58 brw->vs.push_const_size = 0;
64 param = brw_state_batch(brw, AUB_TRACE_VS_CONSTANTS,
67 32, &brw->vs.push_const_offset);
69 if (brw
131 upload_vs_state(struct brw_context *brw) argument
[all...]
H A Dgen7_wm_state.c35 upload_wm_state(struct brw_context *brw) argument
37 struct intel_context *intel = &brw->intel;
40 brw_fragment_program_const(brw->fragment_program);
68 dw1 |= brw->wm.prog_data->barycentric_interp_modes <<
77 if (brw_color_buffer_write_enabled(brw) || writes_depth ||
105 .brw = (BRW_NEW_FRAGMENT_PROGRAM |
113 upload_ps_state(struct brw_context *brw) argument
115 struct intel_context *intel = &brw->intel;
118 const int max_threads_shift = brw->intel.is_haswell ?
124 OUT_BATCH(brw
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H A Dbrw_tex.c46 void brw_validate_textures( struct brw_context *brw )
48 struct gl_context *ctx = &brw->intel.ctx;
49 struct intel_context *intel = &brw->intel;
H A Dbrw_clip_state.c37 brw_upload_clip_unit(struct brw_context *brw) argument
39 struct intel_context *intel = &brw->intel;
43 clip = brw_state_batch(brw, AUB_TRACE_CLIP_STATE,
44 sizeof(*clip), 32, &brw->clip.state_offset);
48 clip->thread0.grf_reg_count = (ALIGN(brw->clip.prog_data->total_grf, 16) /
51 brw_program_reloc(brw,
52 brw->clip.state_offset +
54 brw->clip.prog_offset +
60 clip->thread3.urb_entry_read_length = brw->clip.prog_data->urb_read_length;
62 brw
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H A Dbrw_gs.c47 static void compile_gs_prog( struct brw_context *brw, argument
50 struct intel_context *intel = &brw->intel;
59 c.vue_map = brw->vs.prog_data->vue_map;
66 brw_init_compile(brw, &c.func, mem_ctx);
145 brw_upload_cache(&brw->cache, BRW_GS_PROG,
149 &brw->gs.prog_offset, &brw->gs.prog_data);
153 static void populate_key( struct brw_context *brw, argument
163 struct gl_context *ctx = &brw->intel.ctx;
164 struct intel_context *intel = &brw
239 brw_upload_gs_prog(struct brw_context *brw) argument
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H A Dbrw_wm_state.c45 brw_color_buffer_write_enabled(struct brw_context *brw) argument
47 struct gl_context *ctx = &brw->intel.ctx;
48 const struct gl_fragment_program *fp = brw->fragment_program;
74 brw_upload_wm_unit(struct brw_context *brw) argument
76 struct intel_context *intel = &brw->intel;
78 const struct gl_fragment_program *fp = brw->fragment_program;
81 wm = brw_state_batch(brw, AUB_TRACE_WM_STATE,
82 sizeof(*wm), 32, &brw->wm.state_offset);
85 if (brw->wm.prog_data->prog_offset_16) {
90 assert(brw
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H A Dgen6_viewport_state.c43 gen6_upload_clip_vp(struct brw_context *brw) argument
47 vp = brw_state_batch(brw, AUB_TRACE_CLIP_VP_STATE,
48 sizeof(*vp), 32, &brw->clip.vp_offset);
55 brw->state.dirty.cache |= CACHE_NEW_CLIP_VP;
61 .brw = BRW_NEW_BATCH,
68 gen6_upload_sf_vp(struct brw_context *brw) argument
70 struct gl_context *ctx = &brw->intel.ctx;
77 sfv = brw_state_batch(brw, AUB_TRACE_SF_VP_STATE,
78 sizeof(*sfv), 32, &brw->sf.vp_offset);
98 brw
110 upload_viewport_state_pointers(struct brw_context *brw) argument
[all...]
H A Dbrw_primitive_restart.c81 struct brw_context *brw = brw_context(ctx); local
83 if (brw->sol.counting_primitives_generated ||
84 brw->sol.counting_primitives_written) {
135 struct brw_context *brw = brw_context(ctx); local
153 if (brw->prim_restart.in_progress) {
167 brw->prim_restart.in_progress = true;
172 brw->prim_restart.enable_cut_index = true;
174 brw->prim_restart.enable_cut_index = false;
182 brw->prim_restart.in_progress = false;
189 haswell_upload_cut_index(struct brw_context *brw) argument
[all...]
H A Dgen7_viewport_state.c31 gen7_upload_sf_clip_viewport(struct brw_context *brw) argument
33 struct intel_context *intel = &brw->intel;
41 vp = brw_state_batch(brw, AUB_TRACE_SF_VP_STATE,
42 sizeof(*vp), 64, &brw->sf.vp_offset);
44 brw->clip.vp_offset = brw->sf.vp_offset;
71 OUT_BATCH(brw->sf.vp_offset);
78 .brw = BRW_NEW_BATCH,
86 static void upload_cc_viewport_state_pointer(struct brw_context *brw) argument
88 struct intel_context *intel = &brw
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