Searched refs:i16 (Results 51 - 75 of 166) sorted by relevance

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/external/chromium_org/base/win/
H A Dscoped_variant.h95 void Set(int16 i16);
/external/libhevc/common/arm/
H A Dihevc_itrans_recon_4x4_ttype1.s133 vmov.i16 d4[0],r8
135 vmov.i16 d4[1],r9
137 vmov.i16 d4[2],r10
139 vmov.i16 d4[3],r11
/external/llvm/include/llvm/Support/
H A DDataTypes.h153 # define INT16_C(C) C##i16
/external/llvm/include/llvm/CodeGen/
H A DMachineValueType.h40 i16 = 3, // This is a 16 bit integer value enumerator in enum:llvm::MVT::SimpleValueType
72 v1i16 = 26, // 1 x i16
73 v2i16 = 27, // 2 x i16
74 v4i16 = 28, // 4 x i16
75 v8i16 = 29, // 8 x i16
76 v16i16 = 30, // 16 x i16
77 v32i16 = 31, // 32 x i16
286 case v32i16: return i16;
381 case i16 :
495 return MVT::i16;
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/external/chromium_org/third_party/icu/source/test/iotest/
H A Diotest.cpp212 int16_t i16; local
268 i16 = (int16_t)uto64(argument);
269 uBufferLenReturned = u_sprintf_u(uBuffer, format, i16);
270 uFileBufferLenReturned = u_fprintf_u(testFile.getAlias(), format, i16);
377 int16_t i16, expected16; local
451 uBufferLenReturned = u_sscanf_u(argument, format, &i16);
452 //uFileBufferLenReturned = u_fscanf_u(testFile, format, i16);
453 if (i16 != expected16) {
455 i, i16, expected16);
581 int16_t i16; local
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/external/icu/icu4c/source/test/iotest/
H A Diotest.cpp212 int16_t i16; local
268 i16 = (int16_t)uto64(argument);
269 uBufferLenReturned = u_sprintf_u(uBuffer, format, i16);
270 uFileBufferLenReturned = u_fprintf_u(testFile.getAlias(), format, i16);
377 int16_t i16, expected16; local
451 uBufferLenReturned = u_sscanf_u(argument, format, &i16);
452 //uFileBufferLenReturned = u_fscanf_u(testFile, format, i16);
453 if (i16 != expected16) {
455 i, i16, expected16);
581 int16_t i16; local
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/external/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp128 addRegisterClass(MVT::i16, &NVPTX::Int16RegsRegClass);
139 setOperationAction(ISD::SELECT_CC, MVT::i16, Expand);
146 setOperationAction(ISD::BR_CC, MVT::i16, Expand);
153 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
179 setOperationAction(ISD::ROTL, MVT::i16, Expand);
180 setOperationAction(ISD::ROTR, MVT::i16, Expand);
183 setOperationAction(ISD::BSWAP, MVT::i16, Expand);
212 setTruncStoreAction(MVT::i16, MVT::i1, Expand);
239 setOperationAction(ISD::CTLZ, MVT::i16, Legal);
242 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Lega
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/external/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp274 if (VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) {
456 case MVT::i16:
582 case MVT::i16:
754 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 ||
775 case MVT::i16:
933 if (SrcVT != MVT::i8 && SrcVT != MVT::i16 &&
955 if (SrcVT == MVT::i8 || SrcVT == MVT::i16) {
1094 if (DestVT != MVT::i16 && DestVT != MVT::i8)
1332 if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32)
1356 } else if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetV
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/external/libvpx/libvpx/vp8/common/arm/neon/
H A Didct_dequant_full_2x_neon.asm44 vmul.i16 q2, q2, q0
45 vmul.i16 q3, q3, q1
46 vmul.i16 q4, q4, q0
47 vmul.i16 q5, q5, q1
163 vmov.i16 q14, #0
/external/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp307 { ISD::FP_TO_SINT, MVT::i16, MVT::f32, 2 },
308 { ISD::FP_TO_UINT, MVT::i16, MVT::f32, 2 },
309 { ISD::FP_TO_SINT, MVT::i16, MVT::f64, 2 },
310 { ISD::FP_TO_UINT, MVT::i16, MVT::f64, 2 },
338 { ISD::SINT_TO_FP, MVT::f32, MVT::i16, 2 },
339 { ISD::UINT_TO_FP, MVT::f32, MVT::i16, 2 },
340 { ISD::SINT_TO_FP, MVT::f64, MVT::i16, 2 },
341 { ISD::UINT_TO_FP, MVT::f64, MVT::i16, 2 },
362 // i16 -> i64 requires two dependent operations.
363 { ISD::SIGN_EXTEND, MVT::i64, MVT::i16,
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H A DARMSelectionDAGInfo.cpp101 VT = MVT::i16;
125 VT = MVT::i16;
H A DARMFastISel.cpp513 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
746 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
863 case MVT::i16:
984 case MVT::i16:
1109 case MVT::i16:
1381 if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 ||
1417 case MVT::i16:
1444 // We have i1, i8, or i16, we need to either zero extend or sign extend.
1562 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1569 if (SrcVT == MVT::i16 || SrcV
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/external/chromium_org/third_party/webrtc/modules/audio_processing/ns/
H A Dnsx_core_neon.S182 vmov.i16 q13, #512
183 vmov.i16 q7, #15
190 vclz.i16 q4, q0
191 vsub.i16 q4, q4, q7 @ Value of the shift factors; likely negative.
200 vmov.i16 q1, q9
217 vsub.i16 q4, q10, q2
218 vadd.i16 q8, q10, q8
219 vsub.i16 q2, q3, q10
225 vsub.i16 q1, q3, q10
231 vadd.i16 q
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/external/llvm/test/MC/ARM/
H A Dneont2-add-encoding.s7 @ CHECK: vadd.i16 d16, d17, d16 @ encoding: [0x51,0xef,0xa0,0x08]
8 vadd.i16 d16, d17, d16
127 @ CHECK: vaddhn.i16 d16, q8, q9 @ encoding: [0xc0,0xef,0xa2,0x04]
128 vaddhn.i16 d16, q8, q9
133 @ CHECK: vraddhn.i16 d16, q8, q9 @ encoding: [0xc0,0xff,0xa2,0x04]
134 vraddhn.i16 d16, q8, q9
H A Dneon-pairwise-encoding.s5 @ CHECK: vpadd.i16 d16, d17, d16 @ encoding: [0xb0,0x0b,0x51,0xf2]
6 vpadd.i16 d16, d17, d16
14 @ CHECK: vpadd.i16 d17, d17, d16 @ encoding: [0xb0,0x1b,0x51,0xf2]
15 vpadd.i16 d17, d16
H A Dneon-add-encoding.s6 @ CHECK: vadd.i16 d16, d17, d16 @ encoding: [0xa0,0x08,0x51,0xf2]
7 vadd.i16 d16, d17, d16
223 @ CHECK: vaddhn.i16 d16, q8, q9 @ encoding: [0xa2,0x04,0xc0,0xf2]
224 vaddhn.i16 d16, q8, q9
229 @ CHECK: vraddhn.i16 d16, q8, q9 @ encoding: [0xa2,0x04,0xc0,0xf3]
230 vraddhn.i16 d16, q8, q9
240 vadd.i16 d7, d1
245 vadd.i16 q7, q1
250 @ CHECK: vadd.i16 d7, d7, d1 @ encoding: [0x01,0x78,0x17,0xf2]
255 @ CHECK: vadd.i16 q
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H A Dneon-shift-encoding.s9 vshl.i16 d16, d16, #15
17 vshl.i16 q8, q8, #15
26 @ CHECK: vshl.i16 d16, d16, #15 @ encoding: [0x30,0x05,0xdf,0xf2]
34 @ CHECK: vshl.i16 q8, q8, #15 @ encoding: [0x70,0x05,0xdf,0xf2]
260 vshll.i16 q8, d16, #16
270 @ CHECK: vshll.i16 q8, d16, #16 @ encoding: [0x20,0x03,0xf6,0xf3]
273 vshrn.i16 d16, q8, #8
277 @ CHECK: vshrn.i16 d16, q8, #8 @ encoding: [0x30,0x08,0xc8,0xf2]
350 vrshrn.i16 d16, q8, #8
360 @ CHECK: vrshrn.i16 d1
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/external/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp137 if (VT == MVT::i8 || VT == MVT::i16)
167 case MVT::i16: {
224 case MVT::i16:
358 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
/external/valgrind/main/none/tests/arm/
H A Dneon64.stdout.exp4 vmov.i16 d1, #0x7 :: Qd 0x00070007 0x00070007
5 vmov.i16 d1, #0x7 :: Qd 0x00070007 0x00070007
10 vmov.i16 d7, #0x700 :: Qd 0x07000700 0x07000700
11 vmov.i16 d7, #0x700 :: Qd 0x07000700 0x07000700
29 vmvn.i16 d1, #0x7 :: Qd 0xfff8fff8 0xfff8fff8
30 vmvn.i16 d1, #0x7 :: Qd 0xfff8fff8 0xfff8fff8
35 vmvn.i16 d7, #0x700 :: Qd 0xf8fff8ff 0xf8fff8ff
36 vmvn.i16 d7, #0x700 :: Qd 0xf8fff8ff 0xf8fff8ff
50 vorr.i16 d2, #0x7 :: Qd 0x55575557 0x55575557
51 vorr.i16 d
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H A Dneon128.c356 TESTINSN_imm("vmov.i16 q1", q1, 0x7);
359 TESTINSN_imm("vmov.i16 q7", q7, 0x700);
370 TESTINSN_imm("vmvn.i16 q1", q1, 0x7);
373 TESTINSN_imm("vmvn.i16 q7", q7, 0x700);
382 TESTINSN_imm("vorr.i16 q2", q2, 0x7);
384 TESTINSN_imm("vorr.i16 q6", q6, 0x700);
390 TESTINSN_imm("vbic.i16 q3", q3, 0x7);
392 TESTINSN_imm("vbic.i16 q8", q8, 0x700);
408 TESTINSN_un("vmov q10, q11", q10, q11, i16, 7);
415 TESTINSN_bin("vadd.i16 q
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H A Dneon64.c643 TESTINSN_imm("vmov.i16 d1", d1, 0x7);
646 TESTINSN_imm("vmov.i16 d7", d7, 0x700);
658 TESTINSN_imm("vmvn.i16 d1", d1, 0x7);
661 TESTINSN_imm("vmvn.i16 d7", d7, 0x700);
671 TESTINSN_imm("vorr.i16 d2", d2, 0x7);
673 TESTINSN_imm("vorr.i16 d6", d6, 0x700);
680 TESTINSN_imm("vbic.i16 d3", d3, 0x7);
682 TESTINSN_imm("vbic.i16 d8", d8, 0x700);
701 TESTINSN_un("vmov d10, d11", d10, d11, i16, 7);
709 TESTINSN_bin("vadd.i16 d
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/external/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp437 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
452 case MVT::i16:
537 case MVT::i16:
600 // those that can be sign or zero-extended to a basic operation (i1/i8/i16).
637 case MVT::i16:
694 // those that can be sign or zero-extended to a basic operation (i1/i8/i16).
894 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 ||
921 case MVT::i16:
959 // We have i1, i8, or i16, we need to either zero extend or sign extend.
1165 if (SrcVT == MVT::i16 || SrcV
[all...]
/external/clang/test/Sema/
H A Datomic-ops.c44 short i16; variable
52 _Static_assert(__atomic_is_lock_free(2, &i16), "");
54 _Static_assert(__atomic_is_lock_free(4, &i16), ""); // expected-error {{not an integral constant expression}}
75 _Static_assert(__atomic_always_lock_free(2, &i16), "");
77 _Static_assert(!__atomic_always_lock_free(4, &i16), "");
/external/chromium_org/third_party/webrtc/common_audio/signal_processing/
H A Dmin_max_operations_neon.S39 vmov.i16 q12, #0
132 vmov.i16 q12, #0x8000
212 vmov.i16 q12, #0x7FFF
/external/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp627 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
630 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
1327 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
1329 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
1749 // A special case for i16, which needs truncating as, in most cases, it's
1752 if (Val.getOpcode() == ISD::TRUNCATE && NVT == MVT::i16 &&
1813 case MVT::i16:
1951 if (LdVT != MVT::i64 && LdVT != MVT::i32 && LdVT != MVT::i16 &&
2015 if (LdVT == MVT::i16) return X86::DEC16m;
2021 if (LdVT == MVT::i16) retur
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