/external/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 818 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) argument 820 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 961 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); local 991 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 992 unsigned AndRes = RegInfo.createVirtualRegister(RC); 993 unsigned Success = RegInfo.createVirtualRegister(RC); 1060 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); local 1061 unsigned ScrReg = RegInfo.createVirtualRegister(RC); 1080 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); local 1088 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 1230 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); local 1312 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); local 2698 const TargetRegisterClass *RC = getRegClassFor(RegVT); local 2988 const TargetRegisterClass *RC; local 3560 const TargetRegisterClass *RC = getRegClassFor(RegTy); local 3681 const TargetRegisterClass *RC = getRegClassFor(RegTy); local [all...] |
/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 487 const TargetRegisterClass *RC, const unsigned *Map) { 493 return std::make_pair(Map[Index], RC); 693 const TargetRegisterClass *RC; local 700 RC = &SystemZ::GR32BitRegClass; 704 RC = &SystemZ::GR64BitRegClass; 708 RC = &SystemZ::FP32BitRegClass; 712 RC = &SystemZ::FP64BitRegClass; 716 unsigned VReg = MRI.createVirtualRegister(RC); 2752 const TargetRegisterClass *RC = (BitSize <= 32 ? local 2764 unsigned OrigVal = MRI.createVirtualRegister(RC); 486 parseRegisterNumber(const std::string &Constraint, const TargetRegisterClass *RC, const unsigned *Map) argument 2875 const TargetRegisterClass *RC = (BitSize <= 32 ? local 2985 const TargetRegisterClass *RC = &SystemZ::GR32BitRegClass; local 3144 const TargetRegisterClass *RC = &SystemZ::ADDR64BitRegClass; local 3299 const TargetRegisterClass *RC = &SystemZ::GR64BitRegClass; local [all...] |
/external/llvm/lib/Transforms/Scalar/ |
H A D | LoopStrengthReduce.cpp | 536 const SCEVConstant *RC = dyn_cast<SCEVConstant>(RHS); local 537 if (RC) { 538 const APInt &RA = RC->getValue()->getValue(); 542 return SE.getMulExpr(LHS, RC); 550 if (!RC) 553 const APInt &RA = RC->getValue()->getValue();
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/external/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 2276 const TargetRegisterClass *RC; local 2278 RC = &X86::GR32RegClass; 2280 RC = &X86::GR64RegClass; 2282 RC = &X86::FR32RegClass; 2284 RC = &X86::FR64RegClass; 2286 RC = &X86::VR512RegClass; 2288 RC = &X86::VR256RegClass; 2290 RC = &X86::VR128RegClass; 2292 RC = &X86::VR64RegClass; 2294 RC [all...] |
/external/clang/lib/AST/ |
H A D | ASTContext.cpp | 352 const RawComment *RC = nullptr; local 360 RC = Raw.getRaw(); 365 RC = getRawCommentForDeclNoCache(I); 368 if (RC) { 369 Raw.setRaw(RC); 375 if (RC) 381 assert(!RC || RC->isDocumentation()); 388 Raw.setRaw(RC); 398 return RC; 435 const RawComment *RC = getRawCommentForDeclNoCache(D); local 461 const RawComment *RC = getRawCommentForAnyRedecl(D, &OriginalDecl); local [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 1712 const TargetRegisterClass *RC; local 1715 RC = &AArch64::GPR32RegClass; 1717 RC = &AArch64::GPR64RegClass; 1719 RC = &AArch64::FPR32RegClass; 1721 RC = &AArch64::FPR64RegClass; 1723 RC = &AArch64::FPR128RegClass; 1728 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
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/external/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 2693 const TargetRegisterClass *RC; local 2695 RC = &ARM::tGPRRegClass; 2697 RC = &ARM::GPRRegClass; 2700 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 2714 Reg = MF.addLiveIn(NextVA.getLocReg(), RC); 2847 const TargetRegisterClass *RC; local 2849 RC = &ARM::tGPRRegClass; 2851 RC = &ARM::GPRRegClass; 2853 unsigned VReg = MF.addLiveIn(GPRArgRegs[firstRegToSaveIndex], RC); 3016 const TargetRegisterClass *RC; local [all...] |
/external/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 3310 const MCRegisterClass *RC; local 3312 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID]; 3314 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID]; 3316 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID]; 3343 if (!RC->contains(EndReg)) 3371 if (!RC->contains(Reg)) 3386 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] && 3684 const MCRegisterClass *RC = (Spacing == 1) ? local 3687 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); 3697 const MCRegisterClass *RC local [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 2257 const TargetRegisterClass *RC; local 2265 RC = &PPC::GPRCRegClass; 2268 RC = &PPC::F4RCRegClass; 2272 RC = &PPC::VSFRCRegClass; 2274 RC = &PPC::F8RCRegClass; 2280 RC = &PPC::VRRCRegClass; 2284 RC = &PPC::VSHRCRegClass; 2289 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 6349 const TargetRegisterClass *RC = local 6352 unsigned PtrReg = RegInfo.createVirtualRegister(RC); 6463 const TargetRegisterClass *RC = MRI.getRegClass(DstReg); local 6610 const TargetRegisterClass *RC = local 6956 const TargetRegisterClass *RC = local [all...] |
/external/clang/lib/Sema/ |
H A D | SemaExpr.cpp | 10263 const RecordType *RC = CurrentType->getAs<RecordType>(); local 10264 if (!RC) 10267 RecordDecl *RD = RC->getDecl();
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/external/owasp/sanitizer/tools/findbugs/lib/ |
H A D | bcel.jar | META-INF/ META-INF/MANIFEST.MF org/ org/apache/ org/apache/bcel/ org/apache/bcel/classfile/ ... |
/external/chromium_org/third_party/WebKit/Source/devtools/scripts/closure/ |
H A D | compiler.jar | META-INF/ META-INF/MANIFEST.MF com/ com/google/ com/google/javascript/ com/google/javascript/jscomp/ ... |
/external/chromium_org/third_party/closure_compiler/compiler/ |
H A D | compiler.jar | META-INF/ META-INF/MANIFEST.MF com/ com/google/ com/google/debugging/ com/google/debugging/sourcemap/ ... |