/external/llvm/lib/CodeGen/ |
H A D | MachineCSE.cpp | 119 MachineOperand &MO = MI->getOperand(i); 132 unsigned SrcReg = DefMI->getOperand(1).getReg(); 135 if (DefMI->getOperand(0).getSubReg()) 149 if (DefMI->getOperand(1).getSubReg()) 182 const MachineOperand &MO = I->getOperand(i); 216 const MachineOperand &MO = MI->getOperand(i); 235 const MachineOperand &MO = MI->getOperand(i); 307 const MachineOperand &MO = I->getOperand(i); 394 const MachineOperand &MO = MI->getOperand(i); 526 MachineOperand &MO = MI->getOperand( [all...] |
H A D | UnreachableBlockElim.cpp | 153 if (start->getOperand(i).isMBB() && 154 start->getOperand(i).getMBB() == BB) { 180 if (!preds.count(phi->getOperand(i).getMBB())) { 187 unsigned Input = phi->getOperand(1).getReg(); 188 unsigned Output = phi->getOperand(0).getReg();
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H A D | StackMaps.cpp | 40 HasDef(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() && 41 !MI->getOperand(0).isImplicit()), 42 IsAnyReg(MI->getOperand(getMetaIdx(CCPos)).getImm() == CallingConv::AnyReg) 46 while (CheckStartIdx < e && MI->getOperand(CheckStartIdx).isReg() && 47 MI->getOperand(CheckStartIdx).isDef() && 48 !MI->getOperand(CheckStartIdx).isImplicit()) 63 !(MI->getOperand(ScratchIdx).isReg() && 64 MI->getOperand(ScratchIdx).isDef() && 65 MI->getOperand(ScratchId [all...] |
H A D | RegisterCoalescer.cpp | 220 Dst = MI->getOperand(0).getReg(); 221 DstSub = MI->getOperand(0).getSubReg(); 222 Src = MI->getOperand(1).getReg(); 223 SrcSub = MI->getOperand(1).getSubReg(); 225 Dst = MI->getOperand(0).getReg(); 226 DstSub = tri.composeSubRegIndices(MI->getOperand(0).getSubReg(), 227 MI->getOperand(3).getImm()); 228 Src = MI->getOperand(2).getReg(); 229 SrcSub = MI->getOperand(2).getSubReg(); 501 ValSEndInst->getOperand(UId [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86AsmPrinter.cpp | 183 const MachineOperand &MO = MI->getOperand(OpNo); 202 const MachineOperand &MO = MI->getOperand(OpNo); 235 const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); 236 const MachineOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); 237 const MachineOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp); 276 unsigned ScaleVal = MI->getOperand(Op+X86::AddrScaleAmt).getImm(); 288 const MachineOperand &Segment = MI->getOperand(Op+X86::AddrSegmentReg); 300 const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); 301 unsigned ScaleVal = MI->getOperand(Op+X86::AddrScaleAmt).getImm(); 302 const MachineOperand &IndexReg = MI->getOperand(O [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64BranchRelaxation.cpp | 299 return MI->getOperand(2).getMBB(); 305 return MI->getOperand(1).getMBB(); 346 AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(0).getImm(); 348 MI->getOperand(0).setImm((int64_t)CC); 383 MachineBasicBlock *NewDest = BMI->getOperand(0).getMBB(); 388 BMI->getOperand(0).setMBB(DestBB); 395 MI->getOperand(OpNum).setMBB(NewDest); 432 .addOperand(MI->getOperand(0)); 435 MIB.addOperand(MI->getOperand(1));
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H A D | AArch64ConditionalCompares.cpp | 222 MachineBasicBlock *MBB = I.getOperand(oi + 1).getMBB(); 223 unsigned Reg = I.getOperand(oi).getReg(); 248 if (I.getOperand(oi - 1).getMBB() == CmpBB) { 330 if (I->getOperand(3).getImm() || !isUInt<5>(I->getOperand(2).getImm())) { 340 if (isDeadDef(I->getOperand(0).getReg())) 651 MRI->constrainRegClass(CmpMI->getOperand(FirstOp).getReg(), 653 if (CmpMI->getOperand(FirstOp + 1).isReg()) 654 MRI->constrainRegClass(CmpMI->getOperand(FirstOp + 1).getReg(), 658 .addOperand(CmpMI->getOperand(FirstO [all...] |
H A D | AArch64CleanupLocalDynamicTLSPass.cpp | 67 if (!I->getOperand(1).isSymbol() || 68 strcmp(I->getOperand(1).getSymbolName(), "_TLS_MODULE_BASE_"))
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/external/llvm/lib/Target/Sparc/MCTargetDesc/ |
H A D | SparcMCCodeEmitter.cpp | 103 const MCOperand &MO = MI.getOperand(tlsOpNo); 144 const MCOperand &MO = MI.getOperand(OpNo); 179 const MCOperand &MO = MI.getOperand(OpNo); 192 const MCOperand &MO = MI.getOperand(OpNo); 204 const MCOperand &MO = MI.getOperand(OpNo);
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/external/llvm/lib/Transforms/Scalar/ |
H A D | LoopIdiomRecognize.cpp | 250 Value *Op = DeadInst->getOperand(op); 354 ConstantInt *CmpZero = dyn_cast<ConstantInt>(Cond->getOperand(1)); 361 return Cond->getOperand(0); 414 if ((SubOneOp = dyn_cast<BinaryOperator>(DefX2->getOperand(0)))) 415 VarX1 = DefX2->getOperand(1); 417 VarX1 = DefX2->getOperand(0); 418 SubOneOp = dyn_cast<BinaryOperator>(DefX2->getOperand(1)); 424 ConstantInt *Dec = dyn_cast<ConstantInt>(SubInst->getOperand(1)); 436 (PhiX->getOperand(0) != DefX2 && PhiX->getOperand( [all...] |
H A D | JumpThreading.cpp | 418 ComputeValueKnownInPredecessors(I->getOperand(0), BB, LHSVals, 420 ComputeValueKnownInPredecessors(I->getOperand(1), BB, RHSVals, 459 isa<ConstantInt>(I->getOperand(1)) && 460 cast<ConstantInt>(I->getOperand(1))->isOne()) { 461 ComputeValueKnownInPredecessors(I->getOperand(0), BB, Result, 477 if (ConstantInt *CI = dyn_cast<ConstantInt>(BO->getOperand(1))) { 479 ComputeValueKnownInPredecessors(BO->getOperand(0), BB, LHSVals, 498 PHINode *PN = dyn_cast<PHINode>(Cmp->getOperand(0)); 505 Value *RHS = Cmp->getOperand(1)->DoPHITranslation(BB, PredBB); 530 if (isa<Constant>(Cmp->getOperand( [all...] |
/external/llvm/lib/Transforms/Utils/ |
H A D | ValueMapper.cpp | 73 Value *OP = MD->getOperand(i); 86 Value *Op = MD->getOperand(i); 131 Value *Op = C->getOperand(OpNo); 151 Ops.push_back(cast<Constant>(C->getOperand(j))); 159 Ops.push_back(MapValue(cast<Constant>(C->getOperand(OpNo)), VM,
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/external/llvm/lib/IR/ |
H A D | ConstantFold.cpp | 85 Type *SrcTy = Op->getOperand(0)->getType(); 224 Constant *RHS = ExtractConstantBytes(CE->getOperand(1), ByteStart,ByteSize); 233 Constant *LHS = ExtractConstantBytes(CE->getOperand(0), ByteStart,ByteSize); 239 Constant *RHS = ExtractConstantBytes(CE->getOperand(1), ByteStart,ByteSize); 247 Constant *LHS = ExtractConstantBytes(CE->getOperand(0), ByteStart,ByteSize); 253 ConstantInt *Amt = dyn_cast<ConstantInt>(CE->getOperand(1)); 268 return ExtractConstantBytes(CE->getOperand(0), ByteStart+ShAmt, ByteSize); 275 ConstantInt *Amt = dyn_cast<ConstantInt>(CE->getOperand(1)); 290 return ExtractConstantBytes(CE->getOperand(0), ByteStart-ShAmt, ByteSize); 298 cast<IntegerType>(CE->getOperand( [all...] |
H A D | Instructions.cpp | 799 ProfileData->getOperand(0), 800 ProfileData->getOperand(2), 801 ProfileData->getOperand(1) 902 if (ConstantInt *CI = dyn_cast<ConstantInt>(getOperand(0))) 928 assert(getOperand(0)->getType()->isPointerTy() && 1080 assert(getOperand(0) && getOperand(1) && "Both operands must be non-null!"); 1081 assert(getOperand(1)->getType()->isPointerTy() && 1083 assert(getOperand(0)->getType() == 1084 cast<PointerType>(getOperand( [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 442 N->getOperand(0), N->getOperand(1)); 511 SDValue LHS = Op.getOperand(0); 516 SDValue RHS = Op.getOperand(1); 521 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 530 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2)); 544 SDValue SetCC = N->getOperand(0); 547 !SetCC.getOperand(0).getValueType().isInteger()) 550 SDValue False = N->getOperand(2); 571 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand( [all...] |
H A D | MipsSERegisterInfo.cpp | 150 Offset += MI.getOperand(OpNo + 1).getImm(); 202 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill); 203 MI.getOperand(OpNo + 1).ChangeToImmediate(Offset);
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelDAGToDAG.cpp | 394 SDValue Base = Const32->getOperand(0); 443 SDValue N1 = LD->getOperand(1); 510 SDValue N1 = LD->getOperand(1); 776 SDValue Base = Const32->getOperand(0); 844 SDValue MulOp0 = N->getOperand(0); 845 SDValue MulOp1 = N->getOperand(1); 852 SDValue Sext0 = MulOp0.getOperand(0); 878 SDValue Sext1 = MulOp1.getOperand(0); 915 SDValue N0 = N->getOperand(0); 917 SDValue N00 = N0.getOperand( [all...] |
H A D | HexagonCFGOptimizer.cpp | 99 MI->getOperand(1).setMBB(NewTarget); 168 CondBranchTarget = MI->getOperand(1).getMBB(); 181 LayoutSucc->front().getOperand(0).getMBB();
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/external/llvm/lib/Analysis/ |
H A D | Lint.cpp | 469 AA->getTypeStoreSize(I.getOperand(0)->getType()), 471 I.getOperand(0)->getType(), MemRef::Write); 475 Assert1(!isa<UndefValue>(I.getOperand(0)) || 476 !isa<UndefValue>(I.getOperand(1)), 481 Assert1(!isa<UndefValue>(I.getOperand(0)) || 482 !isa<UndefValue>(I.getOperand(1)), 488 dyn_cast<ConstantInt>(findValue(I.getOperand(1), /*OffsetOk=*/false))) 495 dyn_cast<ConstantInt>(findValue(I.getOperand(1), /*OffsetOk=*/false))) 502 dyn_cast<ConstantInt>(findValue(I.getOperand(1), /*OffsetOk=*/false))) 546 Assert1(!isZero(I.getOperand( [all...] |
H A D | CaptureTracking.cpp | 136 if (V == I->getOperand(0)) 165 dyn_cast<ConstantPointerNull>(I->getOperand(1)))
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXImageOptimizer.cpp | 91 Value *TexHandle = cleanupValue(I.getOperand(0)); 109 Value *TexHandle = cleanupValue(I.getOperand(0)); 128 Value *TexHandle = cleanupValue(I.getOperand(0));
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/external/llvm/lib/Target/R600/ |
H A D | SITypeRewriter.cpp | 123 Args.push_back(Def->getOperand(1)); 152 if (BitCastInst *Op = dyn_cast<BitCastInst>(I.getOperand(0))) { 154 I.replaceAllUsesWith(Op->getOperand(0));
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H A D | R600OptimizeVectorRegisters.cpp | 69 MachineOperand &MO = Instr->getOperand(i); 70 unsigned Chan = Instr->getOperand(i + 1).getImm(); 180 unsigned Reg = RSI->Instr->getOperand(0).getReg(); 185 unsigned SrcVec = BaseRSI->Instr->getOperand(0).getReg(); 254 unsigned Swizzle = MI.getOperand(i + Offset).getImm() + 1; 257 MI.getOperand(i + Offset).setImm(RemapChan[j].second - 1); 331 unsigned Reg = MI->getOperand(1).getReg(); 345 unsigned Reg = MI->getOperand(0).getReg();
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/external/llvm/include/llvm/IR/ |
H A D | OperandTraits.h | 110 inline VALUECLASS *getOperand(unsigned) const; \ 136 VALUECLASS *CLASS::getOperand(unsigned i_nocapture) const { \ 138 && "getOperand() out of range!"); \
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/external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonMCInst.cpp | 73 const MCOperand& MCO = getOperand(O); 97 const MCOperand& MO = getOperand(ExtOpNum);
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