Searched defs:reg (Results 276 - 300 of 670) sorted by relevance

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/external/dexmaker/src/dx/java/com/android/dx/ssa/
H A DSsaMethod.java405 * @param reg register in question
406 * @return insn (actual instance from code) that defined this reg or null
407 * if reg is not defined.
409 public SsaInsn getDefinitionForRegister(int reg) { argument
415 return definitionList[reg];
435 return definitionList[reg];
499 int reg = oldSource.getReg();
500 useList[reg].remove(insn);
503 int reg = newSource.getReg();
504 if (useList.length <= reg) {
638 getUseListForRegister(int reg) argument
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/external/dexmaker/src/dx/java/com/android/dx/ssa/back/
H A DFirstFitLocalCombiningAllocator.java58 /** indexed by SSA reg; the set of SSA regs we've mapped */
166 for (RegisterSpec reg : e.getValue()) {
168 regs.append(reg.getReg());
271 * Tries to map a list of SSA registers into the a rop reg, marking
372 int reg;
374 reg = reservedRopRegs.nextClearBit(startReg);
379 while (i < width && !reservedRopRegs.get(reg + i)) {
384 return reg;
387 reg = reservedRopRegs.nextClearBit(reg
1072 private final int[] reg; field in class:FirstFitLocalCombiningAllocator.Multiset
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/external/libnfc-nci/src/nfa/include/
H A Dnfa_snep_api.h171 tNFA_SNEP_REG reg; /* NFA_SNEP_REG_EVT */ member in union:__anon24077
/external/libunwind/include/
H A Dlibunwind-dynamic.h87 int16_t reg; /* what register */ member in struct:unw_dyn_op
179 #define _U_dyn_op_save_reg(op, qp, when, reg, dst) \
180 (*(op) = _U_dyn_op (UNW_DYN_SAVE_REG, (qp), (when), (reg), (dst)))
182 #define _U_dyn_op_spill_fp_rel(op, qp, when, reg, offset) \
183 (*(op) = _U_dyn_op (UNW_DYN_SPILL_FP_REL, (qp), (when), (reg), \
186 #define _U_dyn_op_spill_sp_rel(op, qp, when, reg, offset) \
187 (*(op) = _U_dyn_op (UNW_DYN_SPILL_SP_REL, (qp), (when), (reg), \
190 #define _U_dyn_op_add(op, qp, when, reg, value) \
191 (*(op) = _U_dyn_op (UNW_DYN_ADD, (qp), (when), (reg), (value)))
/external/lldb/source/Plugins/Process/POSIX/
H A DPOSIXThread.cpp526 unsigned reg = LLDB_INVALID_REGNUM; local
543 reg = context.GetRegisterIndexFromOffset(offset);
548 return reg;
552 POSIXThread::GetRegisterName(unsigned reg) argument
567 name = GetRegisterContext()->GetRegisterName(reg);
H A DRegisterContext_i386.cpp159 #define GPR_SIZE(reg) sizeof(((RegisterContext_i386::GPR*)NULL)->reg)
162 #define FPR_SIZE(reg) sizeof(((RegisterContext_i386::FPU*)NULL)->reg)
170 #define DEFINE_GPR(reg, alt, kind1, kind2, kind3, kind4) \
171 { #reg, alt, GPR_SIZE(reg), GPR_OFFSET(reg), eEncodingUint, \
172 eFormatHex, { kind1, kind2, kind3, kind4, gpr_##reg }, NULL, NULL }
174 #define DEFINE_FPR(reg, kind
247 GetRegOffset(unsigned reg) argument
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/external/lldb/source/Target/
H A DRegisterContext.cpp70 for (uint32_t reg = start_idx; reg < num_registers; ++reg)
72 const RegisterInfo * reg_info = GetRegisterInfoAtIndex(reg);
85 RegisterContext::GetRegisterName (uint32_t reg) argument
87 const RegisterInfo * reg_info = GetRegisterInfoAtIndex(reg);
96 uint32_t reg = ConvertRegisterKindToRegisterNumber (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC); local
97 return ReadRegisterAsUnsigned (reg, fail_value);
103 uint32_t reg = ConvertRegisterKindToRegisterNumber (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC); local
104 bool success = WriteRegisterFromUnsigned (reg, p
119 uint32_t reg = ConvertRegisterKindToRegisterNumber (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP); local
126 uint32_t reg = ConvertRegisterKindToRegisterNumber (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP); local
133 uint32_t reg = ConvertRegisterKindToRegisterNumber (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FP); local
140 uint32_t reg = ConvertRegisterKindToRegisterNumber (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FP); local
147 uint32_t reg = ConvertRegisterKindToRegisterNumber (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA); local
154 uint32_t reg = ConvertRegisterKindToRegisterNumber (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS); local
160 ReadRegisterAsUnsigned(uint32_t reg, uint64_t fail_value) argument
180 WriteRegisterFromUnsigned(uint32_t reg, uint64_t uval) argument
219 const uint32_t reg = reg_set->registers[reg_idx]; local
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/external/llvm/include/llvm/CodeGen/
H A DLiveInterval.h532 const unsigned reg; // the register or stack slot of this interval. member in class:llvm::LiveInterval
536 : reg(Reg), weight(Weight) {}
555 return std::tie(thisIndex, reg) < std::tie(otherIndex, other.reg);
/external/llvm/lib/Target/Hexagon/
H A DHexagonNewValueJump.cpp288 static unsigned getNewValueJumpOpcode(MachineInstr *MI, int reg, argument
307 if (reg >= 0)
325 if (reg >= 0)
390 unsigned predReg = 0; // predicate reg of the jump.
491 // We need cmpReg1 and cmpOp2(imm or reg) while building
/external/ltrace/sysdeps/linux-gnu/arm/
H A Dtrace.c189 /* BX <reg>, BLX <reg> */
192 enum arm_register reg = BITS(this_instr, 0, 3); local
196 if (arm_get_register_offpc(proc, reg, &tmp) < 0)
/external/mesa3d/src/gallium/auxiliary/gallivm/
H A Dlp_bld_tgsi_aos.c104 const struct tgsi_full_src_register * reg,
114 assert(!reg->Register.Indirect);
128 reg->Register.Index * 4 + chan);
134 lp_build_name(scalar, "const[%u].%c", reg->Register.Index, "xyzw"[chan]);
175 const struct tgsi_full_src_register * reg,
180 LLVMValueRef res = bld->immediates[reg->Register.Index];
188 const struct tgsi_full_src_register * reg,
193 LLVMValueRef res = bld->inputs[reg->Register.Index];
194 assert(!reg->Register.Indirect);
202 const struct tgsi_full_src_register * reg,
102 emit_fetch_constant( struct lp_build_tgsi_context * bld_base, const struct tgsi_full_src_register * reg, enum tgsi_opcode_type stype, unsigned swizzle) argument
173 emit_fetch_immediate( struct lp_build_tgsi_context * bld_base, const struct tgsi_full_src_register * reg, enum tgsi_opcode_type stype, unsigned swizzle) argument
186 emit_fetch_input( struct lp_build_tgsi_context * bld_base, const struct tgsi_full_src_register * reg, enum tgsi_opcode_type stype, unsigned swizzle) argument
200 emit_fetch_temporary( struct lp_build_tgsi_context * bld_base, const struct tgsi_full_src_register * reg, enum tgsi_opcode_type stype, unsigned swizzle) argument
228 const struct tgsi_full_dst_register *reg = &inst->Dst[index]; local
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/external/mesa3d/src/gallium/drivers/i915/
H A Di915_fpc_translate.c114 negate(int reg, int x, int y, int z, int w) argument
117 return reg ^ (((x & 1) << UREG_CHANNEL_X_NEGATE_SHIFT) |
190 i915_program_error(p, "Exceeded max temporary reg");
671 tmp, /* dest reg: a dummy reg */
686 tmp, /* dest reg: a dummy reg */
1350 depth, /* dest reg */
/external/mesa3d/src/gallium/drivers/nv50/codegen/
H A Dnv50_ir_from_tgsi.cpp50 : reg(src->Register),
54 SrcRegister(const struct tgsi_src_register& src) : reg(src), fsr(NULL) { }
58 struct tgsi_src_register reg; local
59 memset(&reg, 0, sizeof(reg));
60 reg.Index = off.Index;
61 reg.File = off.File;
62 reg.SwizzleX = off.SwizzleX;
63 reg.SwizzleY = off.SwizzleY;
64 reg
111 const struct tgsi_src_register reg; member in class:tgsi::Instruction::SrcRegister
152 const struct tgsi_dst_register reg; member in class:tgsi::Instruction::DstRegister
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/external/mesa3d/src/gallium/drivers/r600/
H A Dr600_hw_context.c132 const struct r600_reg *reg, int index, int nreg,
141 block->start_offset = reg[i].offset;
144 block->reg = &block->pm4[block->pm4_ndwords];
152 if (reg[i+j].flags & REG_FLAG_DIRTY_ALWAYS) {
155 if (reg[i+j].flags & REG_FLAG_ENABLE_ALWAYS) {
162 if (reg[i+j].flags & REG_FLAG_FLUSH_CHANGE) {
166 if (reg[i+j].flags & REG_FLAG_NEED_BO) {
175 (ctx->family < CHIP_RV770) && reg[i+j].flags & REG_FLAG_RV6XX_SBU) {
177 block->pm4[block->pm4_ndwords++] = reg[i+j].sbu_flags;
184 int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigne argument
130 r600_init_block(struct r600_context *ctx, struct r600_block *block, const struct r600_reg *reg, int index, int nreg, unsigned opcode, unsigned offset_base) argument
713 r600_reg_set_block_reloc(struct r600_pipe_reg *reg) argument
760 struct r600_pipe_reg *reg = &state->regs[i]; local
770 struct r600_pipe_reg *reg = &state->regs[i]; local
783 struct r600_pipe_reg *reg = &state->regs[i]; local
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/external/mesa3d/src/gallium/drivers/svga/svgadump/
H A Dsvga_shader.h60 sh_reg_type( struct sh_reg reg )
62 return reg.type_lo | (reg.type_hi << 3);
73 struct sh_reg reg; member in struct:sh_def
80 struct sh_reg reg; member in struct:sh_defb
92 struct sh_reg reg; member in struct:sh_defi
142 sh_dstreg_type( struct sh_dstreg reg )
144 return reg.type_lo | (reg.type_hi << 3);
154 struct sh_dstreg reg; member in struct:sh_dcl
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/external/mesa3d/src/mesa/drivers/dri/i915/
H A Di915_fragprog.c92 i915_program_error(p, "Exceeded max temporary reg: %d/%d",
587 tmp, A0_DEST_CHANNEL_ALL, /* use a dummy dest reg */
600 0, /* use a dummy dest reg */
1201 GLint reg = p->param[i].reg; local
1202 COPY_4V(p->constant[reg], p->param[i].values);
H A Di915_program.c42 #define A0_DEST( reg ) (((reg)&UREG_TYPE_NR_MASK)>>UREG_A0_DEST_SHIFT_LEFT)
43 #define D0_DEST( reg ) (((reg)&UREG_TYPE_NR_MASK)>>UREG_A0_DEST_SHIFT_LEFT)
44 #define T0_DEST( reg ) (((reg)&UREG_TYPE_NR_MASK)>>UREG_A0_DEST_SHIFT_LEFT)
45 #define A0_SRC0( reg ) (((reg)&UREG_MASK)>>UREG_A0_SRC0_SHIFT_LEFT)
46 #define A1_SRC0( reg ) (((reg)
113 GLuint reg = UREG(type, nr); local
303 GLint reg, idx; local
333 GLint reg, idx; local
373 GLint reg; local
410 GLint reg, i; local
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/external/mesa3d/src/mesa/drivers/dri/i965/
H A Dbrw_eu.h196 struct brw_reg reg; local
204 reg.type = type;
205 reg.file = file;
206 reg.nr = nr;
207 reg.subnr = subnr * type_sz(type);
208 reg.negate = 0;
209 reg.abs = 0;
210 reg.vstride = vstride;
211 reg.width = width;
212 reg
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H A Dbrw_vec4.cpp62 src_reg::src_reg(register_file file, int reg, const glsl_type *type) argument
67 this->reg = reg;
107 src_reg::src_reg(dst_reg reg) argument
111 this->file = reg.file;
112 this->reg = reg.reg;
113 this->reg_offset = reg.reg_offset;
114 this->type = reg
160 dst_reg(register_file file, int reg) argument
168 dst_reg(register_file file, int reg, const glsl_type *type, int writemask) argument
179 dst_reg(struct brw_reg reg) argument
187 dst_reg(src_reg reg) argument
307 int reg = inst->src[i].reg; local
323 int reg = inst->dst.reg; local
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H A Dbrw_vec4_emit.cpp63 int grf = attribute_map[inst->dst.reg + inst->dst.reg_offset];
65 struct brw_reg reg = brw_vec8_grf(grf, 0); local
66 reg.dw1.bits.writemask = inst->dst.writemask;
69 inst->dst.fixed_hw_reg = reg;
76 int grf = attribute_map[inst->src[i].reg + inst->src[i].reg_offset];
78 struct brw_reg reg = brw_vec8_grf(grf, 0); local
79 reg.dw1.bits.swizzle = inst->src[i].swizzle;
80 reg.type = inst->src[i].type;
82 reg = brw_abs(reg);
110 setup_uniforms(int reg) argument
141 int reg = 0; local
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/external/mesa3d/src/mesa/drivers/dri/r200/
H A Dr200_sanity.c602 struct reg { struct
614 static struct reg regs[Elements(reg_names)+1];
615 static struct reg scalars[512+1];
616 static struct reg vectors[512*4+1];
650 static int find_or_add_value( struct reg *reg, int val ) argument
654 for ( j = 0 ; j < reg->nvalues ; j++)
655 if ( val == reg->values[j].i )
658 if (j == reg->nalloc) {
659 reg
710 print_int_reg_assignment( struct reg *reg, int data ) argument
734 print_float_reg_assignment( struct reg *reg, float data ) argument
765 print_reg_assignment( struct reg *reg, int data ) argument
828 struct reg *reg = lookup_reg( regs, packet[id].start + i*4 ); local
856 struct reg *reg = lookup_reg( scalars, start ); local
888 struct reg *reg = lookup_reg( scalars, start ); local
924 struct reg *reg = lookup_reg( vectors, start*4+j ); local
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H A Dradeon_common.c437 int i, j, reg, count; local
452 reg = (packet0 & 0x1FFF) << 2;
454 fprintf(stderr, " %s[%d]: cmdpacket0 (first reg=0x%04x, count=%d)\n",
455 state->name, i, reg, count);
459 state->name, i, reg, state->cmd[i]);
460 reg += 4;
/external/mesa3d/src/mesa/drivers/dri/radeon/
H A Dradeon_common.c437 int i, j, reg, count; local
452 reg = (packet0 & 0x1FFF) << 2;
454 fprintf(stderr, " %s[%d]: cmdpacket0 (first reg=0x%04x, count=%d)\n",
455 state->name, i, reg, count);
459 state->name, i, reg, state->cmd[i]);
460 reg += 4;
H A Dradeon_sanity.c324 struct reg { struct
336 static struct reg regs[Elements(reg_names)+1];
337 static struct reg scalars[512+1];
338 static struct reg vectors[512*4+1];
372 static int find_or_add_value( struct reg *reg, int val ) argument
376 for ( j = 0 ; j < reg->nvalues ; j++)
377 if ( val == reg->values[j].i )
380 if (j == reg->nalloc) {
381 reg
432 print_int_reg_assignment( struct reg *reg, int data ) argument
456 print_float_reg_assignment( struct reg *reg, float data ) argument
487 print_reg_assignment( struct reg *reg, int data ) argument
550 struct reg *reg = lookup_reg( regs, packet[id].start + i*4 ); local
578 struct reg *reg = lookup_reg( scalars, start ); local
610 struct reg *reg = lookup_reg( scalars, start ); local
646 struct reg *reg = lookup_reg( vectors, start*4+j ); local
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/external/mesa3d/src/mesa/program/
H A Dnvvertparse.c313 GLint reg = atoi((char *) (token + 1)); local
314 if (reg >= MAX_NV_VERTEX_PROGRAM_TEMPS)
316 *tempRegNum = reg;
367 GLint reg = atoi((char *) token); local
368 if (reg >= MAX_NV_VERTEX_PROGRAM_PARAMS)
370 *regNum = reg;
399 GLint reg; local
401 reg = atoi((char *) token);
402 if (reg >= MAX_NV_VERTEX_PROGRAM_PARAMS)
405 srcReg->Index = reg;
485 GLint reg = atoi((char *) token); local
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