Searched refs:TT (Results 76 - 100 of 195) sorted by relevance

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/external/llvm/lib/Target/R600/MCTargetDesc/
H A DAMDGPUMCAsmInfo.cpp14 AMDGPUMCAsmInfo::AMDGPUMCAsmInfo(StringRef &TT) : MCAsmInfo() { argument
/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/
H A DAMDGPUMCTargetDesc.h39 MCAsmBackend *createAMDGPUAsmBackend(const Target &T, StringRef TT);
/external/llvm/include/llvm/Support/
H A DTargetRegistry.h60 MCRelocationInfo *createMCRelocationInfo(StringRef TT, MCContext &Ctx);
62 MCSymbolizer *createMCSymbolizer(StringRef TT, LLVMOpInfoCallback GetOpInfo,
83 StringRef TT);
84 typedef MCCodeGenInfo *(*MCCodeGenInfoCtorFnTy)(StringRef TT,
90 typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(StringRef TT);
91 typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(StringRef TT,
95 StringRef TT,
106 StringRef TT,
127 StringRef TT,
144 typedef MCRelocationInfo *(*MCRelocationInfoCtorTy)(StringRef TT,
427 createMCObjectStreamer(StringRef TT, MCContext &Ctx, MCAsmBackend &TAB, raw_ostream &_OS, MCCodeEmitter *_Emitter, const MCSubtargetInfo &STI, bool RelaxAll, bool NoExecStack) const argument
467 createMCRelocationInfo(StringRef TT, MCContext &Ctx) const argument
484 createMCSymbolizer(StringRef TT, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo, MCContext *Ctx, MCRelocationInfo *RelInfo) const argument
861 Allocator(const MCRegisterInfo & , StringRef TT) argument
1064 Allocator(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
[all...]
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DAMDGPUSubtarget.cpp23 AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS) : argument
24 AMDGPUGenSubtargetInfo(TT, CPU, FS), mDumpCode(false) {
H A DAMDGPUTargetMachine.h27 MCAsmInfo* createMCAsmInfo(const Target &T, StringRef TT);
41 AMDGPUTargetMachine(const Target &T, StringRef TT, StringRef FS,
H A DAMDGPUTargetMachine.cpp41 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT, argument
48 LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OptLevel),
49 Subtarget(TT, CPU, FS),
H A DAMDGPUSubtarget.h43 AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS);
/external/clang/test/CodeGenCXX/
H A Dtemp-order.cpp21 TempTracker &TT; member in struct:A
26 : TT(_TT), P(_P), Truth(_Truth) {}
27 A(const A &RHS) : TT(RHS.TT), P(RHS.P), Truth(RHS.Truth) { RHS.P = 0; }
30 TT.Product *= pow(P, ++TT.Index);
34 TT = RHS.TT;
/external/clang/test/Sema/
H A Dwarn-documentation.cpp421 // expected-warning@+1 {{template parameter 'T' not found in the template declaration}} expected-note@+1 {{did you mean 'TT'?}}
423 template<typename TT>
424 void test_tparam4(TT aaa);
426 // expected-warning@+1 {{template parameter 'T' not found in the template declaration}} expected-note@+1 {{did you mean 'TT'?}}
428 template<typename TT>
454 /// \tparam TT Bbb
455 template<template<typename T> class TT>
456 void test_tparam10(TT<int> aaa);
459 /// \tparam TT Bbb
461 template<template<template<typename T> class TT, clas
[all...]
/external/clang/test/SemaTemplate/
H A Dinstantiate-field.cpp59 template < typename TT > struct BidirectionalIterator
69 TT i;
H A Dtemp_arg_template.cpp50 template <template<typename,int> class TT, typename T, int N>
51 int operator<<(int, TT<T, N> a) { // expected-note{{candidate template ignored}}
H A Dinstantiate-function-params.cpp24 template < typename TT > struct InputIterator {
27 template < typename TT > struct ForwardIterator : InputIterator<TT> { // expected-note {{in instantiation}}
/external/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCAsmInfo.cpp67 AArch64MCAsmInfoELF::AArch64MCAsmInfoELF(StringRef TT) { argument
68 Triple T(TT);
/external/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp74 HexagonSubtarget::HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS, argument
76 : HexagonGenSubtargetInfo(TT, CPU, FS), CPUString(CPU.str()),
H A DHexagonTargetMachine.cpp67 HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT, argument
72 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
73 Subtarget(TT, CPU, FS, *this) {
/external/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsAsmBackend.cpp397 StringRef TT,
399 return new MipsAsmBackend(T, Triple(TT).getOS(),
405 StringRef TT,
407 return new MipsAsmBackend(T, Triple(TT).getOS(),
413 StringRef TT,
415 return new MipsAsmBackend(T, Triple(TT).getOS(),
421 StringRef TT,
423 return new MipsAsmBackend(T, Triple(TT).getOS(),
395 createMipsAsmBackendEL32(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument
403 createMipsAsmBackendEB32(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument
411 createMipsAsmBackendEL64(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument
419 createMipsAsmBackendEB64(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument
/external/llvm/lib/Target/Sparc/MCTargetDesc/
H A DSparcMCAsmInfo.cpp23 SparcELFMCAsmInfo::SparcELFMCAsmInfo(StringRef TT) { argument
25 Triple TheTriple(TT);
/external/llvm/lib/Target/Sparc/
H A DSparcSubtarget.cpp78 SparcSubtarget::SparcSubtarget(const std::string &TT, const std::string &CPU, argument
81 : SparcGenSubtargetInfo(TT, CPU, FS), Is64Bit(is64Bit),
/external/mesa3d/src/gallium/drivers/radeon/
H A DAMDGPUSubtarget.cpp23 AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS) : argument
24 AMDGPUGenSubtargetInfo(TT, CPU, FS), mDumpCode(false) {
H A DAMDGPUTargetMachine.h27 MCAsmInfo* createMCAsmInfo(const Target &T, StringRef TT);
41 AMDGPUTargetMachine(const Target &T, StringRef TT, StringRef FS,
H A DAMDGPUTargetMachine.cpp41 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT, argument
48 LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OptLevel),
49 Subtarget(TT, CPU, FS),
/external/llvm/lib/Target/AArch64/
H A DAArch64TargetMachine.cpp84 AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT, argument
90 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
91 Subtarget(TT, CPU, FS, *this, LittleEndian) {
98 AArch64leTargetMachine(const Target &T, StringRef TT, argument
102 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
107 AArch64beTargetMachine(const Target &T, StringRef TT, argument
111 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
/external/llvm/lib/Target/Mips/
H A DMipsSubtarget.cpp63 static StringRef selectMipsCPU(Triple TT, StringRef CPU) { argument
65 if (TT.getArch() == Triple::mips || TT.getArch() == Triple::mipsel)
105 MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU, argument
108 : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(Mips32),
117 TargetTriple(TT),
170 if (TT.find("linux") == std::string::npos)
/external/llvm/lib/Target/SystemZ/MCTargetDesc/
H A DSystemZMCTargetDesc.cpp98 StringRef TT) {
99 MCAsmInfo *MAI = new SystemZMCAsmInfo(TT);
114 static MCRegisterInfo *createSystemZMCRegisterInfo(StringRef TT) { argument
120 static MCSubtargetInfo *createSystemZMCSubtargetInfo(StringRef TT, argument
124 InitSystemZMCSubtargetInfo(X, TT, CPU, FS);
128 static MCCodeGenInfo *createSystemZMCCodeGenInfo(StringRef TT, Reloc::Model RM, argument
184 static MCStreamer *createSystemZMCObjectStreamer(const Target &T, StringRef TT, argument
/external/llvm/lib/Target/X86/
H A DX86TargetMachine.cpp34 X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT, StringRef CPU, argument
38 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
39 Subtarget(TT, CPU, FS, *this, Options.StackAlignmentOverride) {

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