/external/llvm/lib/Target/X86/ |
H A D | X86SelectionDAGInfo.cpp | 252 EVT DstVT = Dst.getValueType(); local 256 DAG.getNode(ISD::ADD, dl, DstVT, Dst, 257 DAG.getConstant(Offset, DstVT)),
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H A D | X86FastISel.cpp | 92 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT, 530 /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g. 532 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, argument 535 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, 1028 EVT DstVT = VA.getValVT(); local 1030 if (SrcVT != DstVT) { 1037 assert(DstVT == MVT::i32 && "X86 should always ext to i32"); 1047 SrcReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op, 1279 EVT DstVT = TLI.getValueType(I->getType()); local 1280 if (!TLI.isTypeLegal(DstVT)) 2087 EVT DstVT = TLI.getValueType(I->getType()); local 3150 EVT DstVT = TLI.getValueType(I->getType()); local [all...] |
H A D | X86ISelDAGToDAG.cpp | 504 MVT DstVT = N->getSimpleValueType(0); local 507 if (SrcVT.isVector() || DstVT.isVector()) 515 bool DstIsSSE = X86Lowering->isScalarFPTypeInSSEReg(DstVT); 533 MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'. 535 MemVT = SrcIsSSE ? SrcVT : DstVT; 545 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp,
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H A D | X86ISelLowering.cpp | 10905 MVT DstVT = Op.getSimpleValueType(); 10906 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64) 10910 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32) 10976 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0)); 15999 MVT DstVT = Op.getSimpleValueType(); 16003 if (DstVT != MVT::f64) 16033 assert((DstVT == MVT::i64 || 16034 (DstVT.isVector() && DstVT.getSizeInBits()==64)) && 16037 if (SrcVT==MVT::i64 && DstVT [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | FastISel.cpp | 840 EVT DstVT = TLI.getValueType(I->getType()); local 843 DstVT == MVT::Other || !DstVT.isSimple()) 848 if (!TLI.isTypeLegal(DstVT)) 863 DstVT.getSimpleVT(), 892 MVT DstVT = DstEVT.getSimpleVT(); local 902 if (SrcVT == DstVT) { 904 const TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT); 915 ResultReg = FastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill); 1187 EVT DstVT local [all...] |
H A D | LegalizeIntegerTypes.cpp | 2693 EVT DstVT = N->getValueType(0); local 2694 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT); 2697 return TLI.makeLibCall(DAG, LC, DstVT, &Op, 1, true, SDLoc(N)).first; 2797 EVT DstVT = N->getValueType(0); local 2801 // treated as signed) is representable in DstVT. Check that the mantissa 2802 // size of DstVT is >= than the number of bits in SrcVT -1. 2803 const fltSemantics &sem = DAG.EVTToAPFloatSemantics(DstVT); 2807 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op); 2854 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(), 2859 return DAG.getNode(ISD::FADD, dl, DstVT, SignedCon [all...] |
/external/llvm/lib/Transforms/Scalar/ |
H A D | Scalarizer.cpp | 477 VectorType *DstVT = dyn_cast<VectorType>(BCI.getDestTy()); local 479 if (!DstVT || !SrcVT) 482 unsigned DstNumElems = DstVT->getNumElements(); 491 Res[I] = Builder.CreateBitCast(Op0[I], DstVT->getElementType(), 497 Type *MidTy = VectorType::get(DstVT->getElementType(), FanOut); 523 Res[ResI] = Builder.CreateBitCast(V, DstVT->getElementType(),
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCFastISel.cpp | 918 MVT DstVT; local 920 if (!isTypeLegal(DstTy, DstVT)) 923 if (DstVT != MVT::f32 && DstVT != MVT::f64) 951 if (DstVT == MVT::f32 && !PPCSubTarget->hasFPCVT()) 973 if (DstVT == MVT::f32) 1025 MVT DstVT, SrcVT; local 1027 if (!isTypeLegal(DstTy, DstVT)) 1030 if (DstVT != MVT::i32 && DstVT ! [all...] |
/external/llvm/lib/CodeGen/ |
H A D | CodeGenPrepare.cpp | 539 EVT DstVT = TLI.getValueType(CI->getType()); local 542 if (SrcVT.isInteger() != DstVT.isInteger()) 547 if (SrcVT.bitsLT(DstVT)) return false; 555 if (TLI.getTypeAction(CI->getContext(), DstVT) == 557 DstVT = TLI.getTypeToTransformTo(CI->getContext(), DstVT); 560 if (SrcVT != DstVT)
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelDAGToDAG.cpp | 904 EVT DstVT = N->getValueType(0); local 927 DstVT = MVT::i32; 931 if (DstVT == MVT::i64) 937 InsertTo64 = DstVT == MVT::i64; 940 DstVT = MVT::i32; 944 if (DstVT == MVT::i64) 950 InsertTo64 = DstVT == MVT::i64; 953 DstVT = MVT::i32; 969 SDNode *Res = CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i64, DstVT,
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/external/llvm/lib/Target/ARM/ |
H A D | ARMFastISel.cpp | 1552 MVT DstVT; 1554 if (!isTypeLegal(Ty, DstVT)) 1585 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT)); 1596 MVT DstVT; 1598 if (!isTypeLegal(RetTy, DstVT)) 1617 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
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H A D | ARMISelLowering.cpp | 3953 EVT DstVT = N->getValueType(0); local 3954 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) && 3958 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) { 3963 return DAG.getNode(ISD::BITCAST, dl, DstVT, 3968 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
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