Searched refs:RS (Results 1 - 25 of 119) sorted by relevance

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/external/valgrind/main/none/tests/mips64/
H A Dmacro_int.h1 #define TEST1(instruction, RSval, RTval, RD, RS, RT) \
5 "move $"#RS", %1" "\n\t" \
12 : #RD, #RS, #RT \
19 #define TEST2(instruction, RSval, imm, RT, RS) \
23 "move $"#RS", %1" "\n\t" \
29 : #RT, #RS \
35 #define TEST3(instruction, RSval, RD, RS) \
39 "move $"#RS", %1" "\n\t" \
45 : #RD, #RS \
51 #define TEST4(instruction, RSval, RTval, RS, R
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H A Dbranch_and_jump_instructions.c107 #define TEST3(instruction, RDval, RSval, RTval, RD, RS, RT) \
112 "move $"#RS", %1" "\n\t" \
115 instruction" $"#RS", $"#RT", end"instruction#RDval "\n\t" \
124 : #RD, #RS, #RT \
130 #define TEST4(instruction, RDval, RSval, RD, RS) \
135 "move $"#RS", %1" "\n\t" \
137 instruction" $"#RS", end"instruction#RDval "\n\t" \
146 : #RD, #RS \
152 #define TEST5(instruction, RDval, RSval, RD, RS) \
158 "move $"#RS",
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H A Dbranches.c130 #define TESTINST4(instruction, RDval, RSval, RTval, RD, RS, RT) \
135 "move $"#RS", %1" "\n\t" \
138 instruction" $"#RS", $"#RT", end"instruction#RDval "\n\t" \
147 : #RD, #RS, #RT \
153 #define TESTINST5(instruction, RDval, RSval, RD, RS) \
158 "move $"#RS", %1" "\n\t" \
160 instruction" $"#RS", end"instruction#RDval "\n\t" \
169 : #RD, #RS \
175 #define TESTINST6(instruction, RDval, RSval, RD, RS) \
181 "move $"#RS",
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H A Dcvm_ins.c70 #define TESTINST1(instruction, RSVal, RT, RS, p, lenm1) \
75 "move $" #RS ", %1" "\n\t" \
80 : #RS, #RT, "cc", "memory" \
85 #define TESTINST2(instruction, RSVal, RTval, RD, RS, RT) \
90 "move $" #RS ", %1" "\n\t" \
96 : #RD, #RS, #RT, "cc", "memory" \
101 #define TESTINST3(instruction, RSVal, RT, RS,imm) \
106 "move $" #RS ", %1" "\n\t" \
111 : #RS, #RT, "cc", "memory" \
H A Dload_store_multiple.c23 #define TESTINST1(instruction, RTval, offset, RT, RS) \
27 "move $"#RS", %1" "\n\t" \
30 "lw %0, "#offset"($"#RS")" "\n\t" \
33 : #RT, #RS \
39 "move $"#RS", %1" "\n\t" \
42 "lw %0, "#offset"($"#RS")" "\n\t" \
45 : #RT, #RS \
53 #define TESTINSTsw(RTval, offset, RT, RS) \
57 "move $"#RS", %1" "\n\t" \
58 "daddiu $"#RS",
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/external/llvm/lib/DebugInfo/
H A DDWARFCompileUnit.h19 DWARFCompileUnit(const DWARFDebugAbbrev *DA, StringRef IS, StringRef RS, argument
22 : DWARFUnit(DA, IS, RS, SS, SOS, AOS, M, LE) {}
H A DDWARFTypeUnit.h22 DWARFTypeUnit(const DWARFDebugAbbrev *DA, StringRef IS, StringRef RS, argument
25 : DWARFUnit(DA, IS, RS, SS, SOS, AOS, M, LE) {}
/external/qemu/disas/
H A Dppc.c84 /* Opcode is defined for the POWER (RS/6000) architecture. */
729 the RS field in the instruction. This is used for extended
734 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
737 #define RS RBS + 1
738 #define RT RS
742 /* The RS and RT fields of the DS form stq instruction, which have
744 #define RSQ RS + 1
748 /* The RS field of the tlbwe instruction, which is optional. */
1455 the RS field in the instruction. This is used for extended
2153 { "efscfd", VX(4, 719), VX_MASK, PPCEFS, { RS, R
733 #define RS macro
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/external/llvm/lib/Target/PowerPC/
H A DPPCJITInfo.cpp33 #define BUILD_ADDIS(RD,RS,IMM16) \
34 ((15 << 26) | ((RD) << 21) | ((RS) << 16) | ((IMM16) & 65535))
35 #define BUILD_ORI(RD,RS,UIMM16) \
36 ((24 << 26) | ((RS) << 21) | ((RD) << 16) | ((UIMM16) & 65535))
37 #define BUILD_ORIS(RD,RS,UIMM16) \
38 ((25 << 26) | ((RS) << 21) | ((RD) << 16) | ((UIMM16) & 65535))
39 #define BUILD_RLDICR(RD,RS,SH,ME) \
40 ((30 << 26) | ((RS) << 21) | ((RD) << 16) | (((SH) & 31) << 11) | \
42 #define BUILD_MTSPR(RS,SPR) \
43 ((31 << 26) | ((RS) << 2
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H A DPPCFrameLowering.h44 RegScavenger *RS = nullptr) const override;
46 RegScavenger *RS = nullptr) const override;
47 void addScavengingSpillSlot(MachineFunction &MF, RegScavenger *RS) const;
/external/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.h47 RegScavenger *RS = nullptr) const override;
50 RegScavenger *RS = nullptr) const;
/external/llvm/lib/Target/XCore/
H A DXCoreFrameLowering.h50 RegScavenger *RS = nullptr) const override;
53 RegScavenger *RS = nullptr) const override;
H A DXCoreRegisterInfo.h45 RegScavenger *RS = nullptr) const override;
H A DXCoreRegisterInfo.cpp95 int Offset, RegScavenger *RS ) {
96 assert(RS && "requiresRegisterScavenging failed");
100 unsigned ScratchOffset = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0);
101 RS->setUsed(ScratchOffset);
163 unsigned Reg, int Offset, RegScavenger *RS ) {
164 assert(RS && "requiresRegisterScavenging failed");
172 ScratchBase = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0);
173 RS->setUsed(ScratchBase);
177 unsigned ScratchOffset = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0);
178 RS
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DAMDGPURegisterInfo.cpp40 RegScavenger *RS) const {
H A DAMDGPURegisterInfo.h55 RegScavenger *RS) const;
/external/llvm/lib/Target/MSP430/
H A DMSP430RegisterInfo.h39 RegScavenger *RS = nullptr) const override;
/external/mesa3d/src/gallium/drivers/radeon/
H A DAMDGPURegisterInfo.cpp40 RegScavenger *RS) const {
/external/clang/lib/StaticAnalyzer/Checkers/
H A DReturnPointerRangeChecker.cpp31 void checkPreStmt(const ReturnStmt *RS, CheckerContext &C) const;
35 void ReturnPointerRangeChecker::checkPreStmt(const ReturnStmt *RS, argument
39 const Expr *RetE = RS->getRetValue();
H A DReturnUndefChecker.cpp35 void checkPreStmt(const ReturnStmt *RS, CheckerContext &C) const;
39 void ReturnUndefChecker::checkPreStmt(const ReturnStmt *RS, argument
41 const Expr *RetE = RS->getRetValue();
/external/llvm/lib/Target/Hexagon/
H A DHexagonFixupHwLoops.cpp67 RegScavenger &RS);
121 RegScavenger RS; local
127 RS.enterBasicBlock(MBB);
134 RS.forward(MII);
141 convertLoopInstr(MF, MII, RS);
162 RegScavenger &RS) {
166 unsigned Scratch = RS.scavengeRegister(&Hexagon::IntRegsRegClass, MII, 0);
160 convertLoopInstr(MachineFunction &MF, MachineBasicBlock::iterator &MII, RegScavenger &RS) argument
H A DHexagonRegisterInfo.h61 RegScavenger *RS = nullptr) const override;
/external/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.h64 RegScavenger *RS = nullptr) const override;
67 RegScavenger *RS = nullptr) const;
/external/llvm/lib/Target/SystemZ/
H A DSystemZFrameLowering.h31 RegScavenger *RS) const override;
42 RegScavenger *RS) const override;
/external/llvm/lib/CodeGen/
H A DPrologEpilogInserter.h48 RegScavenger *RS; member in class:llvm::PEI

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