Searched refs:SubReg1 (Results 1 - 5 of 5) sorted by relevance

/external/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp197 unsigned Src1 = 0, SubReg1; local
215 Src1 = getSrcFromCopy(&*Def, MRI, SubReg1);
290 unsigned Src1 = 0, SubReg1; local
308 Src1 = getSrcFromCopy(&*Def, MRI, SubReg1);
325 SubReg1 = 0;
340 .addReg(Src1, getKillRegState(true), SubReg1);
/external/llvm/lib/Target/R600/
H A DAMDGPUISelDAGToDAG.cpp337 SDValue RC, SubReg0, SubReg1; local
344 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, MVT::i32);
348 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32);
353 N->getOperand(1), SubReg1 };
/external/llvm/lib/CodeGen/
H A DTargetInstrInfo.cpp140 unsigned SubReg1 = MI->getOperand(Idx1).getSubReg(); local
155 SubReg0 = SubReg1;
170 MI->getOperand(Idx2).setSubReg(SubReg1);
/external/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp1569 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::gsub_1, MVT::i32); local
1570 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1580 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32); local
1581 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1590 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32); local
1591 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1600 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32); local
1601 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1612 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32); local
1615 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1626 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32); local
1640 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32); local
[all...]
/external/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp253 unsigned SubReg1 = MI->getOperand(1).getSubReg(); local
264 assert(MI->getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch");
291 MI->getOperand(2).setSubReg(SubReg1);

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