Searched refs:base_reg (Results 1 - 22 of 22) sorted by relevance

/external/chromium_org/v8/src/x64/
H A Dcodegen-x64.h57 Register base_reg,
62 : base_reg_(base_reg),
70 Register base_reg,
75 : base_reg_(base_reg),
83 Register base_reg,
88 : base_reg_(base_reg),
56 StackArgumentsAccessor( Register base_reg, int argument_count_immediate, StackArgumentsAccessorReceiverMode receiver_mode = ARGUMENTS_CONTAIN_RECEIVER, int extra_displacement_to_last_argument = 0) argument
69 StackArgumentsAccessor( Register base_reg, Register argument_count_reg, StackArgumentsAccessorReceiverMode receiver_mode = ARGUMENTS_CONTAIN_RECEIVER, int extra_displacement_to_last_argument = 0) argument
82 StackArgumentsAccessor( Register base_reg, const ParameterCount& parameter_count, StackArgumentsAccessorReceiverMode receiver_mode = ARGUMENTS_CONTAIN_RECEIVER, int extra_displacement_to_last_argument = 0) argument
H A Ddisasm-x64.cc340 int base_reg(int low_bits) { return low_bits | ((rex_ & 0x01) << 3); } function in class:disasm::DisassemblerX64
1423 NameOfCPURegister(base_reg(current & 0x07)));
1429 NameOfCPURegister(base_reg(current & 0x07)));
1453 NameOfCPURegister(base_reg(current & 0x07)),
H A Dmacro-assembler-x64.cc739 Register base_reg = r15; local
740 Move(base_reg, next_address);
741 movp(prev_next_address_reg, Operand(base_reg, kNextOffset));
742 movp(prev_limit_reg, Operand(base_reg, kLimitOffset));
743 addl(Operand(base_reg, kLevelOffset), Immediate(1));
790 subl(Operand(base_reg, kLevelOffset), Immediate(1));
791 movp(Operand(base_reg, kNextOffset), prev_next_address_reg);
792 cmpp(prev_limit_reg, Operand(base_reg, kLimitOffset));
853 movp(Operand(base_reg, kLimitOffset), prev_limit_reg);
H A Dassembler-x64.cc158 int base_reg = (has_sib ? operand.buf_[1] : modrm) & 0x07;
161 bool is_baseless = (mode == 0) && (base_reg == 0x05); // No base or RIP base.
181 } else if (disp_value != 0 || (base_reg == 0x05)) {
/external/lldb/include/lldb/Core/
H A DEmulateInstruction.h190 RegisterInfo base_reg; // base register number member in struct:lldb_private::EmulateInstruction::Context::__anon25225::RegisterPlusIndirectOffset
197 RegisterInfo base_reg; // base register for address calculation member in struct:lldb_private::EmulateInstruction::Context::__anon25225::RegisterToRegisterPlusOffset
203 RegisterInfo base_reg; // base register for address calculation member in struct:lldb_private::EmulateInstruction::Context::__anon25225::RegisterToRegisterPlusIndirectOffset
246 SetRegisterPlusOffset (RegisterInfo base_reg, argument
250 info.RegisterPlusOffset.reg = base_reg;
255 SetRegisterPlusIndirectOffset (RegisterInfo base_reg, argument
259 info.RegisterPlusIndirectOffset.base_reg = base_reg;
265 RegisterInfo base_reg,
270 info.RegisterToRegisterPlusOffset.base_reg
264 SetRegisterToRegisterPlusOffset(RegisterInfo data_reg, RegisterInfo base_reg, int64_t offset) argument
275 SetRegisterToRegisterPlusIndirectOffset(RegisterInfo base_reg, RegisterInfo offset_reg, RegisterInfo data_reg) argument
[all...]
/external/chromium_org/third_party/mesa/src/src/mesa/program/
H A Dregister_allocate.h44 unsigned int base_reg, unsigned int reg);
H A Dregister_allocate.c210 * Adds a conflict between base_reg and reg, and also between reg and
211 * anything that base_reg conflicts with.
219 unsigned int base_reg, unsigned int reg)
223 ra_add_reg_conflict(regs, reg, base_reg);
225 for (i = 0; i < regs->regs[base_reg].num_conflicts; i++) {
226 ra_add_reg_conflict(regs, reg, regs->regs[base_reg].conflict_list[i]);
218 ra_add_transitive_reg_conflict(struct ra_regs *regs, unsigned int base_reg, unsigned int reg) argument
/external/mesa3d/src/mesa/program/
H A Dregister_allocate.h44 unsigned int base_reg, unsigned int reg);
H A Dregister_allocate.c210 * Adds a conflict between base_reg and reg, and also between reg and
211 * anything that base_reg conflicts with.
219 unsigned int base_reg, unsigned int reg)
223 ra_add_reg_conflict(regs, reg, base_reg);
225 for (i = 0; i < regs->regs[base_reg].num_conflicts; i++) {
226 ra_add_reg_conflict(regs, reg, regs->regs[base_reg].conflict_list[i]);
218 ra_add_transitive_reg_conflict(struct ra_regs *regs, unsigned int base_reg, unsigned int reg) argument
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/
H A Dbrw_vec4_reg_allocate.cpp131 for (int base_reg = j;
132 base_reg < j + class_sizes[i];
133 base_reg++) {
134 ra_add_transitive_reg_conflict(brw->vs.regs, base_reg, reg);
H A Dbrw_fs_reg_allocate.cpp119 for (int base_reg = j;
120 base_reg < j + class_sizes[i];
121 base_reg++) {
122 ra_add_transitive_reg_conflict(brw->wm.regs, base_reg, reg);
H A Dbrw_blorp_blit.cpp493 void alloc_push_const_regs(int base_reg);
743 brw_blorp_blit_program::alloc_push_const_regs(int base_reg) argument
748 brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, base_reg, CONST_LOC(name) / 2)
H A Dbrw_wm_emit.c1323 GLuint base_reg,
1343 brw_message_reg(base_reg + 1),
1357 base_reg,
1322 fire_fb_write( struct brw_wm_compile *c, GLuint base_reg, GLuint nr, GLuint target, GLuint eot ) argument
/external/mesa3d/src/mesa/drivers/dri/i965/
H A Dbrw_vec4_reg_allocate.cpp131 for (int base_reg = j;
132 base_reg < j + class_sizes[i];
133 base_reg++) {
134 ra_add_transitive_reg_conflict(brw->vs.regs, base_reg, reg);
H A Dbrw_fs_reg_allocate.cpp119 for (int base_reg = j;
120 base_reg < j + class_sizes[i];
121 base_reg++) {
122 ra_add_transitive_reg_conflict(brw->wm.regs, base_reg, reg);
H A Dbrw_blorp_blit.cpp493 void alloc_push_const_regs(int base_reg);
743 brw_blorp_blit_program::alloc_push_const_regs(int base_reg) argument
748 brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, base_reg, CONST_LOC(name) / 2)
H A Dbrw_wm_emit.c1323 GLuint base_reg,
1343 brw_message_reg(base_reg + 1),
1357 base_reg,
1322 fire_fb_write( struct brw_wm_compile *c, GLuint base_reg, GLuint nr, GLuint target, GLuint eot ) argument
/external/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.cpp3964 RegisterInfo base_reg; local
3965 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rn, base_reg);
3970 ctx.SetRegisterPlusOffset (base_reg, (int32_t) (offset_addr - base));
3979 context.SetRegisterPlusOffset (base_reg, (int32_t) (offset_addr - base));
4097 RegisterInfo base_reg; local
4098 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
4122 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, offset);
4222 RegisterInfo base_reg; local
4223 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
4247 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, R
4373 RegisterInfo base_reg; local
4498 RegisterInfo base_reg; local
4687 RegisterInfo base_reg; local
4887 RegisterInfo base_reg; local
5017 RegisterInfo base_reg; local
5185 RegisterInfo base_reg; local
5200 RegisterInfo base_reg; local
5855 RegisterInfo base_reg; local
6062 RegisterInfo base_reg; local
6235 RegisterInfo base_reg; local
6473 RegisterInfo base_reg; local
6611 RegisterInfo base_reg; local
6725 RegisterInfo base_reg; local
6892 RegisterInfo base_reg; local
7053 RegisterInfo base_reg; local
7152 RegisterInfo base_reg; local
7299 RegisterInfo base_reg; local
7450 RegisterInfo base_reg; local
7564 RegisterInfo base_reg; local
7728 RegisterInfo base_reg; local
8207 RegisterInfo base_reg; local
9822 RegisterInfo base_reg; local
10022 RegisterInfo base_reg; local
10170 RegisterInfo base_reg; local
10422 RegisterInfo base_reg; local
10551 RegisterInfo base_reg; local
10720 RegisterInfo base_reg; local
10913 RegisterInfo base_reg; local
11067 RegisterInfo base_reg; local
11205 RegisterInfo base_reg; local
11376 RegisterInfo base_reg; local
11548 RegisterInfo base_reg; local
11715 RegisterInfo base_reg; local
11887 RegisterInfo base_reg; local
12013 RegisterInfo base_reg; local
[all...]
/external/qemu/
H A Dgdbstub.c260 int base_reg; member in struct:GDBRegisterState
1393 if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
1394 return r->get_reg(env, mem_buf, reg - r->base_reg);
1409 if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
1410 return r->set_reg(env, mem_buf, reg - r->base_reg);
1431 s->base_reg = last_reg;
1447 if (g_pos != s->base_reg) {
1449 "Expected %d got %d\n", xml, g_pos, s->base_reg);
[all...]
/external/lldb/source/Core/
H A DEmulateInstruction.cpp516 info.RegisterPlusIndirectOffset.base_reg.name,
524 info.RegisterToRegisterPlusOffset.base_reg.name,
533 info.RegisterToRegisterPlusIndirectOffset.base_reg.name,
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/radeon/
H A Dradeon_state_init.c423 uint32_t base_reg; local
435 case 1: base_reg = RADEON_PP_CUBIC_OFFSET_T1_0; break;
436 case 2: base_reg = RADEON_PP_CUBIC_OFFSET_T2_0; break;
438 case 0: base_reg = RADEON_PP_CUBIC_OFFSET_T0_0; break;
444 OUT_BATCH(CP_PACKET0(base_reg + (4 * j), 0));
/external/mesa3d/src/mesa/drivers/dri/radeon/
H A Dradeon_state_init.c423 uint32_t base_reg; local
435 case 1: base_reg = RADEON_PP_CUBIC_OFFSET_T1_0; break;
436 case 2: base_reg = RADEON_PP_CUBIC_OFFSET_T2_0; break;
438 case 0: base_reg = RADEON_PP_CUBIC_OFFSET_T0_0; break;
444 OUT_BATCH(CP_PACKET0(base_reg + (4 * j), 0));

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