DAGCombiner.cpp revision 03fa6ea4025d9c658badc5670413e02e4eefc2f2
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Nate Begeman and is distributed under the 6// University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// FIXME: Missing folds 14// sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into 15// a sequence of multiplies, shifts, and adds. This should be controlled by 16// some kind of hint from the target that int div is expensive. 17// various folds of mulh[s,u] by constants such as -1, powers of 2, etc. 18// 19// FIXME: select C, pow2, pow2 -> something smart 20// FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z) 21// FIXME: Dead stores -> nuke 22// FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!) 23// FIXME: mul (x, const) -> shifts + adds 24// FIXME: undef values 25// FIXME: divide by zero is currently left unfolded. do we want to turn this 26// into an undef? 27// FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false 28// 29//===----------------------------------------------------------------------===// 30 31#define DEBUG_TYPE "dagcombine" 32#include "llvm/ADT/Statistic.h" 33#include "llvm/Analysis/AliasAnalysis.h" 34#include "llvm/CodeGen/SelectionDAG.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/MathExtras.h" 37#include "llvm/Target/TargetLowering.h" 38#include "llvm/Support/Compiler.h" 39#include "llvm/Support/CommandLine.h" 40#include <algorithm> 41#include <cmath> 42#include <iostream> 43#include <algorithm> 44using namespace llvm; 45 46namespace { 47 static Statistic<> NodesCombined ("dagcombiner", 48 "Number of dag nodes combined"); 49 50 static Statistic<> PreIndexedNodes ("pre_indexed_ops", 51 "Number of pre-indexed nodes created"); 52 static Statistic<> PostIndexedNodes ("post_indexed_ops", 53 "Number of post-indexed nodes created"); 54 55 static cl::opt<bool> 56 CombinerAA("combiner-alias-analysis", cl::Hidden, 57 cl::desc("Turn on alias analysis during testing")); 58 59 static cl::opt<bool> 60 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 61 cl::desc("Include global information in alias analysis")); 62 63//------------------------------ DAGCombiner ---------------------------------// 64 65 class VISIBILITY_HIDDEN DAGCombiner { 66 SelectionDAG &DAG; 67 TargetLowering &TLI; 68 bool AfterLegalize; 69 70 // Worklist of all of the nodes that need to be simplified. 71 std::vector<SDNode*> WorkList; 72 73 // AA - Used for DAG load/store alias analysis. 74 AliasAnalysis &AA; 75 76 /// AddUsersToWorkList - When an instruction is simplified, add all users of 77 /// the instruction to the work lists because they might get more simplified 78 /// now. 79 /// 80 void AddUsersToWorkList(SDNode *N) { 81 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 82 UI != UE; ++UI) 83 AddToWorkList(*UI); 84 } 85 86 /// removeFromWorkList - remove all instances of N from the worklist. 87 /// 88 void removeFromWorkList(SDNode *N) { 89 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 90 WorkList.end()); 91 } 92 93 public: 94 /// AddToWorkList - Add to the work list making sure it's instance is at the 95 /// the back (next to be processed.) 96 void AddToWorkList(SDNode *N) { 97 removeFromWorkList(N); 98 WorkList.push_back(N); 99 } 100 101 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo, 102 bool AddTo = true) { 103 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 104 ++NodesCombined; 105 DEBUG(std::cerr << "\nReplacing.1 "; N->dump(); 106 std::cerr << "\nWith: "; To[0].Val->dump(&DAG); 107 std::cerr << " and " << NumTo-1 << " other values\n"); 108 std::vector<SDNode*> NowDead; 109 DAG.ReplaceAllUsesWith(N, To, &NowDead); 110 111 if (AddTo) { 112 // Push the new nodes and any users onto the worklist 113 for (unsigned i = 0, e = NumTo; i != e; ++i) { 114 AddToWorkList(To[i].Val); 115 AddUsersToWorkList(To[i].Val); 116 } 117 } 118 119 // Nodes can be reintroduced into the worklist. Make sure we do not 120 // process a node that has been replaced. 121 removeFromWorkList(N); 122 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 123 removeFromWorkList(NowDead[i]); 124 125 // Finally, since the node is now dead, remove it from the graph. 126 DAG.DeleteNode(N); 127 return SDOperand(N, 0); 128 } 129 130 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) { 131 return CombineTo(N, &Res, 1, AddTo); 132 } 133 134 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1, 135 bool AddTo = true) { 136 SDOperand To[] = { Res0, Res1 }; 137 return CombineTo(N, To, 2, AddTo); 138 } 139 private: 140 141 /// SimplifyDemandedBits - Check the specified integer node value to see if 142 /// it can be simplified or if things it uses can be simplified by bit 143 /// propagation. If so, return true. 144 bool SimplifyDemandedBits(SDOperand Op) { 145 TargetLowering::TargetLoweringOpt TLO(DAG); 146 uint64_t KnownZero, KnownOne; 147 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType()); 148 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 149 return false; 150 151 // Revisit the node. 152 AddToWorkList(Op.Val); 153 154 // Replace the old value with the new one. 155 ++NodesCombined; 156 DEBUG(std::cerr << "\nReplacing.2 "; TLO.Old.Val->dump(); 157 std::cerr << "\nWith: "; TLO.New.Val->dump(&DAG); 158 std::cerr << '\n'); 159 160 std::vector<SDNode*> NowDead; 161 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead); 162 163 // Push the new node and any (possibly new) users onto the worklist. 164 AddToWorkList(TLO.New.Val); 165 AddUsersToWorkList(TLO.New.Val); 166 167 // Nodes can end up on the worklist more than once. Make sure we do 168 // not process a node that has been replaced. 169 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 170 removeFromWorkList(NowDead[i]); 171 172 // Finally, if the node is now dead, remove it from the graph. The node 173 // may not be dead if the replacement process recursively simplified to 174 // something else needing this node. 175 if (TLO.Old.Val->use_empty()) { 176 removeFromWorkList(TLO.Old.Val); 177 DAG.DeleteNode(TLO.Old.Val); 178 } 179 return true; 180 } 181 182 /// CombineToPreIndexedLoadStore - Try turning a load / store and a 183 /// pre-indexed load / store when the base pointer is a add or subtract 184 /// and it has other uses besides the load / store. After the 185 /// transformation, the new indexed load / store has effectively folded 186 /// the add / subtract in and all of its other uses are redirected to the 187 /// new load / store. 188 bool CombineToPreIndexedLoadStore(SDNode *N) { 189 if (!AfterLegalize) 190 return false; 191 192 bool isLoad = true; 193 SDOperand Ptr; 194 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 195 Ptr = LD->getBasePtr(); 196 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 197 Ptr = ST->getBasePtr(); 198 isLoad = false; 199 } else 200 return false; 201 202 if ((Ptr.getOpcode() == ISD::ADD || Ptr.getOpcode() == ISD::SUB) && 203 Ptr.Val->use_size() > 1) { 204 SDOperand BasePtr; 205 SDOperand Offset; 206 ISD::MemOpAddrMode AM = ISD::UNINDEXED; 207 if (TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) { 208 // Try turning it into a pre-indexed load / store except when 209 // 1) Another use of base ptr is a predecessor of N. If ptr is folded 210 // that would create a cycle. 211 // 2) All uses are load / store ops that use it as base ptr. 212 213 // Now check for #1 and #2. 214 bool RealUse = false; 215 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 216 E = Ptr.Val->use_end(); I != E; ++I) { 217 SDNode *Use = *I; 218 if (Use == N) 219 continue; 220 if (Use->isPredecessor(N)) 221 return false; 222 223 if (!((Use->getOpcode() == ISD::LOAD && 224 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 225 (Use->getOpcode() == ISD::STORE) && 226 cast<StoreSDNode>(Use)->getBasePtr() == Ptr)) 227 RealUse = true; 228 } 229 if (!RealUse) 230 return false; 231 232 SDOperand Result = isLoad 233 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM) 234 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 235 ++PreIndexedNodes; 236 ++NodesCombined; 237 DEBUG(std::cerr << "\nReplacing.4 "; N->dump(); 238 std::cerr << "\nWith: "; Result.Val->dump(&DAG); 239 std::cerr << '\n'); 240 std::vector<SDNode*> NowDead; 241 if (isLoad) { 242 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 243 NowDead); 244 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 245 NowDead); 246 } else { 247 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 248 NowDead); 249 } 250 251 // Nodes can end up on the worklist more than once. Make sure we do 252 // not process a node that has been replaced. 253 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 254 removeFromWorkList(NowDead[i]); 255 // Finally, since the node is now dead, remove it from the graph. 256 DAG.DeleteNode(N); 257 258 // Replace the uses of Ptr with uses of the updated base value. 259 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 260 NowDead); 261 removeFromWorkList(Ptr.Val); 262 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 263 removeFromWorkList(NowDead[i]); 264 DAG.DeleteNode(Ptr.Val); 265 266 return true; 267 } 268 } 269 return false; 270 } 271 272 /// CombineToPostIndexedLoadStore - Try combine a load / store with a 273 /// add / sub of the base pointer node into a post-indexed load / store. 274 /// The transformation folded the add / subtract into the new indexed 275 /// load / store effectively and all of its uses are redirected to the 276 /// new load / store. 277 bool CombineToPostIndexedLoadStore(SDNode *N) { 278 if (!AfterLegalize) 279 return false; 280 281 bool isLoad = true; 282 SDOperand Ptr; 283 MVT::ValueType VT; 284 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 285 Ptr = LD->getBasePtr(); 286 VT = LD->getLoadedVT(); 287 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 288 Ptr = ST->getBasePtr(); 289 VT = ST->getStoredVT(); 290 isLoad = false; 291 } else 292 return false; 293 294 if (Ptr.Val->use_size() > 1) { 295 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 296 E = Ptr.Val->use_end(); I != E; ++I) { 297 SDNode *Op = *I; 298 if (Op == N || 299 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 300 continue; 301 302 SDOperand BasePtr; 303 SDOperand Offset; 304 ISD::MemOpAddrMode AM = ISD::UNINDEXED; 305 if (TLI.getPostIndexedAddressParts(Op, VT, BasePtr, Offset, AM,DAG) && 306 BasePtr == Ptr) { 307 // Try turning it into a post-indexed load / store except when 308 // 1) Op must be independent of N, i.e. Op is neither a predecessor 309 // nor a successor of N. Otherwise, if Op is folded that would 310 // create a cycle. 311 // 2) All uses are load / store ops that use it as base ptr. 312 313 // Check for #3. 314 bool TryNext = false; 315 for (SDNode::use_iterator II = BasePtr.Val->use_begin(), 316 EE = BasePtr.Val->use_end(); II != EE; ++II) { 317 SDNode *Use = *II; 318 if (Use == Ptr.Val) 319 continue; 320 321 // If all the uses are load / store addresses, then don't do the 322 // transformation. 323 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 324 bool RealUse = false; 325 for (SDNode::use_iterator III = Use->use_begin(), 326 EEE = Use->use_end(); III != EEE; ++III) { 327 SDNode *UseUse = *III; 328 if (!((UseUse->getOpcode() == ISD::LOAD && 329 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) || 330 (UseUse->getOpcode() == ISD::STORE) && 331 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use)) 332 RealUse = true; 333 } 334 335 if (!RealUse) { 336 TryNext = true; 337 break; 338 } 339 } 340 } 341 if (TryNext) 342 continue; 343 344 // Check for #1 345 if (!Op->isPredecessor(N) && !N->isPredecessor(Op)) { 346 SDOperand Result = isLoad 347 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM) 348 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 349 ++PostIndexedNodes; 350 ++NodesCombined; 351 DEBUG(std::cerr << "\nReplacing.5 "; N->dump(); 352 std::cerr << "\nWith: "; Result.Val->dump(&DAG); 353 std::cerr << '\n'); 354 std::vector<SDNode*> NowDead; 355 if (isLoad) { 356 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 357 NowDead); 358 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 359 NowDead); 360 } else { 361 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 362 NowDead); 363 } 364 365 // Nodes can end up on the worklist more than once. Make sure we do 366 // not process a node that has been replaced. 367 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 368 removeFromWorkList(NowDead[i]); 369 // Finally, since the node is now dead, remove it from the graph. 370 DAG.DeleteNode(N); 371 372 // Replace the uses of Use with uses of the updated base value. 373 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0), 374 Result.getValue(isLoad ? 1 : 0), 375 NowDead); 376 removeFromWorkList(Op); 377 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 378 removeFromWorkList(NowDead[i]); 379 DAG.DeleteNode(Op); 380 381 return true; 382 } 383 } 384 } 385 } 386 return false; 387 } 388 389 /// visit - call the node-specific routine that knows how to fold each 390 /// particular type of node. 391 SDOperand visit(SDNode *N); 392 393 // Visitation implementation - Implement dag node combining for different 394 // node types. The semantics are as follows: 395 // Return Value: 396 // SDOperand.Val == 0 - No change was made 397 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 398 // otherwise - N should be replaced by the returned Operand. 399 // 400 SDOperand visitTokenFactor(SDNode *N); 401 SDOperand visitADD(SDNode *N); 402 SDOperand visitSUB(SDNode *N); 403 SDOperand visitMUL(SDNode *N); 404 SDOperand visitSDIV(SDNode *N); 405 SDOperand visitUDIV(SDNode *N); 406 SDOperand visitSREM(SDNode *N); 407 SDOperand visitUREM(SDNode *N); 408 SDOperand visitMULHU(SDNode *N); 409 SDOperand visitMULHS(SDNode *N); 410 SDOperand visitAND(SDNode *N); 411 SDOperand visitOR(SDNode *N); 412 SDOperand visitXOR(SDNode *N); 413 SDOperand visitVBinOp(SDNode *N, ISD::NodeType IntOp, ISD::NodeType FPOp); 414 SDOperand visitSHL(SDNode *N); 415 SDOperand visitSRA(SDNode *N); 416 SDOperand visitSRL(SDNode *N); 417 SDOperand visitCTLZ(SDNode *N); 418 SDOperand visitCTTZ(SDNode *N); 419 SDOperand visitCTPOP(SDNode *N); 420 SDOperand visitSELECT(SDNode *N); 421 SDOperand visitSELECT_CC(SDNode *N); 422 SDOperand visitSETCC(SDNode *N); 423 SDOperand visitSIGN_EXTEND(SDNode *N); 424 SDOperand visitZERO_EXTEND(SDNode *N); 425 SDOperand visitANY_EXTEND(SDNode *N); 426 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 427 SDOperand visitTRUNCATE(SDNode *N); 428 SDOperand visitBIT_CONVERT(SDNode *N); 429 SDOperand visitVBIT_CONVERT(SDNode *N); 430 SDOperand visitFADD(SDNode *N); 431 SDOperand visitFSUB(SDNode *N); 432 SDOperand visitFMUL(SDNode *N); 433 SDOperand visitFDIV(SDNode *N); 434 SDOperand visitFREM(SDNode *N); 435 SDOperand visitFCOPYSIGN(SDNode *N); 436 SDOperand visitSINT_TO_FP(SDNode *N); 437 SDOperand visitUINT_TO_FP(SDNode *N); 438 SDOperand visitFP_TO_SINT(SDNode *N); 439 SDOperand visitFP_TO_UINT(SDNode *N); 440 SDOperand visitFP_ROUND(SDNode *N); 441 SDOperand visitFP_ROUND_INREG(SDNode *N); 442 SDOperand visitFP_EXTEND(SDNode *N); 443 SDOperand visitFNEG(SDNode *N); 444 SDOperand visitFABS(SDNode *N); 445 SDOperand visitBRCOND(SDNode *N); 446 SDOperand visitBR_CC(SDNode *N); 447 SDOperand visitLOAD(SDNode *N); 448 SDOperand visitSTORE(SDNode *N); 449 SDOperand visitINSERT_VECTOR_ELT(SDNode *N); 450 SDOperand visitVINSERT_VECTOR_ELT(SDNode *N); 451 SDOperand visitVBUILD_VECTOR(SDNode *N); 452 SDOperand visitVECTOR_SHUFFLE(SDNode *N); 453 SDOperand visitVVECTOR_SHUFFLE(SDNode *N); 454 455 SDOperand XformToShuffleWithZero(SDNode *N); 456 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS); 457 458 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS); 459 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N); 460 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 461 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 462 SDOperand N3, ISD::CondCode CC); 463 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 464 ISD::CondCode Cond, bool foldBooleans = true); 465 SDOperand ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *, MVT::ValueType); 466 SDOperand BuildSDIV(SDNode *N); 467 SDOperand BuildUDIV(SDNode *N); 468 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS); 469 470 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 471 /// looking for aliasing nodes and adding them to the Aliases vector. 472 void GatherAllAliases(SDNode *N, SDOperand OriginalChain, 473 SmallVector<SDOperand, 8> &Aliases); 474 475 /// isAlias - Return true if there is any possibility that the two addresses 476 /// overlap. 477 bool isAlias(SDOperand Ptr1, int64_t Size1, 478 const Value *SrcValue1, int SrcValueOffset1, 479 SDOperand Ptr2, int64_t Size2, 480 const Value *SrcValue2, int SrcValueOffset2); 481 482 /// FindAliasInfo - Extracts the relevant alias information from the memory 483 /// node. Returns true if the operand was a load. 484 bool FindAliasInfo(SDNode *N, 485 SDOperand &Ptr, int64_t &Size, 486 const Value *&SrcValue, int &SrcValueOffset); 487 488 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 489 /// looking for a better chain (aliasing node.) 490 SDOperand FindBetterChain(SDNode *N, SDOperand Chain); 491 492public: 493 DAGCombiner(SelectionDAG &D, AliasAnalysis &A) 494 : DAG(D), 495 TLI(D.getTargetLoweringInfo()), 496 AfterLegalize(false), 497 AA(A) {} 498 499 /// Run - runs the dag combiner on all nodes in the work list 500 void Run(bool RunningAfterLegalize); 501 }; 502} 503 504//===----------------------------------------------------------------------===// 505// TargetLowering::DAGCombinerInfo implementation 506//===----------------------------------------------------------------------===// 507 508void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 509 ((DAGCombiner*)DC)->AddToWorkList(N); 510} 511 512SDOperand TargetLowering::DAGCombinerInfo:: 513CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 514 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size()); 515} 516 517SDOperand TargetLowering::DAGCombinerInfo:: 518CombineTo(SDNode *N, SDOperand Res) { 519 return ((DAGCombiner*)DC)->CombineTo(N, Res); 520} 521 522 523SDOperand TargetLowering::DAGCombinerInfo:: 524CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 525 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 526} 527 528 529 530 531//===----------------------------------------------------------------------===// 532 533 534// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 535// that selects between the values 1 and 0, making it equivalent to a setcc. 536// Also, set the incoming LHS, RHS, and CC references to the appropriate 537// nodes based on the type of node we are checking. This simplifies life a 538// bit for the callers. 539static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 540 SDOperand &CC) { 541 if (N.getOpcode() == ISD::SETCC) { 542 LHS = N.getOperand(0); 543 RHS = N.getOperand(1); 544 CC = N.getOperand(2); 545 return true; 546 } 547 if (N.getOpcode() == ISD::SELECT_CC && 548 N.getOperand(2).getOpcode() == ISD::Constant && 549 N.getOperand(3).getOpcode() == ISD::Constant && 550 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 && 551 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 552 LHS = N.getOperand(0); 553 RHS = N.getOperand(1); 554 CC = N.getOperand(4); 555 return true; 556 } 557 return false; 558} 559 560// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 561// one use. If this is true, it allows the users to invert the operation for 562// free when it is profitable to do so. 563static bool isOneUseSetCC(SDOperand N) { 564 SDOperand N0, N1, N2; 565 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 566 return true; 567 return false; 568} 569 570SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){ 571 MVT::ValueType VT = N0.getValueType(); 572 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 573 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 574 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 575 if (isa<ConstantSDNode>(N1)) { 576 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 577 AddToWorkList(OpNode.Val); 578 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 579 } else if (N0.hasOneUse()) { 580 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 581 AddToWorkList(OpNode.Val); 582 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 583 } 584 } 585 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 586 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 587 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 588 if (isa<ConstantSDNode>(N0)) { 589 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 590 AddToWorkList(OpNode.Val); 591 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 592 } else if (N1.hasOneUse()) { 593 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 594 AddToWorkList(OpNode.Val); 595 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 596 } 597 } 598 return SDOperand(); 599} 600 601void DAGCombiner::Run(bool RunningAfterLegalize) { 602 // set the instance variable, so that the various visit routines may use it. 603 AfterLegalize = RunningAfterLegalize; 604 605 // Add all the dag nodes to the worklist. 606 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 607 E = DAG.allnodes_end(); I != E; ++I) 608 WorkList.push_back(I); 609 610 // Create a dummy node (which is not added to allnodes), that adds a reference 611 // to the root node, preventing it from being deleted, and tracking any 612 // changes of the root. 613 HandleSDNode Dummy(DAG.getRoot()); 614 615 // The root of the dag may dangle to deleted nodes until the dag combiner is 616 // done. Set it to null to avoid confusion. 617 DAG.setRoot(SDOperand()); 618 619 /// DagCombineInfo - Expose the DAG combiner to the target combiner impls. 620 TargetLowering::DAGCombinerInfo 621 DagCombineInfo(DAG, !RunningAfterLegalize, this); 622 623 // while the worklist isn't empty, inspect the node on the end of it and 624 // try and combine it. 625 while (!WorkList.empty()) { 626 SDNode *N = WorkList.back(); 627 WorkList.pop_back(); 628 629 // If N has no uses, it is dead. Make sure to revisit all N's operands once 630 // N is deleted from the DAG, since they too may now be dead or may have a 631 // reduced number of uses, allowing other xforms. 632 if (N->use_empty() && N != &Dummy) { 633 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 634 AddToWorkList(N->getOperand(i).Val); 635 636 DAG.DeleteNode(N); 637 continue; 638 } 639 640 SDOperand RV = visit(N); 641 642 // If nothing happened, try a target-specific DAG combine. 643 if (RV.Val == 0) { 644 assert(N->getOpcode() != ISD::DELETED_NODE && 645 "Node was deleted but visit returned NULL!"); 646 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 647 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) 648 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 649 } 650 651 if (RV.Val) { 652 ++NodesCombined; 653 // If we get back the same node we passed in, rather than a new node or 654 // zero, we know that the node must have defined multiple values and 655 // CombineTo was used. Since CombineTo takes care of the worklist 656 // mechanics for us, we have no work to do in this case. 657 if (RV.Val != N) { 658 assert(N->getOpcode() != ISD::DELETED_NODE && 659 RV.Val->getOpcode() != ISD::DELETED_NODE && 660 "Node was deleted but visit returned new node!"); 661 662 DEBUG(std::cerr << "\nReplacing.3 "; N->dump(); 663 std::cerr << "\nWith: "; RV.Val->dump(&DAG); 664 std::cerr << '\n'); 665 std::vector<SDNode*> NowDead; 666 if (N->getNumValues() == RV.Val->getNumValues()) 667 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead); 668 else { 669 assert(N->getValueType(0) == RV.getValueType() && "Type mismatch"); 670 SDOperand OpV = RV; 671 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead); 672 } 673 674 // Push the new node and any users onto the worklist 675 AddToWorkList(RV.Val); 676 AddUsersToWorkList(RV.Val); 677 678 // Nodes can be reintroduced into the worklist. Make sure we do not 679 // process a node that has been replaced. 680 removeFromWorkList(N); 681 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 682 removeFromWorkList(NowDead[i]); 683 684 // Finally, since the node is now dead, remove it from the graph. 685 DAG.DeleteNode(N); 686 } 687 } 688 } 689 690 // If the root changed (e.g. it was a dead load, update the root). 691 DAG.setRoot(Dummy.getValue()); 692} 693 694SDOperand DAGCombiner::visit(SDNode *N) { 695 switch(N->getOpcode()) { 696 default: break; 697 case ISD::TokenFactor: return visitTokenFactor(N); 698 case ISD::ADD: return visitADD(N); 699 case ISD::SUB: return visitSUB(N); 700 case ISD::MUL: return visitMUL(N); 701 case ISD::SDIV: return visitSDIV(N); 702 case ISD::UDIV: return visitUDIV(N); 703 case ISD::SREM: return visitSREM(N); 704 case ISD::UREM: return visitUREM(N); 705 case ISD::MULHU: return visitMULHU(N); 706 case ISD::MULHS: return visitMULHS(N); 707 case ISD::AND: return visitAND(N); 708 case ISD::OR: return visitOR(N); 709 case ISD::XOR: return visitXOR(N); 710 case ISD::SHL: return visitSHL(N); 711 case ISD::SRA: return visitSRA(N); 712 case ISD::SRL: return visitSRL(N); 713 case ISD::CTLZ: return visitCTLZ(N); 714 case ISD::CTTZ: return visitCTTZ(N); 715 case ISD::CTPOP: return visitCTPOP(N); 716 case ISD::SELECT: return visitSELECT(N); 717 case ISD::SELECT_CC: return visitSELECT_CC(N); 718 case ISD::SETCC: return visitSETCC(N); 719 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 720 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 721 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 722 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 723 case ISD::TRUNCATE: return visitTRUNCATE(N); 724 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 725 case ISD::VBIT_CONVERT: return visitVBIT_CONVERT(N); 726 case ISD::FADD: return visitFADD(N); 727 case ISD::FSUB: return visitFSUB(N); 728 case ISD::FMUL: return visitFMUL(N); 729 case ISD::FDIV: return visitFDIV(N); 730 case ISD::FREM: return visitFREM(N); 731 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 732 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 733 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 734 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 735 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 736 case ISD::FP_ROUND: return visitFP_ROUND(N); 737 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 738 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 739 case ISD::FNEG: return visitFNEG(N); 740 case ISD::FABS: return visitFABS(N); 741 case ISD::BRCOND: return visitBRCOND(N); 742 case ISD::BR_CC: return visitBR_CC(N); 743 case ISD::LOAD: return visitLOAD(N); 744 case ISD::STORE: return visitSTORE(N); 745 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 746 case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N); 747 case ISD::VBUILD_VECTOR: return visitVBUILD_VECTOR(N); 748 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 749 case ISD::VVECTOR_SHUFFLE: return visitVVECTOR_SHUFFLE(N); 750 case ISD::VADD: return visitVBinOp(N, ISD::ADD , ISD::FADD); 751 case ISD::VSUB: return visitVBinOp(N, ISD::SUB , ISD::FSUB); 752 case ISD::VMUL: return visitVBinOp(N, ISD::MUL , ISD::FMUL); 753 case ISD::VSDIV: return visitVBinOp(N, ISD::SDIV, ISD::FDIV); 754 case ISD::VUDIV: return visitVBinOp(N, ISD::UDIV, ISD::UDIV); 755 case ISD::VAND: return visitVBinOp(N, ISD::AND , ISD::AND); 756 case ISD::VOR: return visitVBinOp(N, ISD::OR , ISD::OR); 757 case ISD::VXOR: return visitVBinOp(N, ISD::XOR , ISD::XOR); 758 } 759 return SDOperand(); 760} 761 762/// getInputChainForNode - Given a node, return its input chain if it has one, 763/// otherwise return a null sd operand. 764static SDOperand getInputChainForNode(SDNode *N) { 765 if (unsigned NumOps = N->getNumOperands()) { 766 if (N->getOperand(0).getValueType() == MVT::Other) 767 return N->getOperand(0); 768 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 769 return N->getOperand(NumOps-1); 770 for (unsigned i = 1; i < NumOps-1; ++i) 771 if (N->getOperand(i).getValueType() == MVT::Other) 772 return N->getOperand(i); 773 } 774 return SDOperand(0, 0); 775} 776 777SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 778 // If N has two operands, where one has an input chain equal to the other, 779 // the 'other' chain is redundant. 780 if (N->getNumOperands() == 2) { 781 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1)) 782 return N->getOperand(0); 783 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0)) 784 return N->getOperand(1); 785 } 786 787 788 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 789 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor. 790 bool Changed = false; // If we should replace this token factor. 791 792 // Start out with this token factor. 793 TFs.push_back(N); 794 795 // Iterate through token factors. The TFs grows when new token factors are 796 // encountered. 797 for (unsigned i = 0; i < TFs.size(); ++i) { 798 SDNode *TF = TFs[i]; 799 800 // Check each of the operands. 801 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 802 SDOperand Op = TF->getOperand(i); 803 804 switch (Op.getOpcode()) { 805 case ISD::EntryToken: 806 // Entry tokens don't need to be added to the list. They are 807 // rededundant. 808 Changed = true; 809 break; 810 811 case ISD::TokenFactor: 812 if ((CombinerAA || Op.hasOneUse()) && 813 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) { 814 // Queue up for processing. 815 TFs.push_back(Op.Val); 816 // Clean up in case the token factor is removed. 817 AddToWorkList(Op.Val); 818 Changed = true; 819 break; 820 } 821 // Fall thru 822 823 default: 824 // Only add if not there prior. 825 if (std::find(Ops.begin(), Ops.end(), Op) == Ops.end()) 826 Ops.push_back(Op); 827 break; 828 } 829 } 830 } 831 832 SDOperand Result; 833 834 // If we've change things around then replace token factor. 835 if (Changed) { 836 if (Ops.size() == 0) { 837 // The entry token is the only possible outcome. 838 Result = DAG.getEntryNode(); 839 } else { 840 // New and improved token factor. 841 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size()); 842 } 843 844 // Don't add users to work list. 845 return CombineTo(N, Result, false); 846 } 847 848 return Result; 849} 850 851SDOperand DAGCombiner::visitADD(SDNode *N) { 852 SDOperand N0 = N->getOperand(0); 853 SDOperand N1 = N->getOperand(1); 854 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 855 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 856 MVT::ValueType VT = N0.getValueType(); 857 858 // fold (add c1, c2) -> c1+c2 859 if (N0C && N1C) 860 return DAG.getNode(ISD::ADD, VT, N0, N1); 861 // canonicalize constant to RHS 862 if (N0C && !N1C) 863 return DAG.getNode(ISD::ADD, VT, N1, N0); 864 // fold (add x, 0) -> x 865 if (N1C && N1C->isNullValue()) 866 return N0; 867 // fold ((c1-A)+c2) -> (c1+c2)-A 868 if (N1C && N0.getOpcode() == ISD::SUB) 869 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 870 return DAG.getNode(ISD::SUB, VT, 871 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT), 872 N0.getOperand(1)); 873 // reassociate add 874 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1); 875 if (RADD.Val != 0) 876 return RADD; 877 // fold ((0-A) + B) -> B-A 878 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 879 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 880 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 881 // fold (A + (0-B)) -> A-B 882 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 883 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 884 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 885 // fold (A+(B-A)) -> B 886 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 887 return N1.getOperand(0); 888 889 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0))) 890 return SDOperand(N, 0); 891 892 // fold (a+b) -> (a|b) iff a and b share no bits. 893 if (MVT::isInteger(VT) && !MVT::isVector(VT)) { 894 uint64_t LHSZero, LHSOne; 895 uint64_t RHSZero, RHSOne; 896 uint64_t Mask = MVT::getIntVTBitMask(VT); 897 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 898 if (LHSZero) { 899 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 900 901 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 902 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 903 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 904 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 905 return DAG.getNode(ISD::OR, VT, N0, N1); 906 } 907 } 908 909 return SDOperand(); 910} 911 912SDOperand DAGCombiner::visitSUB(SDNode *N) { 913 SDOperand N0 = N->getOperand(0); 914 SDOperand N1 = N->getOperand(1); 915 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 916 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 917 MVT::ValueType VT = N0.getValueType(); 918 919 // fold (sub x, x) -> 0 920 if (N0 == N1) 921 return DAG.getConstant(0, N->getValueType(0)); 922 // fold (sub c1, c2) -> c1-c2 923 if (N0C && N1C) 924 return DAG.getNode(ISD::SUB, VT, N0, N1); 925 // fold (sub x, c) -> (add x, -c) 926 if (N1C) 927 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT)); 928 // fold (A+B)-A -> B 929 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 930 return N0.getOperand(1); 931 // fold (A+B)-B -> A 932 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 933 return N0.getOperand(0); 934 return SDOperand(); 935} 936 937SDOperand DAGCombiner::visitMUL(SDNode *N) { 938 SDOperand N0 = N->getOperand(0); 939 SDOperand N1 = N->getOperand(1); 940 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 941 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 942 MVT::ValueType VT = N0.getValueType(); 943 944 // fold (mul c1, c2) -> c1*c2 945 if (N0C && N1C) 946 return DAG.getNode(ISD::MUL, VT, N0, N1); 947 // canonicalize constant to RHS 948 if (N0C && !N1C) 949 return DAG.getNode(ISD::MUL, VT, N1, N0); 950 // fold (mul x, 0) -> 0 951 if (N1C && N1C->isNullValue()) 952 return N1; 953 // fold (mul x, -1) -> 0-x 954 if (N1C && N1C->isAllOnesValue()) 955 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 956 // fold (mul x, (1 << c)) -> x << c 957 if (N1C && isPowerOf2_64(N1C->getValue())) 958 return DAG.getNode(ISD::SHL, VT, N0, 959 DAG.getConstant(Log2_64(N1C->getValue()), 960 TLI.getShiftAmountTy())); 961 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 962 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { 963 // FIXME: If the input is something that is easily negated (e.g. a 964 // single-use add), we should put the negate there. 965 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 966 DAG.getNode(ISD::SHL, VT, N0, 967 DAG.getConstant(Log2_64(-N1C->getSignExtended()), 968 TLI.getShiftAmountTy()))); 969 } 970 971 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 972 if (N1C && N0.getOpcode() == ISD::SHL && 973 isa<ConstantSDNode>(N0.getOperand(1))) { 974 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 975 AddToWorkList(C3.Val); 976 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 977 } 978 979 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 980 // use. 981 { 982 SDOperand Sh(0,0), Y(0,0); 983 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 984 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 985 N0.Val->hasOneUse()) { 986 Sh = N0; Y = N1; 987 } else if (N1.getOpcode() == ISD::SHL && 988 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) { 989 Sh = N1; Y = N0; 990 } 991 if (Sh.Val) { 992 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 993 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 994 } 995 } 996 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 997 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 998 isa<ConstantSDNode>(N0.getOperand(1))) { 999 return DAG.getNode(ISD::ADD, VT, 1000 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 1001 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 1002 } 1003 1004 // reassociate mul 1005 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1); 1006 if (RMUL.Val != 0) 1007 return RMUL; 1008 return SDOperand(); 1009} 1010 1011SDOperand DAGCombiner::visitSDIV(SDNode *N) { 1012 SDOperand N0 = N->getOperand(0); 1013 SDOperand N1 = N->getOperand(1); 1014 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1015 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1016 MVT::ValueType VT = N->getValueType(0); 1017 1018 // fold (sdiv c1, c2) -> c1/c2 1019 if (N0C && N1C && !N1C->isNullValue()) 1020 return DAG.getNode(ISD::SDIV, VT, N0, N1); 1021 // fold (sdiv X, 1) -> X 1022 if (N1C && N1C->getSignExtended() == 1LL) 1023 return N0; 1024 // fold (sdiv X, -1) -> 0-X 1025 if (N1C && N1C->isAllOnesValue()) 1026 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1027 // If we know the sign bits of both operands are zero, strength reduce to a 1028 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1029 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 1030 if (TLI.MaskedValueIsZero(N1, SignBit) && 1031 TLI.MaskedValueIsZero(N0, SignBit)) 1032 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 1033 // fold (sdiv X, pow2) -> simple ops after legalize 1034 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() && 1035 (isPowerOf2_64(N1C->getSignExtended()) || 1036 isPowerOf2_64(-N1C->getSignExtended()))) { 1037 // If dividing by powers of two is cheap, then don't perform the following 1038 // fold. 1039 if (TLI.isPow2DivCheap()) 1040 return SDOperand(); 1041 int64_t pow2 = N1C->getSignExtended(); 1042 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1043 unsigned lg2 = Log2_64(abs2); 1044 // Splat the sign bit into the register 1045 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0, 1046 DAG.getConstant(MVT::getSizeInBits(VT)-1, 1047 TLI.getShiftAmountTy())); 1048 AddToWorkList(SGN.Val); 1049 // Add (N0 < 0) ? abs2 - 1 : 0; 1050 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN, 1051 DAG.getConstant(MVT::getSizeInBits(VT)-lg2, 1052 TLI.getShiftAmountTy())); 1053 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 1054 AddToWorkList(SRL.Val); 1055 AddToWorkList(ADD.Val); // Divide by pow2 1056 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD, 1057 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 1058 // If we're dividing by a positive value, we're done. Otherwise, we must 1059 // negate the result. 1060 if (pow2 > 0) 1061 return SRA; 1062 AddToWorkList(SRA.Val); 1063 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 1064 } 1065 // if integer divide is expensive and we satisfy the requirements, emit an 1066 // alternate sequence. 1067 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 1068 !TLI.isIntDivCheap()) { 1069 SDOperand Op = BuildSDIV(N); 1070 if (Op.Val) return Op; 1071 } 1072 return SDOperand(); 1073} 1074 1075SDOperand DAGCombiner::visitUDIV(SDNode *N) { 1076 SDOperand N0 = N->getOperand(0); 1077 SDOperand N1 = N->getOperand(1); 1078 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1079 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1080 MVT::ValueType VT = N->getValueType(0); 1081 1082 // fold (udiv c1, c2) -> c1/c2 1083 if (N0C && N1C && !N1C->isNullValue()) 1084 return DAG.getNode(ISD::UDIV, VT, N0, N1); 1085 // fold (udiv x, (1 << c)) -> x >>u c 1086 if (N1C && isPowerOf2_64(N1C->getValue())) 1087 return DAG.getNode(ISD::SRL, VT, N0, 1088 DAG.getConstant(Log2_64(N1C->getValue()), 1089 TLI.getShiftAmountTy())); 1090 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1091 if (N1.getOpcode() == ISD::SHL) { 1092 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1093 if (isPowerOf2_64(SHC->getValue())) { 1094 MVT::ValueType ADDVT = N1.getOperand(1).getValueType(); 1095 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 1096 DAG.getConstant(Log2_64(SHC->getValue()), 1097 ADDVT)); 1098 AddToWorkList(Add.Val); 1099 return DAG.getNode(ISD::SRL, VT, N0, Add); 1100 } 1101 } 1102 } 1103 // fold (udiv x, c) -> alternate 1104 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) { 1105 SDOperand Op = BuildUDIV(N); 1106 if (Op.Val) return Op; 1107 } 1108 return SDOperand(); 1109} 1110 1111SDOperand DAGCombiner::visitSREM(SDNode *N) { 1112 SDOperand N0 = N->getOperand(0); 1113 SDOperand N1 = N->getOperand(1); 1114 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1115 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1116 MVT::ValueType VT = N->getValueType(0); 1117 1118 // fold (srem c1, c2) -> c1%c2 1119 if (N0C && N1C && !N1C->isNullValue()) 1120 return DAG.getNode(ISD::SREM, VT, N0, N1); 1121 // If we know the sign bits of both operands are zero, strength reduce to a 1122 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1123 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 1124 if (TLI.MaskedValueIsZero(N1, SignBit) && 1125 TLI.MaskedValueIsZero(N0, SignBit)) 1126 return DAG.getNode(ISD::UREM, VT, N0, N1); 1127 1128 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on 1129 // the remainder operation. 1130 if (N1C && !N1C->isNullValue()) { 1131 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1); 1132 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1); 1133 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1134 AddToWorkList(Div.Val); 1135 AddToWorkList(Mul.Val); 1136 return Sub; 1137 } 1138 1139 return SDOperand(); 1140} 1141 1142SDOperand DAGCombiner::visitUREM(SDNode *N) { 1143 SDOperand N0 = N->getOperand(0); 1144 SDOperand N1 = N->getOperand(1); 1145 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1146 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1147 MVT::ValueType VT = N->getValueType(0); 1148 1149 // fold (urem c1, c2) -> c1%c2 1150 if (N0C && N1C && !N1C->isNullValue()) 1151 return DAG.getNode(ISD::UREM, VT, N0, N1); 1152 // fold (urem x, pow2) -> (and x, pow2-1) 1153 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue())) 1154 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT)); 1155 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1156 if (N1.getOpcode() == ISD::SHL) { 1157 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1158 if (isPowerOf2_64(SHC->getValue())) { 1159 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT)); 1160 AddToWorkList(Add.Val); 1161 return DAG.getNode(ISD::AND, VT, N0, Add); 1162 } 1163 } 1164 } 1165 1166 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on 1167 // the remainder operation. 1168 if (N1C && !N1C->isNullValue()) { 1169 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1); 1170 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1); 1171 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1172 AddToWorkList(Div.Val); 1173 AddToWorkList(Mul.Val); 1174 return Sub; 1175 } 1176 1177 return SDOperand(); 1178} 1179 1180SDOperand DAGCombiner::visitMULHS(SDNode *N) { 1181 SDOperand N0 = N->getOperand(0); 1182 SDOperand N1 = N->getOperand(1); 1183 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1184 1185 // fold (mulhs x, 0) -> 0 1186 if (N1C && N1C->isNullValue()) 1187 return N1; 1188 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1189 if (N1C && N1C->getValue() == 1) 1190 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 1191 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 1192 TLI.getShiftAmountTy())); 1193 return SDOperand(); 1194} 1195 1196SDOperand DAGCombiner::visitMULHU(SDNode *N) { 1197 SDOperand N0 = N->getOperand(0); 1198 SDOperand N1 = N->getOperand(1); 1199 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1200 1201 // fold (mulhu x, 0) -> 0 1202 if (N1C && N1C->isNullValue()) 1203 return N1; 1204 // fold (mulhu x, 1) -> 0 1205 if (N1C && N1C->getValue() == 1) 1206 return DAG.getConstant(0, N0.getValueType()); 1207 return SDOperand(); 1208} 1209 1210/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1211/// two operands of the same opcode, try to simplify it. 1212SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1213 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1); 1214 MVT::ValueType VT = N0.getValueType(); 1215 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1216 1217 // For each of OP in AND/OR/XOR: 1218 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1219 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1220 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1221 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1222 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1223 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 1224 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1225 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1226 N0.getOperand(0).getValueType(), 1227 N0.getOperand(0), N1.getOperand(0)); 1228 AddToWorkList(ORNode.Val); 1229 return DAG.getNode(N0.getOpcode(), VT, ORNode); 1230 } 1231 1232 // For each of OP in SHL/SRL/SRA/AND... 1233 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1234 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1235 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1236 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1237 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1238 N0.getOperand(1) == N1.getOperand(1)) { 1239 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1240 N0.getOperand(0).getValueType(), 1241 N0.getOperand(0), N1.getOperand(0)); 1242 AddToWorkList(ORNode.Val); 1243 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1244 } 1245 1246 return SDOperand(); 1247} 1248 1249SDOperand DAGCombiner::visitAND(SDNode *N) { 1250 SDOperand N0 = N->getOperand(0); 1251 SDOperand N1 = N->getOperand(1); 1252 SDOperand LL, LR, RL, RR, CC0, CC1; 1253 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1254 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1255 MVT::ValueType VT = N1.getValueType(); 1256 1257 // fold (and c1, c2) -> c1&c2 1258 if (N0C && N1C) 1259 return DAG.getNode(ISD::AND, VT, N0, N1); 1260 // canonicalize constant to RHS 1261 if (N0C && !N1C) 1262 return DAG.getNode(ISD::AND, VT, N1, N0); 1263 // fold (and x, -1) -> x 1264 if (N1C && N1C->isAllOnesValue()) 1265 return N0; 1266 // if (and x, c) is known to be zero, return 0 1267 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 1268 return DAG.getConstant(0, VT); 1269 // reassociate and 1270 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1); 1271 if (RAND.Val != 0) 1272 return RAND; 1273 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1274 if (N1C && N0.getOpcode() == ISD::OR) 1275 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1276 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) 1277 return N1; 1278 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1279 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1280 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType()); 1281 if (TLI.MaskedValueIsZero(N0.getOperand(0), 1282 ~N1C->getValue() & InMask)) { 1283 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 1284 N0.getOperand(0)); 1285 1286 // Replace uses of the AND with uses of the Zero extend node. 1287 CombineTo(N, Zext); 1288 1289 // We actually want to replace all uses of the any_extend with the 1290 // zero_extend, to avoid duplicating things. This will later cause this 1291 // AND to be folded. 1292 CombineTo(N0.Val, Zext); 1293 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1294 } 1295 } 1296 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1297 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1298 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1299 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1300 1301 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1302 MVT::isInteger(LL.getValueType())) { 1303 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 1304 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) { 1305 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1306 AddToWorkList(ORNode.Val); 1307 return DAG.getSetCC(VT, ORNode, LR, Op1); 1308 } 1309 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 1310 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1311 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1312 AddToWorkList(ANDNode.Val); 1313 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1314 } 1315 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 1316 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1317 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1318 AddToWorkList(ORNode.Val); 1319 return DAG.getSetCC(VT, ORNode, LR, Op1); 1320 } 1321 } 1322 // canonicalize equivalent to ll == rl 1323 if (LL == RR && LR == RL) { 1324 Op1 = ISD::getSetCCSwappedOperands(Op1); 1325 std::swap(RL, RR); 1326 } 1327 if (LL == RL && LR == RR) { 1328 bool isInteger = MVT::isInteger(LL.getValueType()); 1329 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1330 if (Result != ISD::SETCC_INVALID) 1331 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1332 } 1333 } 1334 1335 // Simplify: and (op x...), (op y...) -> (op (and x, y)) 1336 if (N0.getOpcode() == N1.getOpcode()) { 1337 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1338 if (Tmp.Val) return Tmp; 1339 } 1340 1341 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1342 // fold (and (sra)) -> (and (srl)) when possible. 1343 if (!MVT::isVector(VT) && 1344 SimplifyDemandedBits(SDOperand(N, 0))) 1345 return SDOperand(N, 0); 1346 // fold (zext_inreg (extload x)) -> (zextload x) 1347 if (ISD::isEXTLoad(N0.Val)) { 1348 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1349 MVT::ValueType EVT = LN0->getLoadedVT(); 1350 // If we zero all the possible extended bits, then we can turn this into 1351 // a zextload if we are running before legalize or the operation is legal. 1352 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1353 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1354 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1355 LN0->getBasePtr(), LN0->getSrcValue(), 1356 LN0->getSrcValueOffset(), EVT); 1357 AddToWorkList(N); 1358 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1359 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1360 } 1361 } 1362 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1363 if (ISD::isSEXTLoad(N0.Val) && N0.hasOneUse()) { 1364 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1365 MVT::ValueType EVT = LN0->getLoadedVT(); 1366 // If we zero all the possible extended bits, then we can turn this into 1367 // a zextload if we are running before legalize or the operation is legal. 1368 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1369 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1370 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1371 LN0->getBasePtr(), LN0->getSrcValue(), 1372 LN0->getSrcValueOffset(), EVT); 1373 AddToWorkList(N); 1374 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1375 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1376 } 1377 } 1378 1379 // fold (and (load x), 255) -> (zextload x, i8) 1380 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1381 if (N1C && N0.getOpcode() == ISD::LOAD) { 1382 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1383 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1384 N0.hasOneUse()) { 1385 MVT::ValueType EVT, LoadedVT; 1386 if (N1C->getValue() == 255) 1387 EVT = MVT::i8; 1388 else if (N1C->getValue() == 65535) 1389 EVT = MVT::i16; 1390 else if (N1C->getValue() == ~0U) 1391 EVT = MVT::i32; 1392 else 1393 EVT = MVT::Other; 1394 1395 LoadedVT = LN0->getLoadedVT(); 1396 if (EVT != MVT::Other && LoadedVT > EVT && 1397 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1398 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1399 // For big endian targets, we need to add an offset to the pointer to 1400 // load the correct bytes. For little endian systems, we merely need to 1401 // read fewer bytes from the same pointer. 1402 unsigned PtrOff = 1403 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8; 1404 SDOperand NewPtr = LN0->getBasePtr(); 1405 if (!TLI.isLittleEndian()) 1406 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1407 DAG.getConstant(PtrOff, PtrType)); 1408 AddToWorkList(NewPtr.Val); 1409 SDOperand Load = 1410 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr, 1411 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT); 1412 AddToWorkList(N); 1413 CombineTo(N0.Val, Load, Load.getValue(1)); 1414 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1415 } 1416 } 1417 } 1418 1419 return SDOperand(); 1420} 1421 1422SDOperand DAGCombiner::visitOR(SDNode *N) { 1423 SDOperand N0 = N->getOperand(0); 1424 SDOperand N1 = N->getOperand(1); 1425 SDOperand LL, LR, RL, RR, CC0, CC1; 1426 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1427 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1428 MVT::ValueType VT = N1.getValueType(); 1429 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1430 1431 // fold (or c1, c2) -> c1|c2 1432 if (N0C && N1C) 1433 return DAG.getNode(ISD::OR, VT, N0, N1); 1434 // canonicalize constant to RHS 1435 if (N0C && !N1C) 1436 return DAG.getNode(ISD::OR, VT, N1, N0); 1437 // fold (or x, 0) -> x 1438 if (N1C && N1C->isNullValue()) 1439 return N0; 1440 // fold (or x, -1) -> -1 1441 if (N1C && N1C->isAllOnesValue()) 1442 return N1; 1443 // fold (or x, c) -> c iff (x & ~c) == 0 1444 if (N1C && 1445 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)))) 1446 return N1; 1447 // reassociate or 1448 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1); 1449 if (ROR.Val != 0) 1450 return ROR; 1451 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1452 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() && 1453 isa<ConstantSDNode>(N0.getOperand(1))) { 1454 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1455 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1456 N1), 1457 DAG.getConstant(N1C->getValue() | C1->getValue(), VT)); 1458 } 1459 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1460 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1461 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1462 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1463 1464 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1465 MVT::isInteger(LL.getValueType())) { 1466 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1467 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1468 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1469 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1470 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1471 AddToWorkList(ORNode.Val); 1472 return DAG.getSetCC(VT, ORNode, LR, Op1); 1473 } 1474 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1475 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1476 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1477 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1478 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1479 AddToWorkList(ANDNode.Val); 1480 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1481 } 1482 } 1483 // canonicalize equivalent to ll == rl 1484 if (LL == RR && LR == RL) { 1485 Op1 = ISD::getSetCCSwappedOperands(Op1); 1486 std::swap(RL, RR); 1487 } 1488 if (LL == RL && LR == RR) { 1489 bool isInteger = MVT::isInteger(LL.getValueType()); 1490 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1491 if (Result != ISD::SETCC_INVALID) 1492 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1493 } 1494 } 1495 1496 // Simplify: or (op x...), (op y...) -> (op (or x, y)) 1497 if (N0.getOpcode() == N1.getOpcode()) { 1498 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1499 if (Tmp.Val) return Tmp; 1500 } 1501 1502 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible. 1503 if (N0.getOpcode() == ISD::AND && 1504 N1.getOpcode() == ISD::AND && 1505 N0.getOperand(1).getOpcode() == ISD::Constant && 1506 N1.getOperand(1).getOpcode() == ISD::Constant && 1507 // Don't increase # computations. 1508 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) { 1509 // We can only do this xform if we know that bits from X that are set in C2 1510 // but not in C1 are already zero. Likewise for Y. 1511 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1512 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue(); 1513 1514 if (TLI.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 1515 TLI.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 1516 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0)); 1517 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT)); 1518 } 1519 } 1520 1521 1522 // See if this is some rotate idiom. 1523 if (SDNode *Rot = MatchRotate(N0, N1)) 1524 return SDOperand(Rot, 0); 1525 1526 return SDOperand(); 1527} 1528 1529 1530/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 1531static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) { 1532 if (Op.getOpcode() == ISD::AND) { 1533 if (isa<ConstantSDNode>(Op.getOperand(1))) { 1534 Mask = Op.getOperand(1); 1535 Op = Op.getOperand(0); 1536 } else { 1537 return false; 1538 } 1539 } 1540 1541 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 1542 Shift = Op; 1543 return true; 1544 } 1545 return false; 1546} 1547 1548 1549// MatchRotate - Handle an 'or' of two operands. If this is one of the many 1550// idioms for rotate, and if the target supports rotation instructions, generate 1551// a rot[lr]. 1552SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) { 1553 // Must be a legal type. Expanded an promoted things won't work with rotates. 1554 MVT::ValueType VT = LHS.getValueType(); 1555 if (!TLI.isTypeLegal(VT)) return 0; 1556 1557 // The target must have at least one rotate flavor. 1558 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT); 1559 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT); 1560 if (!HasROTL && !HasROTR) return 0; 1561 1562 // Match "(X shl/srl V1) & V2" where V2 may not be present. 1563 SDOperand LHSShift; // The shift. 1564 SDOperand LHSMask; // AND value if any. 1565 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 1566 return 0; // Not part of a rotate. 1567 1568 SDOperand RHSShift; // The shift. 1569 SDOperand RHSMask; // AND value if any. 1570 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 1571 return 0; // Not part of a rotate. 1572 1573 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 1574 return 0; // Not shifting the same value. 1575 1576 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 1577 return 0; // Shifts must disagree. 1578 1579 // Canonicalize shl to left side in a shl/srl pair. 1580 if (RHSShift.getOpcode() == ISD::SHL) { 1581 std::swap(LHS, RHS); 1582 std::swap(LHSShift, RHSShift); 1583 std::swap(LHSMask , RHSMask ); 1584 } 1585 1586 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1587 1588 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 1589 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 1590 if (LHSShift.getOperand(1).getOpcode() == ISD::Constant && 1591 RHSShift.getOperand(1).getOpcode() == ISD::Constant) { 1592 uint64_t LShVal = cast<ConstantSDNode>(LHSShift.getOperand(1))->getValue(); 1593 uint64_t RShVal = cast<ConstantSDNode>(RHSShift.getOperand(1))->getValue(); 1594 if ((LShVal + RShVal) != OpSizeInBits) 1595 return 0; 1596 1597 SDOperand Rot; 1598 if (HasROTL) 1599 Rot = DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0), 1600 LHSShift.getOperand(1)); 1601 else 1602 Rot = DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0), 1603 RHSShift.getOperand(1)); 1604 1605 // If there is an AND of either shifted operand, apply it to the result. 1606 if (LHSMask.Val || RHSMask.Val) { 1607 uint64_t Mask = MVT::getIntVTBitMask(VT); 1608 1609 if (LHSMask.Val) { 1610 uint64_t RHSBits = (1ULL << LShVal)-1; 1611 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits; 1612 } 1613 if (RHSMask.Val) { 1614 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1); 1615 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits; 1616 } 1617 1618 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT)); 1619 } 1620 1621 return Rot.Val; 1622 } 1623 1624 // If there is a mask here, and we have a variable shift, we can't be sure 1625 // that we're masking out the right stuff. 1626 if (LHSMask.Val || RHSMask.Val) 1627 return 0; 1628 1629 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 1630 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 1631 if (RHSShift.getOperand(1).getOpcode() == ISD::SUB && 1632 LHSShift.getOperand(1) == RHSShift.getOperand(1).getOperand(1)) { 1633 if (ConstantSDNode *SUBC = 1634 dyn_cast<ConstantSDNode>(RHSShift.getOperand(1).getOperand(0))) { 1635 if (SUBC->getValue() == OpSizeInBits) 1636 if (HasROTL) 1637 return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0), 1638 LHSShift.getOperand(1)).Val; 1639 else 1640 return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0), 1641 LHSShift.getOperand(1)).Val; 1642 } 1643 } 1644 1645 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 1646 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 1647 if (LHSShift.getOperand(1).getOpcode() == ISD::SUB && 1648 RHSShift.getOperand(1) == LHSShift.getOperand(1).getOperand(1)) { 1649 if (ConstantSDNode *SUBC = 1650 dyn_cast<ConstantSDNode>(LHSShift.getOperand(1).getOperand(0))) { 1651 if (SUBC->getValue() == OpSizeInBits) 1652 if (HasROTL) 1653 return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0), 1654 LHSShift.getOperand(1)).Val; 1655 else 1656 return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0), 1657 RHSShift.getOperand(1)).Val; 1658 } 1659 } 1660 1661 return 0; 1662} 1663 1664 1665SDOperand DAGCombiner::visitXOR(SDNode *N) { 1666 SDOperand N0 = N->getOperand(0); 1667 SDOperand N1 = N->getOperand(1); 1668 SDOperand LHS, RHS, CC; 1669 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1670 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1671 MVT::ValueType VT = N0.getValueType(); 1672 1673 // fold (xor c1, c2) -> c1^c2 1674 if (N0C && N1C) 1675 return DAG.getNode(ISD::XOR, VT, N0, N1); 1676 // canonicalize constant to RHS 1677 if (N0C && !N1C) 1678 return DAG.getNode(ISD::XOR, VT, N1, N0); 1679 // fold (xor x, 0) -> x 1680 if (N1C && N1C->isNullValue()) 1681 return N0; 1682 // reassociate xor 1683 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1); 1684 if (RXOR.Val != 0) 1685 return RXOR; 1686 // fold !(x cc y) -> (x !cc y) 1687 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 1688 bool isInt = MVT::isInteger(LHS.getValueType()); 1689 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 1690 isInt); 1691 if (N0.getOpcode() == ISD::SETCC) 1692 return DAG.getSetCC(VT, LHS, RHS, NotCC); 1693 if (N0.getOpcode() == ISD::SELECT_CC) 1694 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 1695 assert(0 && "Unhandled SetCC Equivalent!"); 1696 abort(); 1697 } 1698 // fold !(x or y) -> (!x and !y) iff x or y are setcc 1699 if (N1C && N1C->getValue() == 1 && 1700 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1701 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1702 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 1703 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1704 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1705 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1706 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 1707 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1708 } 1709 } 1710 // fold !(x or y) -> (!x and !y) iff x or y are constants 1711 if (N1C && N1C->isAllOnesValue() && 1712 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1713 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1714 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 1715 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1716 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1717 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1718 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 1719 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1720 } 1721 } 1722 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 1723 if (N1C && N0.getOpcode() == ISD::XOR) { 1724 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 1725 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 1726 if (N00C) 1727 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 1728 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT)); 1729 if (N01C) 1730 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 1731 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT)); 1732 } 1733 // fold (xor x, x) -> 0 1734 if (N0 == N1) { 1735 if (!MVT::isVector(VT)) { 1736 return DAG.getConstant(0, VT); 1737 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 1738 // Produce a vector of zeros. 1739 SDOperand El = DAG.getConstant(0, MVT::getVectorBaseType(VT)); 1740 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El); 1741 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1742 } 1743 } 1744 1745 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 1746 if (N0.getOpcode() == N1.getOpcode()) { 1747 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1748 if (Tmp.Val) return Tmp; 1749 } 1750 1751 // Simplify the expression using non-local knowledge. 1752 if (!MVT::isVector(VT) && 1753 SimplifyDemandedBits(SDOperand(N, 0))) 1754 return SDOperand(N, 0); 1755 1756 return SDOperand(); 1757} 1758 1759SDOperand DAGCombiner::visitSHL(SDNode *N) { 1760 SDOperand N0 = N->getOperand(0); 1761 SDOperand N1 = N->getOperand(1); 1762 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1763 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1764 MVT::ValueType VT = N0.getValueType(); 1765 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1766 1767 // fold (shl c1, c2) -> c1<<c2 1768 if (N0C && N1C) 1769 return DAG.getNode(ISD::SHL, VT, N0, N1); 1770 // fold (shl 0, x) -> 0 1771 if (N0C && N0C->isNullValue()) 1772 return N0; 1773 // fold (shl x, c >= size(x)) -> undef 1774 if (N1C && N1C->getValue() >= OpSizeInBits) 1775 return DAG.getNode(ISD::UNDEF, VT); 1776 // fold (shl x, 0) -> x 1777 if (N1C && N1C->isNullValue()) 1778 return N0; 1779 // if (shl x, c) is known to be zero, return 0 1780 if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 1781 return DAG.getConstant(0, VT); 1782 if (SimplifyDemandedBits(SDOperand(N, 0))) 1783 return SDOperand(N, 0); 1784 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 1785 if (N1C && N0.getOpcode() == ISD::SHL && 1786 N0.getOperand(1).getOpcode() == ISD::Constant) { 1787 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1788 uint64_t c2 = N1C->getValue(); 1789 if (c1 + c2 > OpSizeInBits) 1790 return DAG.getConstant(0, VT); 1791 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 1792 DAG.getConstant(c1 + c2, N1.getValueType())); 1793 } 1794 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 1795 // (srl (and x, -1 << c1), c1-c2) 1796 if (N1C && N0.getOpcode() == ISD::SRL && 1797 N0.getOperand(1).getOpcode() == ISD::Constant) { 1798 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1799 uint64_t c2 = N1C->getValue(); 1800 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1801 DAG.getConstant(~0ULL << c1, VT)); 1802 if (c2 > c1) 1803 return DAG.getNode(ISD::SHL, VT, Mask, 1804 DAG.getConstant(c2-c1, N1.getValueType())); 1805 else 1806 return DAG.getNode(ISD::SRL, VT, Mask, 1807 DAG.getConstant(c1-c2, N1.getValueType())); 1808 } 1809 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 1810 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 1811 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1812 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 1813 // fold (shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2) 1814 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 1815 isa<ConstantSDNode>(N0.getOperand(1))) { 1816 return DAG.getNode(ISD::ADD, VT, 1817 DAG.getNode(ISD::SHL, VT, N0.getOperand(0), N1), 1818 DAG.getNode(ISD::SHL, VT, N0.getOperand(1), N1)); 1819 } 1820 return SDOperand(); 1821} 1822 1823SDOperand DAGCombiner::visitSRA(SDNode *N) { 1824 SDOperand N0 = N->getOperand(0); 1825 SDOperand N1 = N->getOperand(1); 1826 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1827 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1828 MVT::ValueType VT = N0.getValueType(); 1829 1830 // fold (sra c1, c2) -> c1>>c2 1831 if (N0C && N1C) 1832 return DAG.getNode(ISD::SRA, VT, N0, N1); 1833 // fold (sra 0, x) -> 0 1834 if (N0C && N0C->isNullValue()) 1835 return N0; 1836 // fold (sra -1, x) -> -1 1837 if (N0C && N0C->isAllOnesValue()) 1838 return N0; 1839 // fold (sra x, c >= size(x)) -> undef 1840 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT)) 1841 return DAG.getNode(ISD::UNDEF, VT); 1842 // fold (sra x, 0) -> x 1843 if (N1C && N1C->isNullValue()) 1844 return N0; 1845 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 1846 // sext_inreg. 1847 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 1848 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue(); 1849 MVT::ValueType EVT; 1850 switch (LowBits) { 1851 default: EVT = MVT::Other; break; 1852 case 1: EVT = MVT::i1; break; 1853 case 8: EVT = MVT::i8; break; 1854 case 16: EVT = MVT::i16; break; 1855 case 32: EVT = MVT::i32; break; 1856 } 1857 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)) 1858 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 1859 DAG.getValueType(EVT)); 1860 } 1861 1862 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 1863 if (N1C && N0.getOpcode() == ISD::SRA) { 1864 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1865 unsigned Sum = N1C->getValue() + C1->getValue(); 1866 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1; 1867 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 1868 DAG.getConstant(Sum, N1C->getValueType(0))); 1869 } 1870 } 1871 1872 // Simplify, based on bits shifted out of the LHS. 1873 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 1874 return SDOperand(N, 0); 1875 1876 1877 // If the sign bit is known to be zero, switch this to a SRL. 1878 if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT))) 1879 return DAG.getNode(ISD::SRL, VT, N0, N1); 1880 return SDOperand(); 1881} 1882 1883SDOperand DAGCombiner::visitSRL(SDNode *N) { 1884 SDOperand N0 = N->getOperand(0); 1885 SDOperand N1 = N->getOperand(1); 1886 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1887 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1888 MVT::ValueType VT = N0.getValueType(); 1889 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1890 1891 // fold (srl c1, c2) -> c1 >>u c2 1892 if (N0C && N1C) 1893 return DAG.getNode(ISD::SRL, VT, N0, N1); 1894 // fold (srl 0, x) -> 0 1895 if (N0C && N0C->isNullValue()) 1896 return N0; 1897 // fold (srl x, c >= size(x)) -> undef 1898 if (N1C && N1C->getValue() >= OpSizeInBits) 1899 return DAG.getNode(ISD::UNDEF, VT); 1900 // fold (srl x, 0) -> x 1901 if (N1C && N1C->isNullValue()) 1902 return N0; 1903 // if (srl x, c) is known to be zero, return 0 1904 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits))) 1905 return DAG.getConstant(0, VT); 1906 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 1907 if (N1C && N0.getOpcode() == ISD::SRL && 1908 N0.getOperand(1).getOpcode() == ISD::Constant) { 1909 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1910 uint64_t c2 = N1C->getValue(); 1911 if (c1 + c2 > OpSizeInBits) 1912 return DAG.getConstant(0, VT); 1913 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 1914 DAG.getConstant(c1 + c2, N1.getValueType())); 1915 } 1916 1917 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 1918 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1919 // Shifting in all undef bits? 1920 MVT::ValueType SmallVT = N0.getOperand(0).getValueType(); 1921 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT)) 1922 return DAG.getNode(ISD::UNDEF, VT); 1923 1924 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); 1925 AddToWorkList(SmallShift.Val); 1926 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); 1927 } 1928 1929 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 1930 // bit, which is unmodified by sra. 1931 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) { 1932 if (N0.getOpcode() == ISD::SRA) 1933 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1); 1934 } 1935 1936 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 1937 if (N1C && N0.getOpcode() == ISD::CTLZ && 1938 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) { 1939 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT); 1940 TLI.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 1941 1942 // If any of the input bits are KnownOne, then the input couldn't be all 1943 // zeros, thus the result of the srl will always be zero. 1944 if (KnownOne) return DAG.getConstant(0, VT); 1945 1946 // If all of the bits input the to ctlz node are known to be zero, then 1947 // the result of the ctlz is "32" and the result of the shift is one. 1948 uint64_t UnknownBits = ~KnownZero & Mask; 1949 if (UnknownBits == 0) return DAG.getConstant(1, VT); 1950 1951 // Otherwise, check to see if there is exactly one bit input to the ctlz. 1952 if ((UnknownBits & (UnknownBits-1)) == 0) { 1953 // Okay, we know that only that the single bit specified by UnknownBits 1954 // could be set on input to the CTLZ node. If this bit is set, the SRL 1955 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 1956 // to an SRL,XOR pair, which is likely to simplify more. 1957 unsigned ShAmt = CountTrailingZeros_64(UnknownBits); 1958 SDOperand Op = N0.getOperand(0); 1959 if (ShAmt) { 1960 Op = DAG.getNode(ISD::SRL, VT, Op, 1961 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 1962 AddToWorkList(Op.Val); 1963 } 1964 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 1965 } 1966 } 1967 1968 return SDOperand(); 1969} 1970 1971SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 1972 SDOperand N0 = N->getOperand(0); 1973 MVT::ValueType VT = N->getValueType(0); 1974 1975 // fold (ctlz c1) -> c2 1976 if (isa<ConstantSDNode>(N0)) 1977 return DAG.getNode(ISD::CTLZ, VT, N0); 1978 return SDOperand(); 1979} 1980 1981SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 1982 SDOperand N0 = N->getOperand(0); 1983 MVT::ValueType VT = N->getValueType(0); 1984 1985 // fold (cttz c1) -> c2 1986 if (isa<ConstantSDNode>(N0)) 1987 return DAG.getNode(ISD::CTTZ, VT, N0); 1988 return SDOperand(); 1989} 1990 1991SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 1992 SDOperand N0 = N->getOperand(0); 1993 MVT::ValueType VT = N->getValueType(0); 1994 1995 // fold (ctpop c1) -> c2 1996 if (isa<ConstantSDNode>(N0)) 1997 return DAG.getNode(ISD::CTPOP, VT, N0); 1998 return SDOperand(); 1999} 2000 2001SDOperand DAGCombiner::visitSELECT(SDNode *N) { 2002 SDOperand N0 = N->getOperand(0); 2003 SDOperand N1 = N->getOperand(1); 2004 SDOperand N2 = N->getOperand(2); 2005 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2006 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2007 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2008 MVT::ValueType VT = N->getValueType(0); 2009 2010 // fold select C, X, X -> X 2011 if (N1 == N2) 2012 return N1; 2013 // fold select true, X, Y -> X 2014 if (N0C && !N0C->isNullValue()) 2015 return N1; 2016 // fold select false, X, Y -> Y 2017 if (N0C && N0C->isNullValue()) 2018 return N2; 2019 // fold select C, 1, X -> C | X 2020 if (MVT::i1 == VT && N1C && N1C->getValue() == 1) 2021 return DAG.getNode(ISD::OR, VT, N0, N2); 2022 // fold select C, 0, X -> ~C & X 2023 // FIXME: this should check for C type == X type, not i1? 2024 if (MVT::i1 == VT && N1C && N1C->isNullValue()) { 2025 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2026 AddToWorkList(XORNode.Val); 2027 return DAG.getNode(ISD::AND, VT, XORNode, N2); 2028 } 2029 // fold select C, X, 1 -> ~C | X 2030 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) { 2031 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2032 AddToWorkList(XORNode.Val); 2033 return DAG.getNode(ISD::OR, VT, XORNode, N1); 2034 } 2035 // fold select C, X, 0 -> C & X 2036 // FIXME: this should check for C type == X type, not i1? 2037 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 2038 return DAG.getNode(ISD::AND, VT, N0, N1); 2039 // fold X ? X : Y --> X ? 1 : Y --> X | Y 2040 if (MVT::i1 == VT && N0 == N1) 2041 return DAG.getNode(ISD::OR, VT, N0, N2); 2042 // fold X ? Y : X --> X ? Y : 0 --> X & Y 2043 if (MVT::i1 == VT && N0 == N2) 2044 return DAG.getNode(ISD::AND, VT, N0, N1); 2045 2046 // If we can fold this based on the true/false value, do so. 2047 if (SimplifySelectOps(N, N1, N2)) 2048 return SDOperand(N, 0); // Don't revisit N. 2049 2050 // fold selects based on a setcc into other things, such as min/max/abs 2051 if (N0.getOpcode() == ISD::SETCC) 2052 // FIXME: 2053 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2054 // having to say they don't support SELECT_CC on every type the DAG knows 2055 // about, since there is no way to mark an opcode illegal at all value types 2056 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 2057 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 2058 N1, N2, N0.getOperand(2)); 2059 else 2060 return SimplifySelect(N0, N1, N2); 2061 return SDOperand(); 2062} 2063 2064SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 2065 SDOperand N0 = N->getOperand(0); 2066 SDOperand N1 = N->getOperand(1); 2067 SDOperand N2 = N->getOperand(2); 2068 SDOperand N3 = N->getOperand(3); 2069 SDOperand N4 = N->getOperand(4); 2070 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2071 2072 // fold select_cc lhs, rhs, x, x, cc -> x 2073 if (N2 == N3) 2074 return N2; 2075 2076 // Determine if the condition we're dealing with is constant 2077 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 2078 if (SCC.Val) AddToWorkList(SCC.Val); 2079 2080 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) { 2081 if (SCCC->getValue()) 2082 return N2; // cond always true -> true val 2083 else 2084 return N3; // cond always false -> false val 2085 } 2086 2087 // Fold to a simpler select_cc 2088 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) 2089 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(), 2090 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2091 SCC.getOperand(2)); 2092 2093 // If we can fold this based on the true/false value, do so. 2094 if (SimplifySelectOps(N, N2, N3)) 2095 return SDOperand(N, 0); // Don't revisit N. 2096 2097 // fold select_cc into other things, such as min/max/abs 2098 return SimplifySelectCC(N0, N1, N2, N3, CC); 2099} 2100 2101SDOperand DAGCombiner::visitSETCC(SDNode *N) { 2102 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2103 cast<CondCodeSDNode>(N->getOperand(2))->get()); 2104} 2105 2106SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2107 SDOperand N0 = N->getOperand(0); 2108 MVT::ValueType VT = N->getValueType(0); 2109 2110 // fold (sext c1) -> c1 2111 if (isa<ConstantSDNode>(N0)) 2112 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 2113 2114 // fold (sext (sext x)) -> (sext x) 2115 // fold (sext (aext x)) -> (sext x) 2116 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2117 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 2118 2119 // fold (sext (truncate x)) -> (sextinreg x). 2120 if (N0.getOpcode() == ISD::TRUNCATE && 2121 (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 2122 N0.getValueType()))) { 2123 SDOperand Op = N0.getOperand(0); 2124 if (Op.getValueType() < VT) { 2125 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2126 } else if (Op.getValueType() > VT) { 2127 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2128 } 2129 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op, 2130 DAG.getValueType(N0.getValueType())); 2131 } 2132 2133 // fold (sext (load x)) -> (sext (truncate (sextload x))) 2134 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2135 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){ 2136 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2137 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2138 LN0->getBasePtr(), LN0->getSrcValue(), 2139 LN0->getSrcValueOffset(), 2140 N0.getValueType()); 2141 CombineTo(N, ExtLoad); 2142 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2143 ExtLoad.getValue(1)); 2144 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2145 } 2146 2147 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 2148 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 2149 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && N0.hasOneUse()) { 2150 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2151 MVT::ValueType EVT = LN0->getLoadedVT(); 2152 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2153 LN0->getBasePtr(), LN0->getSrcValue(), 2154 LN0->getSrcValueOffset(), EVT); 2155 CombineTo(N, ExtLoad); 2156 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2157 ExtLoad.getValue(1)); 2158 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2159 } 2160 2161 return SDOperand(); 2162} 2163 2164SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 2165 SDOperand N0 = N->getOperand(0); 2166 MVT::ValueType VT = N->getValueType(0); 2167 2168 // fold (zext c1) -> c1 2169 if (isa<ConstantSDNode>(N0)) 2170 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2171 // fold (zext (zext x)) -> (zext x) 2172 // fold (zext (aext x)) -> (zext x) 2173 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2174 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 2175 2176 // fold (zext (truncate x)) -> (and x, mask) 2177 if (N0.getOpcode() == ISD::TRUNCATE && 2178 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) { 2179 SDOperand Op = N0.getOperand(0); 2180 if (Op.getValueType() < VT) { 2181 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2182 } else if (Op.getValueType() > VT) { 2183 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2184 } 2185 return DAG.getZeroExtendInReg(Op, N0.getValueType()); 2186 } 2187 2188 // fold (zext (and (trunc x), cst)) -> (and x, cst). 2189 if (N0.getOpcode() == ISD::AND && 2190 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2191 N0.getOperand(1).getOpcode() == ISD::Constant) { 2192 SDOperand X = N0.getOperand(0).getOperand(0); 2193 if (X.getValueType() < VT) { 2194 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2195 } else if (X.getValueType() > VT) { 2196 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2197 } 2198 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2199 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2200 } 2201 2202 // fold (zext (load x)) -> (zext (truncate (zextload x))) 2203 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2204 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 2205 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2206 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2207 LN0->getBasePtr(), LN0->getSrcValue(), 2208 LN0->getSrcValueOffset(), 2209 N0.getValueType()); 2210 CombineTo(N, ExtLoad); 2211 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2212 ExtLoad.getValue(1)); 2213 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2214 } 2215 2216 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 2217 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 2218 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && N0.hasOneUse()) { 2219 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2220 MVT::ValueType EVT = LN0->getLoadedVT(); 2221 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2222 LN0->getBasePtr(), LN0->getSrcValue(), 2223 LN0->getSrcValueOffset(), EVT); 2224 CombineTo(N, ExtLoad); 2225 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2226 ExtLoad.getValue(1)); 2227 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2228 } 2229 return SDOperand(); 2230} 2231 2232SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) { 2233 SDOperand N0 = N->getOperand(0); 2234 MVT::ValueType VT = N->getValueType(0); 2235 2236 // fold (aext c1) -> c1 2237 if (isa<ConstantSDNode>(N0)) 2238 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 2239 // fold (aext (aext x)) -> (aext x) 2240 // fold (aext (zext x)) -> (zext x) 2241 // fold (aext (sext x)) -> (sext x) 2242 if (N0.getOpcode() == ISD::ANY_EXTEND || 2243 N0.getOpcode() == ISD::ZERO_EXTEND || 2244 N0.getOpcode() == ISD::SIGN_EXTEND) 2245 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 2246 2247 // fold (aext (truncate x)) 2248 if (N0.getOpcode() == ISD::TRUNCATE) { 2249 SDOperand TruncOp = N0.getOperand(0); 2250 if (TruncOp.getValueType() == VT) 2251 return TruncOp; // x iff x size == zext size. 2252 if (TruncOp.getValueType() > VT) 2253 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp); 2254 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp); 2255 } 2256 2257 // fold (aext (and (trunc x), cst)) -> (and x, cst). 2258 if (N0.getOpcode() == ISD::AND && 2259 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2260 N0.getOperand(1).getOpcode() == ISD::Constant) { 2261 SDOperand X = N0.getOperand(0).getOperand(0); 2262 if (X.getValueType() < VT) { 2263 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2264 } else if (X.getValueType() > VT) { 2265 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2266 } 2267 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2268 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2269 } 2270 2271 // fold (aext (load x)) -> (aext (truncate (extload x))) 2272 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2273 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 2274 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2275 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 2276 LN0->getBasePtr(), LN0->getSrcValue(), 2277 LN0->getSrcValueOffset(), 2278 N0.getValueType()); 2279 CombineTo(N, ExtLoad); 2280 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2281 ExtLoad.getValue(1)); 2282 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2283 } 2284 2285 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 2286 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 2287 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 2288 if (N0.getOpcode() == ISD::LOAD && !ISD::isNON_EXTLoad(N0.Val) && 2289 N0.hasOneUse()) { 2290 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2291 MVT::ValueType EVT = LN0->getLoadedVT(); 2292 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, 2293 LN0->getChain(), LN0->getBasePtr(), 2294 LN0->getSrcValue(), 2295 LN0->getSrcValueOffset(), EVT); 2296 CombineTo(N, ExtLoad); 2297 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2298 ExtLoad.getValue(1)); 2299 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2300 } 2301 return SDOperand(); 2302} 2303 2304 2305SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 2306 SDOperand N0 = N->getOperand(0); 2307 SDOperand N1 = N->getOperand(1); 2308 MVT::ValueType VT = N->getValueType(0); 2309 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 2310 unsigned EVTBits = MVT::getSizeInBits(EVT); 2311 2312 // fold (sext_in_reg c1) -> c1 2313 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 2314 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 2315 2316 // If the input is already sign extended, just drop the extension. 2317 if (TLI.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1) 2318 return N0; 2319 2320 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 2321 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 2322 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 2323 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 2324 } 2325 2326 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero 2327 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1))) 2328 return DAG.getZeroExtendInReg(N0, EVT); 2329 2330 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 2331 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. 2332 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 2333 if (N0.getOpcode() == ISD::SRL) { 2334 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2335 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) { 2336 // We can turn this into an SRA iff the input to the SRL is already sign 2337 // extended enough. 2338 unsigned InSignBits = TLI.ComputeNumSignBits(N0.getOperand(0)); 2339 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits) 2340 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); 2341 } 2342 } 2343 2344 // fold (sext_inreg (extload x)) -> (sextload x) 2345 if (ISD::isEXTLoad(N0.Val) && 2346 EVT == cast<LoadSDNode>(N0)->getLoadedVT() && 2347 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 2348 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2349 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2350 LN0->getBasePtr(), LN0->getSrcValue(), 2351 LN0->getSrcValueOffset(), EVT); 2352 CombineTo(N, ExtLoad); 2353 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 2354 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2355 } 2356 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 2357 if (ISD::isZEXTLoad(N0.Val) && N0.hasOneUse() && 2358 EVT == cast<LoadSDNode>(N0)->getLoadedVT() && 2359 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 2360 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2361 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2362 LN0->getBasePtr(), LN0->getSrcValue(), 2363 LN0->getSrcValueOffset(), EVT); 2364 CombineTo(N, ExtLoad); 2365 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 2366 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2367 } 2368 return SDOperand(); 2369} 2370 2371SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 2372 SDOperand N0 = N->getOperand(0); 2373 MVT::ValueType VT = N->getValueType(0); 2374 2375 // noop truncate 2376 if (N0.getValueType() == N->getValueType(0)) 2377 return N0; 2378 // fold (truncate c1) -> c1 2379 if (isa<ConstantSDNode>(N0)) 2380 return DAG.getNode(ISD::TRUNCATE, VT, N0); 2381 // fold (truncate (truncate x)) -> (truncate x) 2382 if (N0.getOpcode() == ISD::TRUNCATE) 2383 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 2384 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 2385 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 2386 N0.getOpcode() == ISD::ANY_EXTEND) { 2387 if (N0.getValueType() < VT) 2388 // if the source is smaller than the dest, we still need an extend 2389 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 2390 else if (N0.getValueType() > VT) 2391 // if the source is larger than the dest, than we just need the truncate 2392 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 2393 else 2394 // if the source and dest are the same type, we can drop both the extend 2395 // and the truncate 2396 return N0.getOperand(0); 2397 } 2398 // fold (truncate (load x)) -> (smaller load x) 2399 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse()) { 2400 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) && 2401 "Cannot truncate to larger type!"); 2402 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2403 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 2404 // For big endian targets, we need to add an offset to the pointer to load 2405 // the correct bytes. For little endian systems, we merely need to read 2406 // fewer bytes from the same pointer. 2407 uint64_t PtrOff = 2408 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8; 2409 SDOperand NewPtr = TLI.isLittleEndian() ? LN0->getBasePtr() : 2410 DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(), 2411 DAG.getConstant(PtrOff, PtrType)); 2412 AddToWorkList(NewPtr.Val); 2413 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), NewPtr, 2414 LN0->getSrcValue(), LN0->getSrcValueOffset()); 2415 AddToWorkList(N); 2416 CombineTo(N0.Val, Load, Load.getValue(1)); 2417 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2418 } 2419 return SDOperand(); 2420} 2421 2422SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { 2423 SDOperand N0 = N->getOperand(0); 2424 MVT::ValueType VT = N->getValueType(0); 2425 2426 // If the input is a constant, let getNode() fold it. 2427 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 2428 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 2429 if (Res.Val != N) return Res; 2430 } 2431 2432 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 2433 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 2434 2435 // fold (conv (load x)) -> (load (conv*)x) 2436 // FIXME: These xforms need to know that the resultant load doesn't need a 2437 // higher alignment than the original! 2438 if (0 && ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse()) { 2439 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2440 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(), 2441 LN0->getSrcValue(), LN0->getSrcValueOffset()); 2442 AddToWorkList(N); 2443 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 2444 Load.getValue(1)); 2445 return Load; 2446 } 2447 2448 return SDOperand(); 2449} 2450 2451SDOperand DAGCombiner::visitVBIT_CONVERT(SDNode *N) { 2452 SDOperand N0 = N->getOperand(0); 2453 MVT::ValueType VT = N->getValueType(0); 2454 2455 // If the input is a VBUILD_VECTOR with all constant elements, fold this now. 2456 // First check to see if this is all constant. 2457 if (N0.getOpcode() == ISD::VBUILD_VECTOR && N0.Val->hasOneUse() && 2458 VT == MVT::Vector) { 2459 bool isSimple = true; 2460 for (unsigned i = 0, e = N0.getNumOperands()-2; i != e; ++i) 2461 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 2462 N0.getOperand(i).getOpcode() != ISD::Constant && 2463 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 2464 isSimple = false; 2465 break; 2466 } 2467 2468 MVT::ValueType DestEltVT = cast<VTSDNode>(N->getOperand(2))->getVT(); 2469 if (isSimple && !MVT::isVector(DestEltVT)) { 2470 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(N0.Val, DestEltVT); 2471 } 2472 } 2473 2474 return SDOperand(); 2475} 2476 2477/// ConstantFoldVBIT_CONVERTofVBUILD_VECTOR - We know that BV is a vbuild_vector 2478/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 2479/// destination element value type. 2480SDOperand DAGCombiner:: 2481ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) { 2482 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType(); 2483 2484 // If this is already the right type, we're done. 2485 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0); 2486 2487 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT); 2488 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT); 2489 2490 // If this is a conversion of N elements of one type to N elements of another 2491 // type, convert each element. This handles FP<->INT cases. 2492 if (SrcBitSize == DstBitSize) { 2493 SmallVector<SDOperand, 8> Ops; 2494 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) { 2495 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 2496 AddToWorkList(Ops.back().Val); 2497 } 2498 Ops.push_back(*(BV->op_end()-2)); // Add num elements. 2499 Ops.push_back(DAG.getValueType(DstEltVT)); 2500 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 2501 } 2502 2503 // Otherwise, we're growing or shrinking the elements. To avoid having to 2504 // handle annoying details of growing/shrinking FP values, we convert them to 2505 // int first. 2506 if (MVT::isFloatingPoint(SrcEltVT)) { 2507 // Convert the input float vector to a int vector where the elements are the 2508 // same sizes. 2509 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 2510 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 2511 BV = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, IntVT).Val; 2512 SrcEltVT = IntVT; 2513 } 2514 2515 // Now we know the input is an integer vector. If the output is a FP type, 2516 // convert to integer first, then to FP of the right size. 2517 if (MVT::isFloatingPoint(DstEltVT)) { 2518 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 2519 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 2520 SDNode *Tmp = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, TmpVT).Val; 2521 2522 // Next, convert to FP elements of the same size. 2523 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(Tmp, DstEltVT); 2524 } 2525 2526 // Okay, we know the src/dst types are both integers of differing types. 2527 // Handling growing first. 2528 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT)); 2529 if (SrcBitSize < DstBitSize) { 2530 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 2531 2532 SmallVector<SDOperand, 8> Ops; 2533 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; 2534 i += NumInputsPerOutput) { 2535 bool isLE = TLI.isLittleEndian(); 2536 uint64_t NewBits = 0; 2537 bool EltIsUndef = true; 2538 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 2539 // Shift the previously computed bits over. 2540 NewBits <<= SrcBitSize; 2541 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 2542 if (Op.getOpcode() == ISD::UNDEF) continue; 2543 EltIsUndef = false; 2544 2545 NewBits |= cast<ConstantSDNode>(Op)->getValue(); 2546 } 2547 2548 if (EltIsUndef) 2549 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 2550 else 2551 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 2552 } 2553 2554 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements. 2555 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size. 2556 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 2557 } 2558 2559 // Finally, this must be the case where we are shrinking elements: each input 2560 // turns into multiple outputs. 2561 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 2562 SmallVector<SDOperand, 8> Ops; 2563 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) { 2564 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 2565 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 2566 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 2567 continue; 2568 } 2569 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue(); 2570 2571 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 2572 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1); 2573 OpVal >>= DstBitSize; 2574 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 2575 } 2576 2577 // For big endian targets, swap the order of the pieces of each element. 2578 if (!TLI.isLittleEndian()) 2579 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 2580 } 2581 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements. 2582 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size. 2583 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 2584} 2585 2586 2587 2588SDOperand DAGCombiner::visitFADD(SDNode *N) { 2589 SDOperand N0 = N->getOperand(0); 2590 SDOperand N1 = N->getOperand(1); 2591 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2592 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2593 MVT::ValueType VT = N->getValueType(0); 2594 2595 // fold (fadd c1, c2) -> c1+c2 2596 if (N0CFP && N1CFP) 2597 return DAG.getNode(ISD::FADD, VT, N0, N1); 2598 // canonicalize constant to RHS 2599 if (N0CFP && !N1CFP) 2600 return DAG.getNode(ISD::FADD, VT, N1, N0); 2601 // fold (A + (-B)) -> A-B 2602 if (N1.getOpcode() == ISD::FNEG) 2603 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0)); 2604 // fold ((-A) + B) -> B-A 2605 if (N0.getOpcode() == ISD::FNEG) 2606 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0)); 2607 return SDOperand(); 2608} 2609 2610SDOperand DAGCombiner::visitFSUB(SDNode *N) { 2611 SDOperand N0 = N->getOperand(0); 2612 SDOperand N1 = N->getOperand(1); 2613 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2614 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2615 MVT::ValueType VT = N->getValueType(0); 2616 2617 // fold (fsub c1, c2) -> c1-c2 2618 if (N0CFP && N1CFP) 2619 return DAG.getNode(ISD::FSUB, VT, N0, N1); 2620 // fold (A-(-B)) -> A+B 2621 if (N1.getOpcode() == ISD::FNEG) 2622 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0)); 2623 return SDOperand(); 2624} 2625 2626SDOperand DAGCombiner::visitFMUL(SDNode *N) { 2627 SDOperand N0 = N->getOperand(0); 2628 SDOperand N1 = N->getOperand(1); 2629 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2630 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2631 MVT::ValueType VT = N->getValueType(0); 2632 2633 // fold (fmul c1, c2) -> c1*c2 2634 if (N0CFP && N1CFP) 2635 return DAG.getNode(ISD::FMUL, VT, N0, N1); 2636 // canonicalize constant to RHS 2637 if (N0CFP && !N1CFP) 2638 return DAG.getNode(ISD::FMUL, VT, N1, N0); 2639 // fold (fmul X, 2.0) -> (fadd X, X) 2640 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 2641 return DAG.getNode(ISD::FADD, VT, N0, N0); 2642 return SDOperand(); 2643} 2644 2645SDOperand DAGCombiner::visitFDIV(SDNode *N) { 2646 SDOperand N0 = N->getOperand(0); 2647 SDOperand N1 = N->getOperand(1); 2648 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2649 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2650 MVT::ValueType VT = N->getValueType(0); 2651 2652 // fold (fdiv c1, c2) -> c1/c2 2653 if (N0CFP && N1CFP) 2654 return DAG.getNode(ISD::FDIV, VT, N0, N1); 2655 return SDOperand(); 2656} 2657 2658SDOperand DAGCombiner::visitFREM(SDNode *N) { 2659 SDOperand N0 = N->getOperand(0); 2660 SDOperand N1 = N->getOperand(1); 2661 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2662 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2663 MVT::ValueType VT = N->getValueType(0); 2664 2665 // fold (frem c1, c2) -> fmod(c1,c2) 2666 if (N0CFP && N1CFP) 2667 return DAG.getNode(ISD::FREM, VT, N0, N1); 2668 return SDOperand(); 2669} 2670 2671SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) { 2672 SDOperand N0 = N->getOperand(0); 2673 SDOperand N1 = N->getOperand(1); 2674 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2675 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2676 MVT::ValueType VT = N->getValueType(0); 2677 2678 if (N0CFP && N1CFP) // Constant fold 2679 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 2680 2681 if (N1CFP) { 2682 // copysign(x, c1) -> fabs(x) iff ispos(c1) 2683 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 2684 union { 2685 double d; 2686 int64_t i; 2687 } u; 2688 u.d = N1CFP->getValue(); 2689 if (u.i >= 0) 2690 return DAG.getNode(ISD::FABS, VT, N0); 2691 else 2692 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 2693 } 2694 2695 // copysign(fabs(x), y) -> copysign(x, y) 2696 // copysign(fneg(x), y) -> copysign(x, y) 2697 // copysign(copysign(x,z), y) -> copysign(x, y) 2698 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 2699 N0.getOpcode() == ISD::FCOPYSIGN) 2700 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 2701 2702 // copysign(x, abs(y)) -> abs(x) 2703 if (N1.getOpcode() == ISD::FABS) 2704 return DAG.getNode(ISD::FABS, VT, N0); 2705 2706 // copysign(x, copysign(y,z)) -> copysign(x, z) 2707 if (N1.getOpcode() == ISD::FCOPYSIGN) 2708 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 2709 2710 // copysign(x, fp_extend(y)) -> copysign(x, y) 2711 // copysign(x, fp_round(y)) -> copysign(x, y) 2712 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 2713 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 2714 2715 return SDOperand(); 2716} 2717 2718 2719 2720SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 2721 SDOperand N0 = N->getOperand(0); 2722 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2723 MVT::ValueType VT = N->getValueType(0); 2724 2725 // fold (sint_to_fp c1) -> c1fp 2726 if (N0C) 2727 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 2728 return SDOperand(); 2729} 2730 2731SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 2732 SDOperand N0 = N->getOperand(0); 2733 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2734 MVT::ValueType VT = N->getValueType(0); 2735 2736 // fold (uint_to_fp c1) -> c1fp 2737 if (N0C) 2738 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 2739 return SDOperand(); 2740} 2741 2742SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 2743 SDOperand N0 = N->getOperand(0); 2744 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2745 MVT::ValueType VT = N->getValueType(0); 2746 2747 // fold (fp_to_sint c1fp) -> c1 2748 if (N0CFP) 2749 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 2750 return SDOperand(); 2751} 2752 2753SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 2754 SDOperand N0 = N->getOperand(0); 2755 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2756 MVT::ValueType VT = N->getValueType(0); 2757 2758 // fold (fp_to_uint c1fp) -> c1 2759 if (N0CFP) 2760 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 2761 return SDOperand(); 2762} 2763 2764SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 2765 SDOperand N0 = N->getOperand(0); 2766 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2767 MVT::ValueType VT = N->getValueType(0); 2768 2769 // fold (fp_round c1fp) -> c1fp 2770 if (N0CFP) 2771 return DAG.getNode(ISD::FP_ROUND, VT, N0); 2772 2773 // fold (fp_round (fp_extend x)) -> x 2774 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 2775 return N0.getOperand(0); 2776 2777 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 2778 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) { 2779 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0)); 2780 AddToWorkList(Tmp.Val); 2781 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 2782 } 2783 2784 return SDOperand(); 2785} 2786 2787SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 2788 SDOperand N0 = N->getOperand(0); 2789 MVT::ValueType VT = N->getValueType(0); 2790 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 2791 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2792 2793 // fold (fp_round_inreg c1fp) -> c1fp 2794 if (N0CFP) { 2795 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT); 2796 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 2797 } 2798 return SDOperand(); 2799} 2800 2801SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 2802 SDOperand N0 = N->getOperand(0); 2803 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2804 MVT::ValueType VT = N->getValueType(0); 2805 2806 // fold (fp_extend c1fp) -> c1fp 2807 if (N0CFP) 2808 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 2809 2810 // fold (fpext (load x)) -> (fpext (fpround (extload x))) 2811 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2812 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 2813 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2814 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 2815 LN0->getBasePtr(), LN0->getSrcValue(), 2816 LN0->getSrcValueOffset(), 2817 N0.getValueType()); 2818 CombineTo(N, ExtLoad); 2819 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad), 2820 ExtLoad.getValue(1)); 2821 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2822 } 2823 2824 2825 return SDOperand(); 2826} 2827 2828SDOperand DAGCombiner::visitFNEG(SDNode *N) { 2829 SDOperand N0 = N->getOperand(0); 2830 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2831 MVT::ValueType VT = N->getValueType(0); 2832 2833 // fold (fneg c1) -> -c1 2834 if (N0CFP) 2835 return DAG.getNode(ISD::FNEG, VT, N0); 2836 // fold (fneg (sub x, y)) -> (sub y, x) 2837 if (N0.getOpcode() == ISD::SUB) 2838 return DAG.getNode(ISD::SUB, VT, N0.getOperand(1), N0.getOperand(0)); 2839 // fold (fneg (fneg x)) -> x 2840 if (N0.getOpcode() == ISD::FNEG) 2841 return N0.getOperand(0); 2842 return SDOperand(); 2843} 2844 2845SDOperand DAGCombiner::visitFABS(SDNode *N) { 2846 SDOperand N0 = N->getOperand(0); 2847 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2848 MVT::ValueType VT = N->getValueType(0); 2849 2850 // fold (fabs c1) -> fabs(c1) 2851 if (N0CFP) 2852 return DAG.getNode(ISD::FABS, VT, N0); 2853 // fold (fabs (fabs x)) -> (fabs x) 2854 if (N0.getOpcode() == ISD::FABS) 2855 return N->getOperand(0); 2856 // fold (fabs (fneg x)) -> (fabs x) 2857 // fold (fabs (fcopysign x, y)) -> (fabs x) 2858 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 2859 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 2860 2861 return SDOperand(); 2862} 2863 2864SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 2865 SDOperand Chain = N->getOperand(0); 2866 SDOperand N1 = N->getOperand(1); 2867 SDOperand N2 = N->getOperand(2); 2868 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2869 2870 // never taken branch, fold to chain 2871 if (N1C && N1C->isNullValue()) 2872 return Chain; 2873 // unconditional branch 2874 if (N1C && N1C->getValue() == 1) 2875 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 2876 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 2877 // on the target. 2878 if (N1.getOpcode() == ISD::SETCC && 2879 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 2880 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 2881 N1.getOperand(0), N1.getOperand(1), N2); 2882 } 2883 return SDOperand(); 2884} 2885 2886// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 2887// 2888SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 2889 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 2890 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 2891 2892 // Use SimplifySetCC to simplify SETCC's. 2893 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 2894 if (Simp.Val) AddToWorkList(Simp.Val); 2895 2896 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 2897 2898 // fold br_cc true, dest -> br dest (unconditional branch) 2899 if (SCCC && SCCC->getValue()) 2900 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 2901 N->getOperand(4)); 2902 // fold br_cc false, dest -> unconditional fall through 2903 if (SCCC && SCCC->isNullValue()) 2904 return N->getOperand(0); 2905 2906 // fold to a simpler setcc 2907 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 2908 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 2909 Simp.getOperand(2), Simp.getOperand(0), 2910 Simp.getOperand(1), N->getOperand(4)); 2911 return SDOperand(); 2912} 2913 2914SDOperand DAGCombiner::visitLOAD(SDNode *N) { 2915 LoadSDNode *LD = cast<LoadSDNode>(N); 2916 SDOperand Chain = LD->getChain(); 2917 SDOperand Ptr = LD->getBasePtr(); 2918 2919 // If there are no uses of the loaded value, change uses of the chain value 2920 // into uses of the chain input (i.e. delete the dead load). 2921 if (N->hasNUsesOfValue(0, 0)) 2922 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain); 2923 2924 // If this load is directly stored, replace the load value with the stored 2925 // value. 2926 // TODO: Handle store large -> read small portion. 2927 // TODO: Handle TRUNCSTORE/LOADEXT 2928 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 2929 if (ISD::isNON_TRUNCStore(Chain.Val)) { 2930 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 2931 if (PrevST->getBasePtr() == Ptr && 2932 PrevST->getValue().getValueType() == N->getValueType(0)) 2933 return CombineTo(N, Chain.getOperand(1), Chain); 2934 } 2935 } 2936 2937 if (CombinerAA) { 2938 // Walk up chain skipping non-aliasing memory nodes. 2939 SDOperand BetterChain = FindBetterChain(N, Chain); 2940 2941 // If there is a better chain. 2942 if (Chain != BetterChain) { 2943 SDOperand ReplLoad; 2944 2945 // Replace the chain to void dependency. 2946 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 2947 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr, 2948 LD->getSrcValue(), LD->getSrcValueOffset()); 2949 } else { 2950 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), 2951 LD->getValueType(0), 2952 BetterChain, Ptr, LD->getSrcValue(), 2953 LD->getSrcValueOffset(), 2954 LD->getLoadedVT()); 2955 } 2956 2957 // Create token factor to keep old chain connected. 2958 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other, 2959 Chain, ReplLoad.getValue(1)); 2960 2961 // Replace uses with load result and token factor. Don't add users 2962 // to work list. 2963 return CombineTo(N, ReplLoad.getValue(0), Token, false); 2964 } 2965 } 2966 2967 // Try transforming N to an indexed load. 2968 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 2969 return SDOperand(N, 0); 2970 2971 return SDOperand(); 2972} 2973 2974SDOperand DAGCombiner::visitSTORE(SDNode *N) { 2975 StoreSDNode *ST = cast<StoreSDNode>(N); 2976 SDOperand Chain = ST->getChain(); 2977 SDOperand Value = ST->getValue(); 2978 SDOperand Ptr = ST->getBasePtr(); 2979 2980 // If this is a store of a bit convert, store the input value. 2981 // FIXME: This needs to know that the resultant store does not need a 2982 // higher alignment than the original. 2983 if (0 && Value.getOpcode() == ISD::BIT_CONVERT) { 2984 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 2985 ST->getSrcValueOffset()); 2986 } 2987 2988 if (CombinerAA) { 2989 // Walk up chain skipping non-aliasing memory nodes. 2990 SDOperand BetterChain = FindBetterChain(N, Chain); 2991 2992 // If there is a better chain. 2993 if (Chain != BetterChain) { 2994 // Replace the chain to avoid dependency. 2995 SDOperand ReplStore; 2996 if (ST->isTruncatingStore()) { 2997 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr, 2998 ST->getSrcValue(),ST->getSrcValueOffset(), ST->getStoredVT()); 2999 } else { 3000 ReplStore = DAG.getStore(BetterChain, Value, Ptr, 3001 ST->getSrcValue(), ST->getSrcValueOffset()); 3002 } 3003 3004 // Create token to keep both nodes around. 3005 SDOperand Token = 3006 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore); 3007 3008 // Don't add users to work list. 3009 return CombineTo(N, Token, false); 3010 } 3011 } 3012 3013 // Try transforming N to an indexed store. 3014 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 3015 return SDOperand(N, 0); 3016 3017 return SDOperand(); 3018} 3019 3020SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 3021 SDOperand InVec = N->getOperand(0); 3022 SDOperand InVal = N->getOperand(1); 3023 SDOperand EltNo = N->getOperand(2); 3024 3025 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 3026 // vector with the inserted element. 3027 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 3028 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 3029 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 3030 if (Elt < Ops.size()) 3031 Ops[Elt] = InVal; 3032 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), 3033 &Ops[0], Ops.size()); 3034 } 3035 3036 return SDOperand(); 3037} 3038 3039SDOperand DAGCombiner::visitVINSERT_VECTOR_ELT(SDNode *N) { 3040 SDOperand InVec = N->getOperand(0); 3041 SDOperand InVal = N->getOperand(1); 3042 SDOperand EltNo = N->getOperand(2); 3043 SDOperand NumElts = N->getOperand(3); 3044 SDOperand EltType = N->getOperand(4); 3045 3046 // If the invec is a VBUILD_VECTOR and if EltNo is a constant, build a new 3047 // vector with the inserted element. 3048 if (InVec.getOpcode() == ISD::VBUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 3049 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 3050 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 3051 if (Elt < Ops.size()-2) 3052 Ops[Elt] = InVal; 3053 return DAG.getNode(ISD::VBUILD_VECTOR, InVec.getValueType(), 3054 &Ops[0], Ops.size()); 3055 } 3056 3057 return SDOperand(); 3058} 3059 3060SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) { 3061 unsigned NumInScalars = N->getNumOperands()-2; 3062 SDOperand NumElts = N->getOperand(NumInScalars); 3063 SDOperand EltType = N->getOperand(NumInScalars+1); 3064 3065 // Check to see if this is a VBUILD_VECTOR of a bunch of VEXTRACT_VECTOR_ELT 3066 // operations. If so, and if the EXTRACT_ELT vector inputs come from at most 3067 // two distinct vectors, turn this into a shuffle node. 3068 SDOperand VecIn1, VecIn2; 3069 for (unsigned i = 0; i != NumInScalars; ++i) { 3070 // Ignore undef inputs. 3071 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 3072 3073 // If this input is something other than a VEXTRACT_VECTOR_ELT with a 3074 // constant index, bail out. 3075 if (N->getOperand(i).getOpcode() != ISD::VEXTRACT_VECTOR_ELT || 3076 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 3077 VecIn1 = VecIn2 = SDOperand(0, 0); 3078 break; 3079 } 3080 3081 // If the input vector type disagrees with the result of the vbuild_vector, 3082 // we can't make a shuffle. 3083 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0); 3084 if (*(ExtractedFromVec.Val->op_end()-2) != NumElts || 3085 *(ExtractedFromVec.Val->op_end()-1) != EltType) { 3086 VecIn1 = VecIn2 = SDOperand(0, 0); 3087 break; 3088 } 3089 3090 // Otherwise, remember this. We allow up to two distinct input vectors. 3091 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 3092 continue; 3093 3094 if (VecIn1.Val == 0) { 3095 VecIn1 = ExtractedFromVec; 3096 } else if (VecIn2.Val == 0) { 3097 VecIn2 = ExtractedFromVec; 3098 } else { 3099 // Too many inputs. 3100 VecIn1 = VecIn2 = SDOperand(0, 0); 3101 break; 3102 } 3103 } 3104 3105 // If everything is good, we can make a shuffle operation. 3106 if (VecIn1.Val) { 3107 SmallVector<SDOperand, 8> BuildVecIndices; 3108 for (unsigned i = 0; i != NumInScalars; ++i) { 3109 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 3110 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 3111 continue; 3112 } 3113 3114 SDOperand Extract = N->getOperand(i); 3115 3116 // If extracting from the first vector, just use the index directly. 3117 if (Extract.getOperand(0) == VecIn1) { 3118 BuildVecIndices.push_back(Extract.getOperand(1)); 3119 continue; 3120 } 3121 3122 // Otherwise, use InIdx + VecSize 3123 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue(); 3124 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, MVT::i32)); 3125 } 3126 3127 // Add count and size info. 3128 BuildVecIndices.push_back(NumElts); 3129 BuildVecIndices.push_back(DAG.getValueType(MVT::i32)); 3130 3131 // Return the new VVECTOR_SHUFFLE node. 3132 SDOperand Ops[5]; 3133 Ops[0] = VecIn1; 3134 if (VecIn2.Val) { 3135 Ops[1] = VecIn2; 3136 } else { 3137 // Use an undef vbuild_vector as input for the second operand. 3138 std::vector<SDOperand> UnOps(NumInScalars, 3139 DAG.getNode(ISD::UNDEF, 3140 cast<VTSDNode>(EltType)->getVT())); 3141 UnOps.push_back(NumElts); 3142 UnOps.push_back(EltType); 3143 Ops[1] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 3144 &UnOps[0], UnOps.size()); 3145 AddToWorkList(Ops[1].Val); 3146 } 3147 Ops[2] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 3148 &BuildVecIndices[0], BuildVecIndices.size()); 3149 Ops[3] = NumElts; 3150 Ops[4] = EltType; 3151 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops, 5); 3152 } 3153 3154 return SDOperand(); 3155} 3156 3157SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 3158 SDOperand ShufMask = N->getOperand(2); 3159 unsigned NumElts = ShufMask.getNumOperands(); 3160 3161 // If the shuffle mask is an identity operation on the LHS, return the LHS. 3162 bool isIdentity = true; 3163 for (unsigned i = 0; i != NumElts; ++i) { 3164 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 3165 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 3166 isIdentity = false; 3167 break; 3168 } 3169 } 3170 if (isIdentity) return N->getOperand(0); 3171 3172 // If the shuffle mask is an identity operation on the RHS, return the RHS. 3173 isIdentity = true; 3174 for (unsigned i = 0; i != NumElts; ++i) { 3175 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 3176 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 3177 isIdentity = false; 3178 break; 3179 } 3180 } 3181 if (isIdentity) return N->getOperand(1); 3182 3183 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 3184 // needed at all. 3185 bool isUnary = true; 3186 bool isSplat = true; 3187 int VecNum = -1; 3188 unsigned BaseIdx = 0; 3189 for (unsigned i = 0; i != NumElts; ++i) 3190 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 3191 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue(); 3192 int V = (Idx < NumElts) ? 0 : 1; 3193 if (VecNum == -1) { 3194 VecNum = V; 3195 BaseIdx = Idx; 3196 } else { 3197 if (BaseIdx != Idx) 3198 isSplat = false; 3199 if (VecNum != V) { 3200 isUnary = false; 3201 break; 3202 } 3203 } 3204 } 3205 3206 SDOperand N0 = N->getOperand(0); 3207 SDOperand N1 = N->getOperand(1); 3208 // Normalize unary shuffle so the RHS is undef. 3209 if (isUnary && VecNum == 1) 3210 std::swap(N0, N1); 3211 3212 // If it is a splat, check if the argument vector is a build_vector with 3213 // all scalar elements the same. 3214 if (isSplat) { 3215 SDNode *V = N0.Val; 3216 if (V->getOpcode() == ISD::BIT_CONVERT) 3217 V = V->getOperand(0).Val; 3218 if (V->getOpcode() == ISD::BUILD_VECTOR) { 3219 unsigned NumElems = V->getNumOperands()-2; 3220 if (NumElems > BaseIdx) { 3221 SDOperand Base; 3222 bool AllSame = true; 3223 for (unsigned i = 0; i != NumElems; ++i) { 3224 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 3225 Base = V->getOperand(i); 3226 break; 3227 } 3228 } 3229 // Splat of <u, u, u, u>, return <u, u, u, u> 3230 if (!Base.Val) 3231 return N0; 3232 for (unsigned i = 0; i != NumElems; ++i) { 3233 if (V->getOperand(i).getOpcode() != ISD::UNDEF && 3234 V->getOperand(i) != Base) { 3235 AllSame = false; 3236 break; 3237 } 3238 } 3239 // Splat of <x, x, x, x>, return <x, x, x, x> 3240 if (AllSame) 3241 return N0; 3242 } 3243 } 3244 } 3245 3246 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 3247 // into an undef. 3248 if (isUnary || N0 == N1) { 3249 if (N0.getOpcode() == ISD::UNDEF) 3250 return DAG.getNode(ISD::UNDEF, N->getValueType(0)); 3251 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 3252 // first operand. 3253 SmallVector<SDOperand, 8> MappedOps; 3254 for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) { 3255 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 3256 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 3257 MappedOps.push_back(ShufMask.getOperand(i)); 3258 } else { 3259 unsigned NewIdx = 3260 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 3261 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 3262 } 3263 } 3264 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 3265 &MappedOps[0], MappedOps.size()); 3266 AddToWorkList(ShufMask.Val); 3267 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 3268 N0, 3269 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 3270 ShufMask); 3271 } 3272 3273 return SDOperand(); 3274} 3275 3276SDOperand DAGCombiner::visitVVECTOR_SHUFFLE(SDNode *N) { 3277 SDOperand ShufMask = N->getOperand(2); 3278 unsigned NumElts = ShufMask.getNumOperands()-2; 3279 3280 // If the shuffle mask is an identity operation on the LHS, return the LHS. 3281 bool isIdentity = true; 3282 for (unsigned i = 0; i != NumElts; ++i) { 3283 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 3284 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 3285 isIdentity = false; 3286 break; 3287 } 3288 } 3289 if (isIdentity) return N->getOperand(0); 3290 3291 // If the shuffle mask is an identity operation on the RHS, return the RHS. 3292 isIdentity = true; 3293 for (unsigned i = 0; i != NumElts; ++i) { 3294 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 3295 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 3296 isIdentity = false; 3297 break; 3298 } 3299 } 3300 if (isIdentity) return N->getOperand(1); 3301 3302 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 3303 // needed at all. 3304 bool isUnary = true; 3305 bool isSplat = true; 3306 int VecNum = -1; 3307 unsigned BaseIdx = 0; 3308 for (unsigned i = 0; i != NumElts; ++i) 3309 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 3310 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue(); 3311 int V = (Idx < NumElts) ? 0 : 1; 3312 if (VecNum == -1) { 3313 VecNum = V; 3314 BaseIdx = Idx; 3315 } else { 3316 if (BaseIdx != Idx) 3317 isSplat = false; 3318 if (VecNum != V) { 3319 isUnary = false; 3320 break; 3321 } 3322 } 3323 } 3324 3325 SDOperand N0 = N->getOperand(0); 3326 SDOperand N1 = N->getOperand(1); 3327 // Normalize unary shuffle so the RHS is undef. 3328 if (isUnary && VecNum == 1) 3329 std::swap(N0, N1); 3330 3331 // If it is a splat, check if the argument vector is a build_vector with 3332 // all scalar elements the same. 3333 if (isSplat) { 3334 SDNode *V = N0.Val; 3335 3336 // If this is a vbit convert that changes the element type of the vector but 3337 // not the number of vector elements, look through it. Be careful not to 3338 // look though conversions that change things like v4f32 to v2f64. 3339 if (V->getOpcode() == ISD::VBIT_CONVERT) { 3340 SDOperand ConvInput = V->getOperand(0); 3341 if (ConvInput.getValueType() == MVT::Vector && 3342 NumElts == 3343 ConvInput.getConstantOperandVal(ConvInput.getNumOperands()-2)) 3344 V = ConvInput.Val; 3345 } 3346 3347 if (V->getOpcode() == ISD::VBUILD_VECTOR) { 3348 unsigned NumElems = V->getNumOperands()-2; 3349 if (NumElems > BaseIdx) { 3350 SDOperand Base; 3351 bool AllSame = true; 3352 for (unsigned i = 0; i != NumElems; ++i) { 3353 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 3354 Base = V->getOperand(i); 3355 break; 3356 } 3357 } 3358 // Splat of <u, u, u, u>, return <u, u, u, u> 3359 if (!Base.Val) 3360 return N0; 3361 for (unsigned i = 0; i != NumElems; ++i) { 3362 if (V->getOperand(i).getOpcode() != ISD::UNDEF && 3363 V->getOperand(i) != Base) { 3364 AllSame = false; 3365 break; 3366 } 3367 } 3368 // Splat of <x, x, x, x>, return <x, x, x, x> 3369 if (AllSame) 3370 return N0; 3371 } 3372 } 3373 } 3374 3375 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 3376 // into an undef. 3377 if (isUnary || N0 == N1) { 3378 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 3379 // first operand. 3380 SmallVector<SDOperand, 8> MappedOps; 3381 for (unsigned i = 0; i != NumElts; ++i) { 3382 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 3383 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 3384 MappedOps.push_back(ShufMask.getOperand(i)); 3385 } else { 3386 unsigned NewIdx = 3387 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 3388 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 3389 } 3390 } 3391 // Add the type/#elts values. 3392 MappedOps.push_back(ShufMask.getOperand(NumElts)); 3393 MappedOps.push_back(ShufMask.getOperand(NumElts+1)); 3394 3395 ShufMask = DAG.getNode(ISD::VBUILD_VECTOR, ShufMask.getValueType(), 3396 &MappedOps[0], MappedOps.size()); 3397 AddToWorkList(ShufMask.Val); 3398 3399 // Build the undef vector. 3400 SDOperand UDVal = DAG.getNode(ISD::UNDEF, MappedOps[0].getValueType()); 3401 for (unsigned i = 0; i != NumElts; ++i) 3402 MappedOps[i] = UDVal; 3403 MappedOps[NumElts ] = *(N0.Val->op_end()-2); 3404 MappedOps[NumElts+1] = *(N0.Val->op_end()-1); 3405 UDVal = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 3406 &MappedOps[0], MappedOps.size()); 3407 3408 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, 3409 N0, UDVal, ShufMask, 3410 MappedOps[NumElts], MappedOps[NumElts+1]); 3411 } 3412 3413 return SDOperand(); 3414} 3415 3416/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 3417/// a VAND to a vector_shuffle with the destination vector and a zero vector. 3418/// e.g. VAND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 3419/// vector_shuffle V, Zero, <0, 4, 2, 4> 3420SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) { 3421 SDOperand LHS = N->getOperand(0); 3422 SDOperand RHS = N->getOperand(1); 3423 if (N->getOpcode() == ISD::VAND) { 3424 SDOperand DstVecSize = *(LHS.Val->op_end()-2); 3425 SDOperand DstVecEVT = *(LHS.Val->op_end()-1); 3426 if (RHS.getOpcode() == ISD::VBIT_CONVERT) 3427 RHS = RHS.getOperand(0); 3428 if (RHS.getOpcode() == ISD::VBUILD_VECTOR) { 3429 std::vector<SDOperand> IdxOps; 3430 unsigned NumOps = RHS.getNumOperands(); 3431 unsigned NumElts = NumOps-2; 3432 MVT::ValueType EVT = cast<VTSDNode>(RHS.getOperand(NumOps-1))->getVT(); 3433 for (unsigned i = 0; i != NumElts; ++i) { 3434 SDOperand Elt = RHS.getOperand(i); 3435 if (!isa<ConstantSDNode>(Elt)) 3436 return SDOperand(); 3437 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 3438 IdxOps.push_back(DAG.getConstant(i, EVT)); 3439 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 3440 IdxOps.push_back(DAG.getConstant(NumElts, EVT)); 3441 else 3442 return SDOperand(); 3443 } 3444 3445 // Let's see if the target supports this vector_shuffle. 3446 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG)) 3447 return SDOperand(); 3448 3449 // Return the new VVECTOR_SHUFFLE node. 3450 SDOperand NumEltsNode = DAG.getConstant(NumElts, MVT::i32); 3451 SDOperand EVTNode = DAG.getValueType(EVT); 3452 std::vector<SDOperand> Ops; 3453 LHS = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, LHS, NumEltsNode, 3454 EVTNode); 3455 Ops.push_back(LHS); 3456 AddToWorkList(LHS.Val); 3457 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 3458 ZeroOps.push_back(NumEltsNode); 3459 ZeroOps.push_back(EVTNode); 3460 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 3461 &ZeroOps[0], ZeroOps.size())); 3462 IdxOps.push_back(NumEltsNode); 3463 IdxOps.push_back(EVTNode); 3464 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 3465 &IdxOps[0], IdxOps.size())); 3466 Ops.push_back(NumEltsNode); 3467 Ops.push_back(EVTNode); 3468 SDOperand Result = DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, 3469 &Ops[0], Ops.size()); 3470 if (NumEltsNode != DstVecSize || EVTNode != DstVecEVT) { 3471 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result, 3472 DstVecSize, DstVecEVT); 3473 } 3474 return Result; 3475 } 3476 } 3477 return SDOperand(); 3478} 3479 3480/// visitVBinOp - Visit a binary vector operation, like VADD. IntOp indicates 3481/// the scalar operation of the vop if it is operating on an integer vector 3482/// (e.g. ADD) and FPOp indicates the FP version (e.g. FADD). 3483SDOperand DAGCombiner::visitVBinOp(SDNode *N, ISD::NodeType IntOp, 3484 ISD::NodeType FPOp) { 3485 MVT::ValueType EltType = cast<VTSDNode>(*(N->op_end()-1))->getVT(); 3486 ISD::NodeType ScalarOp = MVT::isInteger(EltType) ? IntOp : FPOp; 3487 SDOperand LHS = N->getOperand(0); 3488 SDOperand RHS = N->getOperand(1); 3489 SDOperand Shuffle = XformToShuffleWithZero(N); 3490 if (Shuffle.Val) return Shuffle; 3491 3492 // If the LHS and RHS are VBUILD_VECTOR nodes, see if we can constant fold 3493 // this operation. 3494 if (LHS.getOpcode() == ISD::VBUILD_VECTOR && 3495 RHS.getOpcode() == ISD::VBUILD_VECTOR) { 3496 SmallVector<SDOperand, 8> Ops; 3497 for (unsigned i = 0, e = LHS.getNumOperands()-2; i != e; ++i) { 3498 SDOperand LHSOp = LHS.getOperand(i); 3499 SDOperand RHSOp = RHS.getOperand(i); 3500 // If these two elements can't be folded, bail out. 3501 if ((LHSOp.getOpcode() != ISD::UNDEF && 3502 LHSOp.getOpcode() != ISD::Constant && 3503 LHSOp.getOpcode() != ISD::ConstantFP) || 3504 (RHSOp.getOpcode() != ISD::UNDEF && 3505 RHSOp.getOpcode() != ISD::Constant && 3506 RHSOp.getOpcode() != ISD::ConstantFP)) 3507 break; 3508 // Can't fold divide by zero. 3509 if (N->getOpcode() == ISD::VSDIV || N->getOpcode() == ISD::VUDIV) { 3510 if ((RHSOp.getOpcode() == ISD::Constant && 3511 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) || 3512 (RHSOp.getOpcode() == ISD::ConstantFP && 3513 !cast<ConstantFPSDNode>(RHSOp.Val)->getValue())) 3514 break; 3515 } 3516 Ops.push_back(DAG.getNode(ScalarOp, EltType, LHSOp, RHSOp)); 3517 AddToWorkList(Ops.back().Val); 3518 assert((Ops.back().getOpcode() == ISD::UNDEF || 3519 Ops.back().getOpcode() == ISD::Constant || 3520 Ops.back().getOpcode() == ISD::ConstantFP) && 3521 "Scalar binop didn't fold!"); 3522 } 3523 3524 if (Ops.size() == LHS.getNumOperands()-2) { 3525 Ops.push_back(*(LHS.Val->op_end()-2)); 3526 Ops.push_back(*(LHS.Val->op_end()-1)); 3527 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 3528 } 3529 } 3530 3531 return SDOperand(); 3532} 3533 3534SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 3535 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 3536 3537 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 3538 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3539 // If we got a simplified select_cc node back from SimplifySelectCC, then 3540 // break it down into a new SETCC node, and a new SELECT node, and then return 3541 // the SELECT node, since we were called with a SELECT node. 3542 if (SCC.Val) { 3543 // Check to see if we got a select_cc back (to turn into setcc/select). 3544 // Otherwise, just return whatever node we got back, like fabs. 3545 if (SCC.getOpcode() == ISD::SELECT_CC) { 3546 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 3547 SCC.getOperand(0), SCC.getOperand(1), 3548 SCC.getOperand(4)); 3549 AddToWorkList(SETCC.Val); 3550 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 3551 SCC.getOperand(3), SETCC); 3552 } 3553 return SCC; 3554 } 3555 return SDOperand(); 3556} 3557 3558/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 3559/// are the two values being selected between, see if we can simplify the 3560/// select. Callers of this should assume that TheSelect is deleted if this 3561/// returns true. As such, they should return the appropriate thing (e.g. the 3562/// node) back to the top-level of the DAG combiner loop to avoid it being 3563/// looked at. 3564/// 3565bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS, 3566 SDOperand RHS) { 3567 3568 // If this is a select from two identical things, try to pull the operation 3569 // through the select. 3570 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 3571 // If this is a load and the token chain is identical, replace the select 3572 // of two loads with a load through a select of the address to load from. 3573 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 3574 // constants have been dropped into the constant pool. 3575 if (LHS.getOpcode() == ISD::LOAD && 3576 // Token chains must be identical. 3577 LHS.getOperand(0) == RHS.getOperand(0)) { 3578 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 3579 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 3580 3581 // If this is an EXTLOAD, the VT's must match. 3582 if (LLD->getLoadedVT() == RLD->getLoadedVT()) { 3583 // FIXME: this conflates two src values, discarding one. This is not 3584 // the right thing to do, but nothing uses srcvalues now. When they do, 3585 // turn SrcValue into a list of locations. 3586 SDOperand Addr; 3587 if (TheSelect->getOpcode() == ISD::SELECT) 3588 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(), 3589 TheSelect->getOperand(0), LLD->getBasePtr(), 3590 RLD->getBasePtr()); 3591 else 3592 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(), 3593 TheSelect->getOperand(0), 3594 TheSelect->getOperand(1), 3595 LLD->getBasePtr(), RLD->getBasePtr(), 3596 TheSelect->getOperand(4)); 3597 3598 SDOperand Load; 3599 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) 3600 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(), 3601 Addr,LLD->getSrcValue(), LLD->getSrcValueOffset()); 3602 else { 3603 Load = DAG.getExtLoad(LLD->getExtensionType(), 3604 TheSelect->getValueType(0), 3605 LLD->getChain(), Addr, LLD->getSrcValue(), 3606 LLD->getSrcValueOffset(), 3607 LLD->getLoadedVT()); 3608 } 3609 // Users of the select now use the result of the load. 3610 CombineTo(TheSelect, Load); 3611 3612 // Users of the old loads now use the new load's chain. We know the 3613 // old-load value is dead now. 3614 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); 3615 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); 3616 return true; 3617 } 3618 } 3619 } 3620 3621 return false; 3622} 3623 3624SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 3625 SDOperand N2, SDOperand N3, 3626 ISD::CondCode CC) { 3627 3628 MVT::ValueType VT = N2.getValueType(); 3629 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 3630 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 3631 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 3632 3633 // Determine if the condition we're dealing with is constant 3634 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 3635 if (SCC.Val) AddToWorkList(SCC.Val); 3636 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 3637 3638 // fold select_cc true, x, y -> x 3639 if (SCCC && SCCC->getValue()) 3640 return N2; 3641 // fold select_cc false, x, y -> y 3642 if (SCCC && SCCC->getValue() == 0) 3643 return N3; 3644 3645 // Check to see if we can simplify the select into an fabs node 3646 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 3647 // Allow either -0.0 or 0.0 3648 if (CFP->getValue() == 0.0) { 3649 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 3650 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 3651 N0 == N2 && N3.getOpcode() == ISD::FNEG && 3652 N2 == N3.getOperand(0)) 3653 return DAG.getNode(ISD::FABS, VT, N0); 3654 3655 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 3656 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 3657 N0 == N3 && N2.getOpcode() == ISD::FNEG && 3658 N2.getOperand(0) == N3) 3659 return DAG.getNode(ISD::FABS, VT, N3); 3660 } 3661 } 3662 3663 // Check to see if we can perform the "gzip trick", transforming 3664 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 3665 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 3666 MVT::isInteger(N0.getValueType()) && 3667 MVT::isInteger(N2.getValueType()) && 3668 (N1C->isNullValue() || // (a < 0) ? b : 0 3669 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 3670 MVT::ValueType XType = N0.getValueType(); 3671 MVT::ValueType AType = N2.getValueType(); 3672 if (XType >= AType) { 3673 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 3674 // single-bit constant. 3675 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) { 3676 unsigned ShCtV = Log2_64(N2C->getValue()); 3677 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 3678 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 3679 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 3680 AddToWorkList(Shift.Val); 3681 if (XType > AType) { 3682 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 3683 AddToWorkList(Shift.Val); 3684 } 3685 return DAG.getNode(ISD::AND, AType, Shift, N2); 3686 } 3687 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 3688 DAG.getConstant(MVT::getSizeInBits(XType)-1, 3689 TLI.getShiftAmountTy())); 3690 AddToWorkList(Shift.Val); 3691 if (XType > AType) { 3692 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 3693 AddToWorkList(Shift.Val); 3694 } 3695 return DAG.getNode(ISD::AND, AType, Shift, N2); 3696 } 3697 } 3698 3699 // fold select C, 16, 0 -> shl C, 4 3700 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) && 3701 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 3702 // Get a SetCC of the condition 3703 // FIXME: Should probably make sure that setcc is legal if we ever have a 3704 // target where it isn't. 3705 SDOperand Temp, SCC; 3706 // cast from setcc result type to select result type 3707 if (AfterLegalize) { 3708 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 3709 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 3710 } else { 3711 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 3712 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 3713 } 3714 AddToWorkList(SCC.Val); 3715 AddToWorkList(Temp.Val); 3716 // shl setcc result by log2 n2c 3717 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 3718 DAG.getConstant(Log2_64(N2C->getValue()), 3719 TLI.getShiftAmountTy())); 3720 } 3721 3722 // Check to see if this is the equivalent of setcc 3723 // FIXME: Turn all of these into setcc if setcc if setcc is legal 3724 // otherwise, go ahead with the folds. 3725 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) { 3726 MVT::ValueType XType = N0.getValueType(); 3727 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) { 3728 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 3729 if (Res.getValueType() != VT) 3730 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 3731 return Res; 3732 } 3733 3734 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 3735 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 3736 TLI.isOperationLegal(ISD::CTLZ, XType)) { 3737 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 3738 return DAG.getNode(ISD::SRL, XType, Ctlz, 3739 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 3740 TLI.getShiftAmountTy())); 3741 } 3742 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 3743 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 3744 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 3745 N0); 3746 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 3747 DAG.getConstant(~0ULL, XType)); 3748 return DAG.getNode(ISD::SRL, XType, 3749 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 3750 DAG.getConstant(MVT::getSizeInBits(XType)-1, 3751 TLI.getShiftAmountTy())); 3752 } 3753 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 3754 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 3755 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 3756 DAG.getConstant(MVT::getSizeInBits(XType)-1, 3757 TLI.getShiftAmountTy())); 3758 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 3759 } 3760 } 3761 3762 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 3763 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 3764 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 3765 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) { 3766 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) { 3767 MVT::ValueType XType = N0.getValueType(); 3768 if (SubC->isNullValue() && MVT::isInteger(XType)) { 3769 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 3770 DAG.getConstant(MVT::getSizeInBits(XType)-1, 3771 TLI.getShiftAmountTy())); 3772 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 3773 AddToWorkList(Shift.Val); 3774 AddToWorkList(Add.Val); 3775 return DAG.getNode(ISD::XOR, XType, Add, Shift); 3776 } 3777 } 3778 } 3779 3780 return SDOperand(); 3781} 3782 3783SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 3784 SDOperand N1, ISD::CondCode Cond, 3785 bool foldBooleans) { 3786 // These setcc operations always fold. 3787 switch (Cond) { 3788 default: break; 3789 case ISD::SETFALSE: 3790 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 3791 case ISD::SETTRUE: 3792 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 3793 } 3794 3795 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { 3796 uint64_t C1 = N1C->getValue(); 3797 if (isa<ConstantSDNode>(N0.Val)) { 3798 return DAG.FoldSetCC(VT, N0, N1, Cond); 3799 } else { 3800 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 3801 // equality comparison, then we're just comparing whether X itself is 3802 // zero. 3803 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 3804 N0.getOperand(0).getOpcode() == ISD::CTLZ && 3805 N0.getOperand(1).getOpcode() == ISD::Constant) { 3806 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 3807 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 3808 ShAmt == Log2_32(MVT::getSizeInBits(N0.getValueType()))) { 3809 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 3810 // (srl (ctlz x), 5) == 0 -> X != 0 3811 // (srl (ctlz x), 5) != 1 -> X != 0 3812 Cond = ISD::SETNE; 3813 } else { 3814 // (srl (ctlz x), 5) != 0 -> X == 0 3815 // (srl (ctlz x), 5) == 1 -> X == 0 3816 Cond = ISD::SETEQ; 3817 } 3818 SDOperand Zero = DAG.getConstant(0, N0.getValueType()); 3819 return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0), 3820 Zero, Cond); 3821 } 3822 } 3823 3824 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 3825 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 3826 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType()); 3827 3828 // If the comparison constant has bits in the upper part, the 3829 // zero-extended value could never match. 3830 if (C1 & (~0ULL << InSize)) { 3831 unsigned VSize = MVT::getSizeInBits(N0.getValueType()); 3832 switch (Cond) { 3833 case ISD::SETUGT: 3834 case ISD::SETUGE: 3835 case ISD::SETEQ: return DAG.getConstant(0, VT); 3836 case ISD::SETULT: 3837 case ISD::SETULE: 3838 case ISD::SETNE: return DAG.getConstant(1, VT); 3839 case ISD::SETGT: 3840 case ISD::SETGE: 3841 // True if the sign bit of C1 is set. 3842 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT); 3843 case ISD::SETLT: 3844 case ISD::SETLE: 3845 // True if the sign bit of C1 isn't set. 3846 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT); 3847 default: 3848 break; 3849 } 3850 } 3851 3852 // Otherwise, we can perform the comparison with the low bits. 3853 switch (Cond) { 3854 case ISD::SETEQ: 3855 case ISD::SETNE: 3856 case ISD::SETUGT: 3857 case ISD::SETUGE: 3858 case ISD::SETULT: 3859 case ISD::SETULE: 3860 return DAG.getSetCC(VT, N0.getOperand(0), 3861 DAG.getConstant(C1, N0.getOperand(0).getValueType()), 3862 Cond); 3863 default: 3864 break; // todo, be more careful with signed comparisons 3865 } 3866 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3867 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 3868 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 3869 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy); 3870 MVT::ValueType ExtDstTy = N0.getValueType(); 3871 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy); 3872 3873 // If the extended part has any inconsistent bits, it cannot ever 3874 // compare equal. In other words, they have to be all ones or all 3875 // zeros. 3876 uint64_t ExtBits = 3877 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1)); 3878 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 3879 return DAG.getConstant(Cond == ISD::SETNE, VT); 3880 3881 SDOperand ZextOp; 3882 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType(); 3883 if (Op0Ty == ExtSrcTy) { 3884 ZextOp = N0.getOperand(0); 3885 } else { 3886 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits); 3887 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0), 3888 DAG.getConstant(Imm, Op0Ty)); 3889 } 3890 AddToWorkList(ZextOp.Val); 3891 // Otherwise, make this a use of a zext. 3892 return DAG.getSetCC(VT, ZextOp, 3893 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)), 3894 ExtDstTy), 3895 Cond); 3896 } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) && 3897 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 3898 3899 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 3900 if (N0.getOpcode() == ISD::SETCC) { 3901 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getValue() != 1); 3902 if (TrueWhenTrue) 3903 return N0; 3904 3905 // Invert the condition. 3906 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 3907 CC = ISD::getSetCCInverse(CC, 3908 MVT::isInteger(N0.getOperand(0).getValueType())); 3909 return DAG.getSetCC(VT, N0.getOperand(0), N0.getOperand(1), CC); 3910 } 3911 3912 if ((N0.getOpcode() == ISD::XOR || 3913 (N0.getOpcode() == ISD::AND && 3914 N0.getOperand(0).getOpcode() == ISD::XOR && 3915 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 3916 isa<ConstantSDNode>(N0.getOperand(1)) && 3917 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) { 3918 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 3919 // can only do this if the top bits are known zero. 3920 if (TLI.MaskedValueIsZero(N0, 3921 MVT::getIntVTBitMask(N0.getValueType())-1)){ 3922 // Okay, get the un-inverted input value. 3923 SDOperand Val; 3924 if (N0.getOpcode() == ISD::XOR) 3925 Val = N0.getOperand(0); 3926 else { 3927 assert(N0.getOpcode() == ISD::AND && 3928 N0.getOperand(0).getOpcode() == ISD::XOR); 3929 // ((X^1)&1)^1 -> X & 1 3930 Val = DAG.getNode(ISD::AND, N0.getValueType(), 3931 N0.getOperand(0).getOperand(0), 3932 N0.getOperand(1)); 3933 } 3934 return DAG.getSetCC(VT, Val, N1, 3935 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 3936 } 3937 } 3938 } 3939 3940 uint64_t MinVal, MaxVal; 3941 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0)); 3942 if (ISD::isSignedIntSetCC(Cond)) { 3943 MinVal = 1ULL << (OperandBitSize-1); 3944 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined. 3945 MaxVal = ~0ULL >> (65-OperandBitSize); 3946 else 3947 MaxVal = 0; 3948 } else { 3949 MinVal = 0; 3950 MaxVal = ~0ULL >> (64-OperandBitSize); 3951 } 3952 3953 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 3954 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 3955 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 3956 --C1; // X >= C0 --> X > (C0-1) 3957 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 3958 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 3959 } 3960 3961 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 3962 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 3963 ++C1; // X <= C0 --> X < (C0+1) 3964 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 3965 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 3966 } 3967 3968 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 3969 return DAG.getConstant(0, VT); // X < MIN --> false 3970 3971 // Canonicalize setgt X, Min --> setne X, Min 3972 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 3973 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 3974 // Canonicalize setlt X, Max --> setne X, Max 3975 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 3976 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 3977 3978 // If we have setult X, 1, turn it into seteq X, 0 3979 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 3980 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()), 3981 ISD::SETEQ); 3982 // If we have setugt X, Max-1, turn it into seteq X, Max 3983 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 3984 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()), 3985 ISD::SETEQ); 3986 3987 // If we have "setcc X, C0", check to see if we can shrink the immediate 3988 // by changing cc. 3989 3990 // SETUGT X, SINTMAX -> SETLT X, 0 3991 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 3992 C1 == (~0ULL >> (65-OperandBitSize))) 3993 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()), 3994 ISD::SETLT); 3995 3996 // FIXME: Implement the rest of these. 3997 3998 // Fold bit comparisons when we can. 3999 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 4000 VT == N0.getValueType() && N0.getOpcode() == ISD::AND) 4001 if (ConstantSDNode *AndRHS = 4002 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 4003 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 4004 // Perform the xform if the AND RHS is a single bit. 4005 if (isPowerOf2_64(AndRHS->getValue())) { 4006 return DAG.getNode(ISD::SRL, VT, N0, 4007 DAG.getConstant(Log2_64(AndRHS->getValue()), 4008 TLI.getShiftAmountTy())); 4009 } 4010 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) { 4011 // (X & 8) == 8 --> (X & 8) >> 3 4012 // Perform the xform if C1 is a single bit. 4013 if (isPowerOf2_64(C1)) { 4014 return DAG.getNode(ISD::SRL, VT, N0, 4015 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy())); 4016 } 4017 } 4018 } 4019 } 4020 } else if (isa<ConstantSDNode>(N0.Val)) { 4021 // Ensure that the constant occurs on the RHS. 4022 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 4023 } 4024 4025 if (isa<ConstantFPSDNode>(N0.Val)) { 4026 // Constant fold or commute setcc. 4027 SDOperand O = DAG.FoldSetCC(VT, N0, N1, Cond); 4028 if (O.Val) return O; 4029 } 4030 4031 if (N0 == N1) { 4032 // We can always fold X == X for integer setcc's. 4033 if (MVT::isInteger(N0.getValueType())) 4034 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 4035 unsigned UOF = ISD::getUnorderedFlavor(Cond); 4036 if (UOF == 2) // FP operators that are undefined on NaNs. 4037 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 4038 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 4039 return DAG.getConstant(UOF, VT); 4040 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 4041 // if it is not already. 4042 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 4043 if (NewCond != Cond) 4044 return DAG.getSetCC(VT, N0, N1, NewCond); 4045 } 4046 4047 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 4048 MVT::isInteger(N0.getValueType())) { 4049 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 4050 N0.getOpcode() == ISD::XOR) { 4051 // Simplify (X+Y) == (X+Z) --> Y == Z 4052 if (N0.getOpcode() == N1.getOpcode()) { 4053 if (N0.getOperand(0) == N1.getOperand(0)) 4054 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond); 4055 if (N0.getOperand(1) == N1.getOperand(1)) 4056 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond); 4057 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 4058 // If X op Y == Y op X, try other combinations. 4059 if (N0.getOperand(0) == N1.getOperand(1)) 4060 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond); 4061 if (N0.getOperand(1) == N1.getOperand(0)) 4062 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond); 4063 } 4064 } 4065 4066 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 4067 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 4068 // Turn (X+C1) == C2 --> X == C2-C1 4069 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) { 4070 return DAG.getSetCC(VT, N0.getOperand(0), 4071 DAG.getConstant(RHSC->getValue()-LHSR->getValue(), 4072 N0.getValueType()), Cond); 4073 } 4074 4075 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 4076 if (N0.getOpcode() == ISD::XOR) 4077 // If we know that all of the inverted bits are zero, don't bother 4078 // performing the inversion. 4079 if (TLI.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue())) 4080 return DAG.getSetCC(VT, N0.getOperand(0), 4081 DAG.getConstant(LHSR->getValue()^RHSC->getValue(), 4082 N0.getValueType()), Cond); 4083 } 4084 4085 // Turn (C1-X) == C2 --> X == C1-C2 4086 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 4087 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) { 4088 return DAG.getSetCC(VT, N0.getOperand(1), 4089 DAG.getConstant(SUBC->getValue()-RHSC->getValue(), 4090 N0.getValueType()), Cond); 4091 } 4092 } 4093 } 4094 4095 // Simplify (X+Z) == X --> Z == 0 4096 if (N0.getOperand(0) == N1) 4097 return DAG.getSetCC(VT, N0.getOperand(1), 4098 DAG.getConstant(0, N0.getValueType()), Cond); 4099 if (N0.getOperand(1) == N1) { 4100 if (DAG.isCommutativeBinOp(N0.getOpcode())) 4101 return DAG.getSetCC(VT, N0.getOperand(0), 4102 DAG.getConstant(0, N0.getValueType()), Cond); 4103 else { 4104 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 4105 // (Z-X) == X --> Z == X<<1 4106 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), 4107 N1, 4108 DAG.getConstant(1,TLI.getShiftAmountTy())); 4109 AddToWorkList(SH.Val); 4110 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond); 4111 } 4112 } 4113 } 4114 4115 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 4116 N1.getOpcode() == ISD::XOR) { 4117 // Simplify X == (X+Z) --> Z == 0 4118 if (N1.getOperand(0) == N0) { 4119 return DAG.getSetCC(VT, N1.getOperand(1), 4120 DAG.getConstant(0, N1.getValueType()), Cond); 4121 } else if (N1.getOperand(1) == N0) { 4122 if (DAG.isCommutativeBinOp(N1.getOpcode())) { 4123 return DAG.getSetCC(VT, N1.getOperand(0), 4124 DAG.getConstant(0, N1.getValueType()), Cond); 4125 } else { 4126 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 4127 // X == (Z-X) --> X<<1 == Z 4128 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0, 4129 DAG.getConstant(1,TLI.getShiftAmountTy())); 4130 AddToWorkList(SH.Val); 4131 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond); 4132 } 4133 } 4134 } 4135 } 4136 4137 // Fold away ALL boolean setcc's. 4138 SDOperand Temp; 4139 if (N0.getValueType() == MVT::i1 && foldBooleans) { 4140 switch (Cond) { 4141 default: assert(0 && "Unknown integer setcc!"); 4142 case ISD::SETEQ: // X == Y -> (X^Y)^1 4143 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 4144 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1)); 4145 AddToWorkList(Temp.Val); 4146 break; 4147 case ISD::SETNE: // X != Y --> (X^Y) 4148 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 4149 break; 4150 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 4151 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 4152 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 4153 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp); 4154 AddToWorkList(Temp.Val); 4155 break; 4156 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 4157 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 4158 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 4159 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp); 4160 AddToWorkList(Temp.Val); 4161 break; 4162 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 4163 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 4164 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 4165 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp); 4166 AddToWorkList(Temp.Val); 4167 break; 4168 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 4169 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 4170 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 4171 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp); 4172 break; 4173 } 4174 if (VT != MVT::i1) { 4175 AddToWorkList(N0.Val); 4176 // FIXME: If running after legalize, we probably can't do this. 4177 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 4178 } 4179 return N0; 4180 } 4181 4182 // Could not fold it. 4183 return SDOperand(); 4184} 4185 4186/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 4187/// return a DAG expression to select that will generate the same value by 4188/// multiplying by a magic number. See: 4189/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 4190SDOperand DAGCombiner::BuildSDIV(SDNode *N) { 4191 std::vector<SDNode*> Built; 4192 SDOperand S = TLI.BuildSDIV(N, DAG, &Built); 4193 4194 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 4195 ii != ee; ++ii) 4196 AddToWorkList(*ii); 4197 return S; 4198} 4199 4200/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 4201/// return a DAG expression to select that will generate the same value by 4202/// multiplying by a magic number. See: 4203/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 4204SDOperand DAGCombiner::BuildUDIV(SDNode *N) { 4205 std::vector<SDNode*> Built; 4206 SDOperand S = TLI.BuildUDIV(N, DAG, &Built); 4207 4208 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 4209 ii != ee; ++ii) 4210 AddToWorkList(*ii); 4211 return S; 4212} 4213 4214/// FindBaseOffset - Return true if base is known not to alias with anything 4215/// but itself. Provides base object and offset as results. 4216static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) { 4217 // Assume it is a primitive operation. 4218 Base = Ptr; Offset = 0; 4219 4220 // If it's an adding a simple constant then integrate the offset. 4221 if (Base.getOpcode() == ISD::ADD) { 4222 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 4223 Base = Base.getOperand(0); 4224 Offset += C->getValue(); 4225 } 4226 } 4227 4228 // If it's any of the following then it can't alias with anything but itself. 4229 return isa<FrameIndexSDNode>(Base) || 4230 isa<ConstantPoolSDNode>(Base) || 4231 isa<GlobalAddressSDNode>(Base); 4232} 4233 4234/// isAlias - Return true if there is any possibility that the two addresses 4235/// overlap. 4236bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1, 4237 const Value *SrcValue1, int SrcValueOffset1, 4238 SDOperand Ptr2, int64_t Size2, 4239 const Value *SrcValue2, int SrcValueOffset2) 4240{ 4241 // If they are the same then they must be aliases. 4242 if (Ptr1 == Ptr2) return true; 4243 4244 // Gather base node and offset information. 4245 SDOperand Base1, Base2; 4246 int64_t Offset1, Offset2; 4247 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 4248 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 4249 4250 // If they have a same base address then... 4251 if (Base1 == Base2) { 4252 // Check to see if the addresses overlap. 4253 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 4254 } 4255 4256 // If we know both bases then they can't alias. 4257 if (KnownBase1 && KnownBase2) return false; 4258 4259 if (CombinerGlobalAA) { 4260 // Use alias analysis information. 4261 int Overlap1 = Size1 + SrcValueOffset1 + Offset1; 4262 int Overlap2 = Size2 + SrcValueOffset2 + Offset2; 4263 AliasAnalysis::AliasResult AAResult = 4264 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 4265 if (AAResult == AliasAnalysis::NoAlias) 4266 return false; 4267 } 4268 4269 // Otherwise we have to assume they alias. 4270 return true; 4271} 4272 4273/// FindAliasInfo - Extracts the relevant alias information from the memory 4274/// node. Returns true if the operand was a load. 4275bool DAGCombiner::FindAliasInfo(SDNode *N, 4276 SDOperand &Ptr, int64_t &Size, 4277 const Value *&SrcValue, int &SrcValueOffset) { 4278 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4279 Ptr = LD->getBasePtr(); 4280 Size = MVT::getSizeInBits(LD->getLoadedVT()) >> 3; 4281 SrcValue = LD->getSrcValue(); 4282 SrcValueOffset = LD->getSrcValueOffset(); 4283 return true; 4284 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4285 Ptr = ST->getBasePtr(); 4286 Size = MVT::getSizeInBits(ST->getStoredVT()) >> 3; 4287 SrcValue = ST->getSrcValue(); 4288 SrcValueOffset = ST->getSrcValueOffset(); 4289 } else { 4290 assert(0 && "FindAliasInfo expected a memory operand"); 4291 } 4292 4293 return false; 4294} 4295 4296/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 4297/// looking for aliasing nodes and adding them to the Aliases vector. 4298void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain, 4299 SmallVector<SDOperand, 8> &Aliases) { 4300 SmallVector<SDOperand, 8> Chains; // List of chains to visit. 4301 std::set<SDNode *> Visited; // Visited node set. 4302 4303 // Get alias information for node. 4304 SDOperand Ptr; 4305 int64_t Size; 4306 const Value *SrcValue; 4307 int SrcValueOffset; 4308 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 4309 4310 // Starting off. 4311 Chains.push_back(OriginalChain); 4312 4313 // Look at each chain and determine if it is an alias. If so, add it to the 4314 // aliases list. If not, then continue up the chain looking for the next 4315 // candidate. 4316 while (!Chains.empty()) { 4317 SDOperand Chain = Chains.back(); 4318 Chains.pop_back(); 4319 4320 // Don't bother if we've been before. 4321 if (Visited.find(Chain.Val) != Visited.end()) continue; 4322 Visited.insert(Chain.Val); 4323 4324 switch (Chain.getOpcode()) { 4325 case ISD::EntryToken: 4326 // Entry token is ideal chain operand, but handled in FindBetterChain. 4327 break; 4328 4329 case ISD::LOAD: 4330 case ISD::STORE: { 4331 // Get alias information for Chain. 4332 SDOperand OpPtr; 4333 int64_t OpSize; 4334 const Value *OpSrcValue; 4335 int OpSrcValueOffset; 4336 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize, 4337 OpSrcValue, OpSrcValueOffset); 4338 4339 // If chain is alias then stop here. 4340 if (!(IsLoad && IsOpLoad) && 4341 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 4342 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 4343 Aliases.push_back(Chain); 4344 } else { 4345 // Look further up the chain. 4346 Chains.push_back(Chain.getOperand(0)); 4347 // Clean up old chain. 4348 AddToWorkList(Chain.Val); 4349 } 4350 break; 4351 } 4352 4353 case ISD::TokenFactor: 4354 // We have to check each of the operands of the token factor, so we queue 4355 // then up. Adding the operands to the queue (stack) in reverse order 4356 // maintains the original order and increases the likelihood that getNode 4357 // will find a matching token factor (CSE.) 4358 for (unsigned n = Chain.getNumOperands(); n;) 4359 Chains.push_back(Chain.getOperand(--n)); 4360 // Eliminate the token factor if we can. 4361 AddToWorkList(Chain.Val); 4362 break; 4363 4364 default: 4365 // For all other instructions we will just have to take what we can get. 4366 Aliases.push_back(Chain); 4367 break; 4368 } 4369 } 4370} 4371 4372/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 4373/// for a better chain (aliasing node.) 4374SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) { 4375 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor. 4376 4377 // Accumulate all the aliases to this node. 4378 GatherAllAliases(N, OldChain, Aliases); 4379 4380 if (Aliases.size() == 0) { 4381 // If no operands then chain to entry token. 4382 return DAG.getEntryNode(); 4383 } else if (Aliases.size() == 1) { 4384 // If a single operand then chain to it. We don't need to revisit it. 4385 return Aliases[0]; 4386 } 4387 4388 // Construct a custom tailored token factor. 4389 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 4390 &Aliases[0], Aliases.size()); 4391 4392 // Make sure the old chain gets cleaned up. 4393 if (NewChain != OldChain) AddToWorkList(OldChain.Val); 4394 4395 return NewChain; 4396} 4397 4398// SelectionDAG::Combine - This is the entry point for the file. 4399// 4400void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) { 4401 /// run - This is the main entry point to this class. 4402 /// 4403 DAGCombiner(*this, AA).Run(RunningAfterLegalize); 4404} 4405