DAGCombiner.cpp revision 0b68b758bbb6718fc67423109eeb9df64c711a37
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/ADT/SmallPtrSet.h" 22#include "llvm/ADT/Statistic.h" 23#include "llvm/Analysis/AliasAnalysis.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineFunction.h" 26#include "llvm/IR/DataLayout.h" 27#include "llvm/IR/DerivedTypes.h" 28#include "llvm/IR/Function.h" 29#include "llvm/IR/LLVMContext.h" 30#include "llvm/Support/CommandLine.h" 31#include "llvm/Support/Debug.h" 32#include "llvm/Support/ErrorHandling.h" 33#include "llvm/Support/MathExtras.h" 34#include "llvm/Support/raw_ostream.h" 35#include "llvm/Target/TargetLowering.h" 36#include "llvm/Target/TargetMachine.h" 37#include "llvm/Target/TargetOptions.h" 38#include <algorithm> 39using namespace llvm; 40 41STATISTIC(NodesCombined , "Number of dag nodes combined"); 42STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 43STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 44STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 45STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int"); 46 47namespace { 48 static cl::opt<bool> 49 CombinerAA("combiner-alias-analysis", cl::Hidden, 50 cl::desc("Turn on alias analysis during testing")); 51 52 static cl::opt<bool> 53 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 54 cl::desc("Include global information in alias analysis")); 55 56//------------------------------ DAGCombiner ---------------------------------// 57 58 class DAGCombiner { 59 SelectionDAG &DAG; 60 const TargetLowering &TLI; 61 CombineLevel Level; 62 CodeGenOpt::Level OptLevel; 63 bool LegalOperations; 64 bool LegalTypes; 65 66 // Worklist of all of the nodes that need to be simplified. 67 // 68 // This has the semantics that when adding to the worklist, 69 // the item added must be next to be processed. It should 70 // also only appear once. The naive approach to this takes 71 // linear time. 72 // 73 // To reduce the insert/remove time to logarithmic, we use 74 // a set and a vector to maintain our worklist. 75 // 76 // The set contains the items on the worklist, but does not 77 // maintain the order they should be visited. 78 // 79 // The vector maintains the order nodes should be visited, but may 80 // contain duplicate or removed nodes. When choosing a node to 81 // visit, we pop off the order stack until we find an item that is 82 // also in the contents set. All operations are O(log N). 83 SmallPtrSet<SDNode*, 64> WorkListContents; 84 SmallVector<SDNode*, 64> WorkListOrder; 85 86 // AA - Used for DAG load/store alias analysis. 87 AliasAnalysis &AA; 88 89 /// AddUsersToWorkList - When an instruction is simplified, add all users of 90 /// the instruction to the work lists because they might get more simplified 91 /// now. 92 /// 93 void AddUsersToWorkList(SDNode *N) { 94 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 95 UI != UE; ++UI) 96 AddToWorkList(*UI); 97 } 98 99 /// visit - call the node-specific routine that knows how to fold each 100 /// particular type of node. 101 SDValue visit(SDNode *N); 102 103 public: 104 /// AddToWorkList - Add to the work list making sure its instance is at the 105 /// back (next to be processed.) 106 void AddToWorkList(SDNode *N) { 107 WorkListContents.insert(N); 108 WorkListOrder.push_back(N); 109 } 110 111 /// removeFromWorkList - remove all instances of N from the worklist. 112 /// 113 void removeFromWorkList(SDNode *N) { 114 WorkListContents.erase(N); 115 } 116 117 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 118 bool AddTo = true); 119 120 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 121 return CombineTo(N, &Res, 1, AddTo); 122 } 123 124 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 125 bool AddTo = true) { 126 SDValue To[] = { Res0, Res1 }; 127 return CombineTo(N, To, 2, AddTo); 128 } 129 130 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 131 132 private: 133 134 /// SimplifyDemandedBits - Check the specified integer node value to see if 135 /// it can be simplified or if things it uses can be simplified by bit 136 /// propagation. If so, return true. 137 bool SimplifyDemandedBits(SDValue Op) { 138 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); 139 APInt Demanded = APInt::getAllOnesValue(BitWidth); 140 return SimplifyDemandedBits(Op, Demanded); 141 } 142 143 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 144 145 bool CombineToPreIndexedLoadStore(SDNode *N); 146 bool CombineToPostIndexedLoadStore(SDNode *N); 147 148 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad); 149 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace); 150 SDValue SExtPromoteOperand(SDValue Op, EVT PVT); 151 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT); 152 SDValue PromoteIntBinOp(SDValue Op); 153 SDValue PromoteIntShiftOp(SDValue Op); 154 SDValue PromoteExtend(SDValue Op); 155 bool PromoteLoad(SDValue Op); 156 157 void ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs, 158 SDValue Trunc, SDValue ExtLoad, DebugLoc DL, 159 ISD::NodeType ExtType); 160 161 /// combine - call the node-specific routine that knows how to fold each 162 /// particular type of node. If that doesn't do anything, try the 163 /// target-specific DAG combines. 164 SDValue combine(SDNode *N); 165 166 // Visitation implementation - Implement dag node combining for different 167 // node types. The semantics are as follows: 168 // Return Value: 169 // SDValue.getNode() == 0 - No change was made 170 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 171 // otherwise - N should be replaced by the returned Operand. 172 // 173 SDValue visitTokenFactor(SDNode *N); 174 SDValue visitMERGE_VALUES(SDNode *N); 175 SDValue visitADD(SDNode *N); 176 SDValue visitSUB(SDNode *N); 177 SDValue visitADDC(SDNode *N); 178 SDValue visitSUBC(SDNode *N); 179 SDValue visitADDE(SDNode *N); 180 SDValue visitSUBE(SDNode *N); 181 SDValue visitMUL(SDNode *N); 182 SDValue visitSDIV(SDNode *N); 183 SDValue visitUDIV(SDNode *N); 184 SDValue visitSREM(SDNode *N); 185 SDValue visitUREM(SDNode *N); 186 SDValue visitMULHU(SDNode *N); 187 SDValue visitMULHS(SDNode *N); 188 SDValue visitSMUL_LOHI(SDNode *N); 189 SDValue visitUMUL_LOHI(SDNode *N); 190 SDValue visitSMULO(SDNode *N); 191 SDValue visitUMULO(SDNode *N); 192 SDValue visitSDIVREM(SDNode *N); 193 SDValue visitUDIVREM(SDNode *N); 194 SDValue visitAND(SDNode *N); 195 SDValue visitOR(SDNode *N); 196 SDValue visitXOR(SDNode *N); 197 SDValue SimplifyVBinOp(SDNode *N); 198 SDValue SimplifyVUnaryOp(SDNode *N); 199 SDValue visitSHL(SDNode *N); 200 SDValue visitSRA(SDNode *N); 201 SDValue visitSRL(SDNode *N); 202 SDValue visitCTLZ(SDNode *N); 203 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N); 204 SDValue visitCTTZ(SDNode *N); 205 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N); 206 SDValue visitCTPOP(SDNode *N); 207 SDValue visitSELECT(SDNode *N); 208 SDValue visitSELECT_CC(SDNode *N); 209 SDValue visitSETCC(SDNode *N); 210 SDValue visitSIGN_EXTEND(SDNode *N); 211 SDValue visitZERO_EXTEND(SDNode *N); 212 SDValue visitANY_EXTEND(SDNode *N); 213 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 214 SDValue visitTRUNCATE(SDNode *N); 215 SDValue visitBITCAST(SDNode *N); 216 SDValue visitBUILD_PAIR(SDNode *N); 217 SDValue visitFADD(SDNode *N); 218 SDValue visitFSUB(SDNode *N); 219 SDValue visitFMUL(SDNode *N); 220 SDValue visitFMA(SDNode *N); 221 SDValue visitFDIV(SDNode *N); 222 SDValue visitFREM(SDNode *N); 223 SDValue visitFCOPYSIGN(SDNode *N); 224 SDValue visitSINT_TO_FP(SDNode *N); 225 SDValue visitUINT_TO_FP(SDNode *N); 226 SDValue visitFP_TO_SINT(SDNode *N); 227 SDValue visitFP_TO_UINT(SDNode *N); 228 SDValue visitFP_ROUND(SDNode *N); 229 SDValue visitFP_ROUND_INREG(SDNode *N); 230 SDValue visitFP_EXTEND(SDNode *N); 231 SDValue visitFNEG(SDNode *N); 232 SDValue visitFABS(SDNode *N); 233 SDValue visitFCEIL(SDNode *N); 234 SDValue visitFTRUNC(SDNode *N); 235 SDValue visitFFLOOR(SDNode *N); 236 SDValue visitBRCOND(SDNode *N); 237 SDValue visitBR_CC(SDNode *N); 238 SDValue visitLOAD(SDNode *N); 239 SDValue visitSTORE(SDNode *N); 240 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 241 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 242 SDValue visitBUILD_VECTOR(SDNode *N); 243 SDValue visitCONCAT_VECTORS(SDNode *N); 244 SDValue visitEXTRACT_SUBVECTOR(SDNode *N); 245 SDValue visitVECTOR_SHUFFLE(SDNode *N); 246 SDValue visitMEMBARRIER(SDNode *N); 247 248 SDValue XformToShuffleWithZero(SDNode *N); 249 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 250 251 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 252 253 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 254 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 255 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 256 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 257 SDValue N3, ISD::CondCode CC, 258 bool NotExtCompare = false); 259 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 260 DebugLoc DL, bool foldBooleans = true); 261 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 262 unsigned HiOp); 263 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); 264 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT); 265 SDValue BuildSDIV(SDNode *N); 266 SDValue BuildUDIV(SDNode *N); 267 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, 268 bool DemandHighBits = true); 269 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1); 270 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 271 SDValue ReduceLoadWidth(SDNode *N); 272 SDValue ReduceLoadOpStoreWidth(SDNode *N); 273 SDValue TransformFPLoadStorePair(SDNode *N); 274 SDValue reduceBuildVecExtToExtBuildVec(SDNode *N); 275 SDValue reduceBuildVecConvertToConvertBuildVec(SDNode *N); 276 277 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 278 279 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 280 /// looking for aliasing nodes and adding them to the Aliases vector. 281 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 282 SmallVector<SDValue, 8> &Aliases); 283 284 /// isAlias - Return true if there is any possibility that the two addresses 285 /// overlap. 286 bool isAlias(SDValue Ptr1, int64_t Size1, 287 const Value *SrcValue1, int SrcValueOffset1, 288 unsigned SrcValueAlign1, 289 const MDNode *TBAAInfo1, 290 SDValue Ptr2, int64_t Size2, 291 const Value *SrcValue2, int SrcValueOffset2, 292 unsigned SrcValueAlign2, 293 const MDNode *TBAAInfo2) const; 294 295 /// isAlias - Return true if there is any possibility that the two addresses 296 /// overlap. 297 bool isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1); 298 299 /// FindAliasInfo - Extracts the relevant alias information from the memory 300 /// node. Returns true if the operand was a load. 301 bool FindAliasInfo(SDNode *N, 302 SDValue &Ptr, int64_t &Size, 303 const Value *&SrcValue, int &SrcValueOffset, 304 unsigned &SrcValueAlignment, 305 const MDNode *&TBAAInfo) const; 306 307 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 308 /// looking for a better chain (aliasing node.) 309 SDValue FindBetterChain(SDNode *N, SDValue Chain); 310 311 /// Merge consecutive store operations into a wide store. 312 /// This optimization uses wide integers or vectors when possible. 313 /// \return True if some memory operations were changed. 314 bool MergeConsecutiveStores(StoreSDNode *N); 315 316 public: 317 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 318 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes), 319 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {} 320 321 /// Run - runs the dag combiner on all nodes in the work list 322 void Run(CombineLevel AtLevel); 323 324 SelectionDAG &getDAG() const { return DAG; } 325 326 /// getShiftAmountTy - Returns a type large enough to hold any valid 327 /// shift amount - before type legalization these can be huge. 328 EVT getShiftAmountTy(EVT LHSTy) { 329 return LegalTypes ? TLI.getShiftAmountTy(LHSTy) : TLI.getPointerTy(); 330 } 331 332 /// isTypeLegal - This method returns true if we are running before type 333 /// legalization or if the specified VT is legal. 334 bool isTypeLegal(const EVT &VT) { 335 if (!LegalTypes) return true; 336 return TLI.isTypeLegal(VT); 337 } 338 }; 339} 340 341 342namespace { 343/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 344/// nodes from the worklist. 345class WorkListRemover : public SelectionDAG::DAGUpdateListener { 346 DAGCombiner &DC; 347public: 348 explicit WorkListRemover(DAGCombiner &dc) 349 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {} 350 351 virtual void NodeDeleted(SDNode *N, SDNode *E) { 352 DC.removeFromWorkList(N); 353 } 354}; 355} 356 357//===----------------------------------------------------------------------===// 358// TargetLowering::DAGCombinerInfo implementation 359//===----------------------------------------------------------------------===// 360 361void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 362 ((DAGCombiner*)DC)->AddToWorkList(N); 363} 364 365void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) { 366 ((DAGCombiner*)DC)->removeFromWorkList(N); 367} 368 369SDValue TargetLowering::DAGCombinerInfo:: 370CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 371 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 372} 373 374SDValue TargetLowering::DAGCombinerInfo:: 375CombineTo(SDNode *N, SDValue Res, bool AddTo) { 376 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 377} 378 379 380SDValue TargetLowering::DAGCombinerInfo:: 381CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 382 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 383} 384 385void TargetLowering::DAGCombinerInfo:: 386CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 387 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 388} 389 390//===----------------------------------------------------------------------===// 391// Helper Functions 392//===----------------------------------------------------------------------===// 393 394/// isNegatibleForFree - Return 1 if we can compute the negated form of the 395/// specified expression for the same cost as the expression itself, or 2 if we 396/// can compute the negated form more cheaply than the expression itself. 397static char isNegatibleForFree(SDValue Op, bool LegalOperations, 398 const TargetLowering &TLI, 399 const TargetOptions *Options, 400 unsigned Depth = 0) { 401 // fneg is removable even if it has multiple uses. 402 if (Op.getOpcode() == ISD::FNEG) return 2; 403 404 // Don't allow anything with multiple uses. 405 if (!Op.hasOneUse()) return 0; 406 407 // Don't recurse exponentially. 408 if (Depth > 6) return 0; 409 410 switch (Op.getOpcode()) { 411 default: return false; 412 case ISD::ConstantFP: 413 // Don't invert constant FP values after legalize. The negated constant 414 // isn't necessarily legal. 415 return LegalOperations ? 0 : 1; 416 case ISD::FADD: 417 // FIXME: determine better conditions for this xform. 418 if (!Options->UnsafeFPMath) return 0; 419 420 // After operation legalization, it might not be legal to create new FSUBs. 421 if (LegalOperations && 422 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) 423 return 0; 424 425 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 426 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, 427 Options, Depth + 1)) 428 return V; 429 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 430 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, 431 Depth + 1); 432 case ISD::FSUB: 433 // We can't turn -(A-B) into B-A when we honor signed zeros. 434 if (!Options->UnsafeFPMath) return 0; 435 436 // fold (fneg (fsub A, B)) -> (fsub B, A) 437 return 1; 438 439 case ISD::FMUL: 440 case ISD::FDIV: 441 if (Options->HonorSignDependentRoundingFPMath()) return 0; 442 443 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 444 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, 445 Options, Depth + 1)) 446 return V; 447 448 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, 449 Depth + 1); 450 451 case ISD::FP_EXTEND: 452 case ISD::FP_ROUND: 453 case ISD::FSIN: 454 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options, 455 Depth + 1); 456 } 457} 458 459/// GetNegatedExpression - If isNegatibleForFree returns true, this function 460/// returns the newly negated expression. 461static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 462 bool LegalOperations, unsigned Depth = 0) { 463 // fneg is removable even if it has multiple uses. 464 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 465 466 // Don't allow anything with multiple uses. 467 assert(Op.hasOneUse() && "Unknown reuse!"); 468 469 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 470 switch (Op.getOpcode()) { 471 default: llvm_unreachable("Unknown code"); 472 case ISD::ConstantFP: { 473 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 474 V.changeSign(); 475 return DAG.getConstantFP(V, Op.getValueType()); 476 } 477 case ISD::FADD: 478 // FIXME: determine better conditions for this xform. 479 assert(DAG.getTarget().Options.UnsafeFPMath); 480 481 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 482 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, 483 DAG.getTargetLoweringInfo(), 484 &DAG.getTarget().Options, Depth+1)) 485 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 486 GetNegatedExpression(Op.getOperand(0), DAG, 487 LegalOperations, Depth+1), 488 Op.getOperand(1)); 489 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 490 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 491 GetNegatedExpression(Op.getOperand(1), DAG, 492 LegalOperations, Depth+1), 493 Op.getOperand(0)); 494 case ISD::FSUB: 495 // We can't turn -(A-B) into B-A when we honor signed zeros. 496 assert(DAG.getTarget().Options.UnsafeFPMath); 497 498 // fold (fneg (fsub 0, B)) -> B 499 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 500 if (N0CFP->getValueAPF().isZero()) 501 return Op.getOperand(1); 502 503 // fold (fneg (fsub A, B)) -> (fsub B, A) 504 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 505 Op.getOperand(1), Op.getOperand(0)); 506 507 case ISD::FMUL: 508 case ISD::FDIV: 509 assert(!DAG.getTarget().Options.HonorSignDependentRoundingFPMath()); 510 511 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 512 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, 513 DAG.getTargetLoweringInfo(), 514 &DAG.getTarget().Options, Depth+1)) 515 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 516 GetNegatedExpression(Op.getOperand(0), DAG, 517 LegalOperations, Depth+1), 518 Op.getOperand(1)); 519 520 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 521 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 522 Op.getOperand(0), 523 GetNegatedExpression(Op.getOperand(1), DAG, 524 LegalOperations, Depth+1)); 525 526 case ISD::FP_EXTEND: 527 case ISD::FSIN: 528 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 529 GetNegatedExpression(Op.getOperand(0), DAG, 530 LegalOperations, Depth+1)); 531 case ISD::FP_ROUND: 532 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 533 GetNegatedExpression(Op.getOperand(0), DAG, 534 LegalOperations, Depth+1), 535 Op.getOperand(1)); 536 } 537} 538 539 540// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 541// that selects between the values 1 and 0, making it equivalent to a setcc. 542// Also, set the incoming LHS, RHS, and CC references to the appropriate 543// nodes based on the type of node we are checking. This simplifies life a 544// bit for the callers. 545static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 546 SDValue &CC) { 547 if (N.getOpcode() == ISD::SETCC) { 548 LHS = N.getOperand(0); 549 RHS = N.getOperand(1); 550 CC = N.getOperand(2); 551 return true; 552 } 553 if (N.getOpcode() == ISD::SELECT_CC && 554 N.getOperand(2).getOpcode() == ISD::Constant && 555 N.getOperand(3).getOpcode() == ISD::Constant && 556 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 557 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 558 LHS = N.getOperand(0); 559 RHS = N.getOperand(1); 560 CC = N.getOperand(4); 561 return true; 562 } 563 return false; 564} 565 566// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 567// one use. If this is true, it allows the users to invert the operation for 568// free when it is profitable to do so. 569static bool isOneUseSetCC(SDValue N) { 570 SDValue N0, N1, N2; 571 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 572 return true; 573 return false; 574} 575 576SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 577 SDValue N0, SDValue N1) { 578 EVT VT = N0.getValueType(); 579 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 580 if (isa<ConstantSDNode>(N1)) { 581 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 582 SDValue OpNode = 583 DAG.FoldConstantArithmetic(Opc, VT, 584 cast<ConstantSDNode>(N0.getOperand(1)), 585 cast<ConstantSDNode>(N1)); 586 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 587 } 588 if (N0.hasOneUse()) { 589 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 590 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 591 N0.getOperand(0), N1); 592 AddToWorkList(OpNode.getNode()); 593 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 594 } 595 } 596 597 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 598 if (isa<ConstantSDNode>(N0)) { 599 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 600 SDValue OpNode = 601 DAG.FoldConstantArithmetic(Opc, VT, 602 cast<ConstantSDNode>(N1.getOperand(1)), 603 cast<ConstantSDNode>(N0)); 604 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 605 } 606 if (N1.hasOneUse()) { 607 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 608 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 609 N1.getOperand(0), N0); 610 AddToWorkList(OpNode.getNode()); 611 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 612 } 613 } 614 615 return SDValue(); 616} 617 618SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 619 bool AddTo) { 620 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 621 ++NodesCombined; 622 DEBUG(dbgs() << "\nReplacing.1 "; 623 N->dump(&DAG); 624 dbgs() << "\nWith: "; 625 To[0].getNode()->dump(&DAG); 626 dbgs() << " and " << NumTo-1 << " other values\n"; 627 for (unsigned i = 0, e = NumTo; i != e; ++i) 628 assert((!To[i].getNode() || 629 N->getValueType(i) == To[i].getValueType()) && 630 "Cannot combine value to value of different type!")); 631 WorkListRemover DeadNodes(*this); 632 DAG.ReplaceAllUsesWith(N, To); 633 if (AddTo) { 634 // Push the new nodes and any users onto the worklist 635 for (unsigned i = 0, e = NumTo; i != e; ++i) { 636 if (To[i].getNode()) { 637 AddToWorkList(To[i].getNode()); 638 AddUsersToWorkList(To[i].getNode()); 639 } 640 } 641 } 642 643 // Finally, if the node is now dead, remove it from the graph. The node 644 // may not be dead if the replacement process recursively simplified to 645 // something else needing this node. 646 if (N->use_empty()) { 647 // Nodes can be reintroduced into the worklist. Make sure we do not 648 // process a node that has been replaced. 649 removeFromWorkList(N); 650 651 // Finally, since the node is now dead, remove it from the graph. 652 DAG.DeleteNode(N); 653 } 654 return SDValue(N, 0); 655} 656 657void DAGCombiner:: 658CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 659 // Replace all uses. If any nodes become isomorphic to other nodes and 660 // are deleted, make sure to remove them from our worklist. 661 WorkListRemover DeadNodes(*this); 662 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New); 663 664 // Push the new node and any (possibly new) users onto the worklist. 665 AddToWorkList(TLO.New.getNode()); 666 AddUsersToWorkList(TLO.New.getNode()); 667 668 // Finally, if the node is now dead, remove it from the graph. The node 669 // may not be dead if the replacement process recursively simplified to 670 // something else needing this node. 671 if (TLO.Old.getNode()->use_empty()) { 672 removeFromWorkList(TLO.Old.getNode()); 673 674 // If the operands of this node are only used by the node, they will now 675 // be dead. Make sure to visit them first to delete dead nodes early. 676 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 677 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 678 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 679 680 DAG.DeleteNode(TLO.Old.getNode()); 681 } 682} 683 684/// SimplifyDemandedBits - Check the specified integer node value to see if 685/// it can be simplified or if things it uses can be simplified by bit 686/// propagation. If so, return true. 687bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 688 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); 689 APInt KnownZero, KnownOne; 690 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 691 return false; 692 693 // Revisit the node. 694 AddToWorkList(Op.getNode()); 695 696 // Replace the old value with the new one. 697 ++NodesCombined; 698 DEBUG(dbgs() << "\nReplacing.2 "; 699 TLO.Old.getNode()->dump(&DAG); 700 dbgs() << "\nWith: "; 701 TLO.New.getNode()->dump(&DAG); 702 dbgs() << '\n'); 703 704 CommitTargetLoweringOpt(TLO); 705 return true; 706} 707 708void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) { 709 DebugLoc dl = Load->getDebugLoc(); 710 EVT VT = Load->getValueType(0); 711 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0)); 712 713 DEBUG(dbgs() << "\nReplacing.9 "; 714 Load->dump(&DAG); 715 dbgs() << "\nWith: "; 716 Trunc.getNode()->dump(&DAG); 717 dbgs() << '\n'); 718 WorkListRemover DeadNodes(*this); 719 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc); 720 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1)); 721 removeFromWorkList(Load); 722 DAG.DeleteNode(Load); 723 AddToWorkList(Trunc.getNode()); 724} 725 726SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) { 727 Replace = false; 728 DebugLoc dl = Op.getDebugLoc(); 729 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) { 730 EVT MemVT = LD->getMemoryVT(); 731 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 732 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 733 : ISD::EXTLOAD) 734 : LD->getExtensionType(); 735 Replace = true; 736 return DAG.getExtLoad(ExtType, dl, PVT, 737 LD->getChain(), LD->getBasePtr(), 738 LD->getPointerInfo(), 739 MemVT, LD->isVolatile(), 740 LD->isNonTemporal(), LD->getAlignment()); 741 } 742 743 unsigned Opc = Op.getOpcode(); 744 switch (Opc) { 745 default: break; 746 case ISD::AssertSext: 747 return DAG.getNode(ISD::AssertSext, dl, PVT, 748 SExtPromoteOperand(Op.getOperand(0), PVT), 749 Op.getOperand(1)); 750 case ISD::AssertZext: 751 return DAG.getNode(ISD::AssertZext, dl, PVT, 752 ZExtPromoteOperand(Op.getOperand(0), PVT), 753 Op.getOperand(1)); 754 case ISD::Constant: { 755 unsigned ExtOpc = 756 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 757 return DAG.getNode(ExtOpc, dl, PVT, Op); 758 } 759 } 760 761 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) 762 return SDValue(); 763 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op); 764} 765 766SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) { 767 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) 768 return SDValue(); 769 EVT OldVT = Op.getValueType(); 770 DebugLoc dl = Op.getDebugLoc(); 771 bool Replace = false; 772 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 773 if (NewOp.getNode() == 0) 774 return SDValue(); 775 AddToWorkList(NewOp.getNode()); 776 777 if (Replace) 778 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 779 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp, 780 DAG.getValueType(OldVT)); 781} 782 783SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) { 784 EVT OldVT = Op.getValueType(); 785 DebugLoc dl = Op.getDebugLoc(); 786 bool Replace = false; 787 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 788 if (NewOp.getNode() == 0) 789 return SDValue(); 790 AddToWorkList(NewOp.getNode()); 791 792 if (Replace) 793 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 794 return DAG.getZeroExtendInReg(NewOp, dl, OldVT); 795} 796 797/// PromoteIntBinOp - Promote the specified integer binary operation if the 798/// target indicates it is beneficial. e.g. On x86, it's usually better to 799/// promote i16 operations to i32 since i16 instructions are longer. 800SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) { 801 if (!LegalOperations) 802 return SDValue(); 803 804 EVT VT = Op.getValueType(); 805 if (VT.isVector() || !VT.isInteger()) 806 return SDValue(); 807 808 // If operation type is 'undesirable', e.g. i16 on x86, consider 809 // promoting it. 810 unsigned Opc = Op.getOpcode(); 811 if (TLI.isTypeDesirableForOp(Opc, VT)) 812 return SDValue(); 813 814 EVT PVT = VT; 815 // Consult target whether it is a good idea to promote this operation and 816 // what's the right type to promote it to. 817 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 818 assert(PVT != VT && "Don't know what type to promote to!"); 819 820 bool Replace0 = false; 821 SDValue N0 = Op.getOperand(0); 822 SDValue NN0 = PromoteOperand(N0, PVT, Replace0); 823 if (NN0.getNode() == 0) 824 return SDValue(); 825 826 bool Replace1 = false; 827 SDValue N1 = Op.getOperand(1); 828 SDValue NN1; 829 if (N0 == N1) 830 NN1 = NN0; 831 else { 832 NN1 = PromoteOperand(N1, PVT, Replace1); 833 if (NN1.getNode() == 0) 834 return SDValue(); 835 } 836 837 AddToWorkList(NN0.getNode()); 838 if (NN1.getNode()) 839 AddToWorkList(NN1.getNode()); 840 841 if (Replace0) 842 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode()); 843 if (Replace1) 844 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode()); 845 846 DEBUG(dbgs() << "\nPromoting "; 847 Op.getNode()->dump(&DAG)); 848 DebugLoc dl = Op.getDebugLoc(); 849 return DAG.getNode(ISD::TRUNCATE, dl, VT, 850 DAG.getNode(Opc, dl, PVT, NN0, NN1)); 851 } 852 return SDValue(); 853} 854 855/// PromoteIntShiftOp - Promote the specified integer shift operation if the 856/// target indicates it is beneficial. e.g. On x86, it's usually better to 857/// promote i16 operations to i32 since i16 instructions are longer. 858SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) { 859 if (!LegalOperations) 860 return SDValue(); 861 862 EVT VT = Op.getValueType(); 863 if (VT.isVector() || !VT.isInteger()) 864 return SDValue(); 865 866 // If operation type is 'undesirable', e.g. i16 on x86, consider 867 // promoting it. 868 unsigned Opc = Op.getOpcode(); 869 if (TLI.isTypeDesirableForOp(Opc, VT)) 870 return SDValue(); 871 872 EVT PVT = VT; 873 // Consult target whether it is a good idea to promote this operation and 874 // what's the right type to promote it to. 875 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 876 assert(PVT != VT && "Don't know what type to promote to!"); 877 878 bool Replace = false; 879 SDValue N0 = Op.getOperand(0); 880 if (Opc == ISD::SRA) 881 N0 = SExtPromoteOperand(Op.getOperand(0), PVT); 882 else if (Opc == ISD::SRL) 883 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT); 884 else 885 N0 = PromoteOperand(N0, PVT, Replace); 886 if (N0.getNode() == 0) 887 return SDValue(); 888 889 AddToWorkList(N0.getNode()); 890 if (Replace) 891 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode()); 892 893 DEBUG(dbgs() << "\nPromoting "; 894 Op.getNode()->dump(&DAG)); 895 DebugLoc dl = Op.getDebugLoc(); 896 return DAG.getNode(ISD::TRUNCATE, dl, VT, 897 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1))); 898 } 899 return SDValue(); 900} 901 902SDValue DAGCombiner::PromoteExtend(SDValue Op) { 903 if (!LegalOperations) 904 return SDValue(); 905 906 EVT VT = Op.getValueType(); 907 if (VT.isVector() || !VT.isInteger()) 908 return SDValue(); 909 910 // If operation type is 'undesirable', e.g. i16 on x86, consider 911 // promoting it. 912 unsigned Opc = Op.getOpcode(); 913 if (TLI.isTypeDesirableForOp(Opc, VT)) 914 return SDValue(); 915 916 EVT PVT = VT; 917 // Consult target whether it is a good idea to promote this operation and 918 // what's the right type to promote it to. 919 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 920 assert(PVT != VT && "Don't know what type to promote to!"); 921 // fold (aext (aext x)) -> (aext x) 922 // fold (aext (zext x)) -> (zext x) 923 // fold (aext (sext x)) -> (sext x) 924 DEBUG(dbgs() << "\nPromoting "; 925 Op.getNode()->dump(&DAG)); 926 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0)); 927 } 928 return SDValue(); 929} 930 931bool DAGCombiner::PromoteLoad(SDValue Op) { 932 if (!LegalOperations) 933 return false; 934 935 EVT VT = Op.getValueType(); 936 if (VT.isVector() || !VT.isInteger()) 937 return false; 938 939 // If operation type is 'undesirable', e.g. i16 on x86, consider 940 // promoting it. 941 unsigned Opc = Op.getOpcode(); 942 if (TLI.isTypeDesirableForOp(Opc, VT)) 943 return false; 944 945 EVT PVT = VT; 946 // Consult target whether it is a good idea to promote this operation and 947 // what's the right type to promote it to. 948 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 949 assert(PVT != VT && "Don't know what type to promote to!"); 950 951 DebugLoc dl = Op.getDebugLoc(); 952 SDNode *N = Op.getNode(); 953 LoadSDNode *LD = cast<LoadSDNode>(N); 954 EVT MemVT = LD->getMemoryVT(); 955 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 956 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 957 : ISD::EXTLOAD) 958 : LD->getExtensionType(); 959 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT, 960 LD->getChain(), LD->getBasePtr(), 961 LD->getPointerInfo(), 962 MemVT, LD->isVolatile(), 963 LD->isNonTemporal(), LD->getAlignment()); 964 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD); 965 966 DEBUG(dbgs() << "\nPromoting "; 967 N->dump(&DAG); 968 dbgs() << "\nTo: "; 969 Result.getNode()->dump(&DAG); 970 dbgs() << '\n'); 971 WorkListRemover DeadNodes(*this); 972 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result); 973 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1)); 974 removeFromWorkList(N); 975 DAG.DeleteNode(N); 976 AddToWorkList(Result.getNode()); 977 return true; 978 } 979 return false; 980} 981 982 983//===----------------------------------------------------------------------===// 984// Main DAG Combiner implementation 985//===----------------------------------------------------------------------===// 986 987void DAGCombiner::Run(CombineLevel AtLevel) { 988 // set the instance variables, so that the various visit routines may use it. 989 Level = AtLevel; 990 LegalOperations = Level >= AfterLegalizeVectorOps; 991 LegalTypes = Level >= AfterLegalizeTypes; 992 993 // Add all the dag nodes to the worklist. 994 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 995 E = DAG.allnodes_end(); I != E; ++I) 996 AddToWorkList(I); 997 998 // Create a dummy node (which is not added to allnodes), that adds a reference 999 // to the root node, preventing it from being deleted, and tracking any 1000 // changes of the root. 1001 HandleSDNode Dummy(DAG.getRoot()); 1002 1003 // The root of the dag may dangle to deleted nodes until the dag combiner is 1004 // done. Set it to null to avoid confusion. 1005 DAG.setRoot(SDValue()); 1006 1007 // while the worklist isn't empty, find a node and 1008 // try and combine it. 1009 while (!WorkListContents.empty()) { 1010 SDNode *N; 1011 // The WorkListOrder holds the SDNodes in order, but it may contain duplicates. 1012 // In order to avoid a linear scan, we use a set (O(log N)) to hold what the 1013 // worklist *should* contain, and check the node we want to visit is should 1014 // actually be visited. 1015 do { 1016 N = WorkListOrder.pop_back_val(); 1017 } while (!WorkListContents.erase(N)); 1018 1019 // If N has no uses, it is dead. Make sure to revisit all N's operands once 1020 // N is deleted from the DAG, since they too may now be dead or may have a 1021 // reduced number of uses, allowing other xforms. 1022 if (N->use_empty() && N != &Dummy) { 1023 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1024 AddToWorkList(N->getOperand(i).getNode()); 1025 1026 DAG.DeleteNode(N); 1027 continue; 1028 } 1029 1030 SDValue RV = combine(N); 1031 1032 if (RV.getNode() == 0) 1033 continue; 1034 1035 ++NodesCombined; 1036 1037 // If we get back the same node we passed in, rather than a new node or 1038 // zero, we know that the node must have defined multiple values and 1039 // CombineTo was used. Since CombineTo takes care of the worklist 1040 // mechanics for us, we have no work to do in this case. 1041 if (RV.getNode() == N) 1042 continue; 1043 1044 assert(N->getOpcode() != ISD::DELETED_NODE && 1045 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 1046 "Node was deleted but visit returned new node!"); 1047 1048 DEBUG(dbgs() << "\nReplacing.3 "; 1049 N->dump(&DAG); 1050 dbgs() << "\nWith: "; 1051 RV.getNode()->dump(&DAG); 1052 dbgs() << '\n'); 1053 1054 // Transfer debug value. 1055 DAG.TransferDbgValues(SDValue(N, 0), RV); 1056 WorkListRemover DeadNodes(*this); 1057 if (N->getNumValues() == RV.getNode()->getNumValues()) 1058 DAG.ReplaceAllUsesWith(N, RV.getNode()); 1059 else { 1060 assert(N->getValueType(0) == RV.getValueType() && 1061 N->getNumValues() == 1 && "Type mismatch"); 1062 SDValue OpV = RV; 1063 DAG.ReplaceAllUsesWith(N, &OpV); 1064 } 1065 1066 // Push the new node and any users onto the worklist 1067 AddToWorkList(RV.getNode()); 1068 AddUsersToWorkList(RV.getNode()); 1069 1070 // Add any uses of the old node to the worklist in case this node is the 1071 // last one that uses them. They may become dead after this node is 1072 // deleted. 1073 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1074 AddToWorkList(N->getOperand(i).getNode()); 1075 1076 // Finally, if the node is now dead, remove it from the graph. The node 1077 // may not be dead if the replacement process recursively simplified to 1078 // something else needing this node. 1079 if (N->use_empty()) { 1080 // Nodes can be reintroduced into the worklist. Make sure we do not 1081 // process a node that has been replaced. 1082 removeFromWorkList(N); 1083 1084 // Finally, since the node is now dead, remove it from the graph. 1085 DAG.DeleteNode(N); 1086 } 1087 } 1088 1089 // If the root changed (e.g. it was a dead load, update the root). 1090 DAG.setRoot(Dummy.getValue()); 1091 DAG.RemoveDeadNodes(); 1092} 1093 1094SDValue DAGCombiner::visit(SDNode *N) { 1095 switch (N->getOpcode()) { 1096 default: break; 1097 case ISD::TokenFactor: return visitTokenFactor(N); 1098 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 1099 case ISD::ADD: return visitADD(N); 1100 case ISD::SUB: return visitSUB(N); 1101 case ISD::ADDC: return visitADDC(N); 1102 case ISD::SUBC: return visitSUBC(N); 1103 case ISD::ADDE: return visitADDE(N); 1104 case ISD::SUBE: return visitSUBE(N); 1105 case ISD::MUL: return visitMUL(N); 1106 case ISD::SDIV: return visitSDIV(N); 1107 case ISD::UDIV: return visitUDIV(N); 1108 case ISD::SREM: return visitSREM(N); 1109 case ISD::UREM: return visitUREM(N); 1110 case ISD::MULHU: return visitMULHU(N); 1111 case ISD::MULHS: return visitMULHS(N); 1112 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 1113 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 1114 case ISD::SMULO: return visitSMULO(N); 1115 case ISD::UMULO: return visitUMULO(N); 1116 case ISD::SDIVREM: return visitSDIVREM(N); 1117 case ISD::UDIVREM: return visitUDIVREM(N); 1118 case ISD::AND: return visitAND(N); 1119 case ISD::OR: return visitOR(N); 1120 case ISD::XOR: return visitXOR(N); 1121 case ISD::SHL: return visitSHL(N); 1122 case ISD::SRA: return visitSRA(N); 1123 case ISD::SRL: return visitSRL(N); 1124 case ISD::CTLZ: return visitCTLZ(N); 1125 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N); 1126 case ISD::CTTZ: return visitCTTZ(N); 1127 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N); 1128 case ISD::CTPOP: return visitCTPOP(N); 1129 case ISD::SELECT: return visitSELECT(N); 1130 case ISD::SELECT_CC: return visitSELECT_CC(N); 1131 case ISD::SETCC: return visitSETCC(N); 1132 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 1133 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 1134 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 1135 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 1136 case ISD::TRUNCATE: return visitTRUNCATE(N); 1137 case ISD::BITCAST: return visitBITCAST(N); 1138 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 1139 case ISD::FADD: return visitFADD(N); 1140 case ISD::FSUB: return visitFSUB(N); 1141 case ISD::FMUL: return visitFMUL(N); 1142 case ISD::FMA: return visitFMA(N); 1143 case ISD::FDIV: return visitFDIV(N); 1144 case ISD::FREM: return visitFREM(N); 1145 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 1146 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 1147 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 1148 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 1149 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 1150 case ISD::FP_ROUND: return visitFP_ROUND(N); 1151 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 1152 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 1153 case ISD::FNEG: return visitFNEG(N); 1154 case ISD::FABS: return visitFABS(N); 1155 case ISD::FFLOOR: return visitFFLOOR(N); 1156 case ISD::FCEIL: return visitFCEIL(N); 1157 case ISD::FTRUNC: return visitFTRUNC(N); 1158 case ISD::BRCOND: return visitBRCOND(N); 1159 case ISD::BR_CC: return visitBR_CC(N); 1160 case ISD::LOAD: return visitLOAD(N); 1161 case ISD::STORE: return visitSTORE(N); 1162 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 1163 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 1164 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 1165 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 1166 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N); 1167 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 1168 case ISD::MEMBARRIER: return visitMEMBARRIER(N); 1169 } 1170 return SDValue(); 1171} 1172 1173SDValue DAGCombiner::combine(SDNode *N) { 1174 SDValue RV = visit(N); 1175 1176 // If nothing happened, try a target-specific DAG combine. 1177 if (RV.getNode() == 0) { 1178 assert(N->getOpcode() != ISD::DELETED_NODE && 1179 "Node was deleted but visit returned NULL!"); 1180 1181 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 1182 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 1183 1184 // Expose the DAG combiner to the target combiner impls. 1185 TargetLowering::DAGCombinerInfo 1186 DagCombineInfo(DAG, Level, false, this); 1187 1188 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 1189 } 1190 } 1191 1192 // If nothing happened still, try promoting the operation. 1193 if (RV.getNode() == 0) { 1194 switch (N->getOpcode()) { 1195 default: break; 1196 case ISD::ADD: 1197 case ISD::SUB: 1198 case ISD::MUL: 1199 case ISD::AND: 1200 case ISD::OR: 1201 case ISD::XOR: 1202 RV = PromoteIntBinOp(SDValue(N, 0)); 1203 break; 1204 case ISD::SHL: 1205 case ISD::SRA: 1206 case ISD::SRL: 1207 RV = PromoteIntShiftOp(SDValue(N, 0)); 1208 break; 1209 case ISD::SIGN_EXTEND: 1210 case ISD::ZERO_EXTEND: 1211 case ISD::ANY_EXTEND: 1212 RV = PromoteExtend(SDValue(N, 0)); 1213 break; 1214 case ISD::LOAD: 1215 if (PromoteLoad(SDValue(N, 0))) 1216 RV = SDValue(N, 0); 1217 break; 1218 } 1219 } 1220 1221 // If N is a commutative binary node, try commuting it to enable more 1222 // sdisel CSE. 1223 if (RV.getNode() == 0 && 1224 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 1225 N->getNumValues() == 1) { 1226 SDValue N0 = N->getOperand(0); 1227 SDValue N1 = N->getOperand(1); 1228 1229 // Constant operands are canonicalized to RHS. 1230 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 1231 SDValue Ops[] = { N1, N0 }; 1232 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 1233 Ops, 2); 1234 if (CSENode) 1235 return SDValue(CSENode, 0); 1236 } 1237 } 1238 1239 return RV; 1240} 1241 1242/// getInputChainForNode - Given a node, return its input chain if it has one, 1243/// otherwise return a null sd operand. 1244static SDValue getInputChainForNode(SDNode *N) { 1245 if (unsigned NumOps = N->getNumOperands()) { 1246 if (N->getOperand(0).getValueType() == MVT::Other) 1247 return N->getOperand(0); 1248 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 1249 return N->getOperand(NumOps-1); 1250 for (unsigned i = 1; i < NumOps-1; ++i) 1251 if (N->getOperand(i).getValueType() == MVT::Other) 1252 return N->getOperand(i); 1253 } 1254 return SDValue(); 1255} 1256 1257SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 1258 // If N has two operands, where one has an input chain equal to the other, 1259 // the 'other' chain is redundant. 1260 if (N->getNumOperands() == 2) { 1261 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 1262 return N->getOperand(0); 1263 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 1264 return N->getOperand(1); 1265 } 1266 1267 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 1268 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 1269 SmallPtrSet<SDNode*, 16> SeenOps; 1270 bool Changed = false; // If we should replace this token factor. 1271 1272 // Start out with this token factor. 1273 TFs.push_back(N); 1274 1275 // Iterate through token factors. The TFs grows when new token factors are 1276 // encountered. 1277 for (unsigned i = 0; i < TFs.size(); ++i) { 1278 SDNode *TF = TFs[i]; 1279 1280 // Check each of the operands. 1281 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 1282 SDValue Op = TF->getOperand(i); 1283 1284 switch (Op.getOpcode()) { 1285 case ISD::EntryToken: 1286 // Entry tokens don't need to be added to the list. They are 1287 // rededundant. 1288 Changed = true; 1289 break; 1290 1291 case ISD::TokenFactor: 1292 if (Op.hasOneUse() && 1293 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 1294 // Queue up for processing. 1295 TFs.push_back(Op.getNode()); 1296 // Clean up in case the token factor is removed. 1297 AddToWorkList(Op.getNode()); 1298 Changed = true; 1299 break; 1300 } 1301 // Fall thru 1302 1303 default: 1304 // Only add if it isn't already in the list. 1305 if (SeenOps.insert(Op.getNode())) 1306 Ops.push_back(Op); 1307 else 1308 Changed = true; 1309 break; 1310 } 1311 } 1312 } 1313 1314 SDValue Result; 1315 1316 // If we've change things around then replace token factor. 1317 if (Changed) { 1318 if (Ops.empty()) { 1319 // The entry token is the only possible outcome. 1320 Result = DAG.getEntryNode(); 1321 } else { 1322 // New and improved token factor. 1323 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 1324 MVT::Other, &Ops[0], Ops.size()); 1325 } 1326 1327 // Don't add users to work list. 1328 return CombineTo(N, Result, false); 1329 } 1330 1331 return Result; 1332} 1333 1334/// MERGE_VALUES can always be eliminated. 1335SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 1336 WorkListRemover DeadNodes(*this); 1337 // Replacing results may cause a different MERGE_VALUES to suddenly 1338 // be CSE'd with N, and carry its uses with it. Iterate until no 1339 // uses remain, to ensure that the node can be safely deleted. 1340 // First add the users of this node to the work list so that they 1341 // can be tried again once they have new operands. 1342 AddUsersToWorkList(N); 1343 do { 1344 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1345 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i)); 1346 } while (!N->use_empty()); 1347 removeFromWorkList(N); 1348 DAG.DeleteNode(N); 1349 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1350} 1351 1352static 1353SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 1354 SelectionDAG &DAG) { 1355 EVT VT = N0.getValueType(); 1356 SDValue N00 = N0.getOperand(0); 1357 SDValue N01 = N0.getOperand(1); 1358 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 1359 1360 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 1361 isa<ConstantSDNode>(N00.getOperand(1))) { 1362 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1363 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 1364 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 1365 N00.getOperand(0), N01), 1366 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 1367 N00.getOperand(1), N01)); 1368 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 1369 } 1370 1371 return SDValue(); 1372} 1373 1374SDValue DAGCombiner::visitADD(SDNode *N) { 1375 SDValue N0 = N->getOperand(0); 1376 SDValue N1 = N->getOperand(1); 1377 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1378 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1379 EVT VT = N0.getValueType(); 1380 1381 // fold vector ops 1382 if (VT.isVector()) { 1383 SDValue FoldedVOp = SimplifyVBinOp(N); 1384 if (FoldedVOp.getNode()) return FoldedVOp; 1385 1386 // fold (add x, 0) -> x, vector edition 1387 if (ISD::isBuildVectorAllZeros(N1.getNode())) 1388 return N0; 1389 if (ISD::isBuildVectorAllZeros(N0.getNode())) 1390 return N1; 1391 } 1392 1393 // fold (add x, undef) -> undef 1394 if (N0.getOpcode() == ISD::UNDEF) 1395 return N0; 1396 if (N1.getOpcode() == ISD::UNDEF) 1397 return N1; 1398 // fold (add c1, c2) -> c1+c2 1399 if (N0C && N1C) 1400 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 1401 // canonicalize constant to RHS 1402 if (N0C && !N1C) 1403 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 1404 // fold (add x, 0) -> x 1405 if (N1C && N1C->isNullValue()) 1406 return N0; 1407 // fold (add Sym, c) -> Sym+c 1408 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1409 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1410 GA->getOpcode() == ISD::GlobalAddress) 1411 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1412 GA->getOffset() + 1413 (uint64_t)N1C->getSExtValue()); 1414 // fold ((c1-A)+c2) -> (c1+c2)-A 1415 if (N1C && N0.getOpcode() == ISD::SUB) 1416 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1417 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1418 DAG.getConstant(N1C->getAPIntValue()+ 1419 N0C->getAPIntValue(), VT), 1420 N0.getOperand(1)); 1421 // reassociate add 1422 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1423 if (RADD.getNode() != 0) 1424 return RADD; 1425 // fold ((0-A) + B) -> B-A 1426 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1427 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1428 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1429 // fold (A + (0-B)) -> A-B 1430 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1431 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1432 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1433 // fold (A+(B-A)) -> B 1434 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1435 return N1.getOperand(0); 1436 // fold ((B-A)+A) -> B 1437 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1438 return N0.getOperand(0); 1439 // fold (A+(B-(A+C))) to (B-C) 1440 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1441 N0 == N1.getOperand(1).getOperand(0)) 1442 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1443 N1.getOperand(1).getOperand(1)); 1444 // fold (A+(B-(C+A))) to (B-C) 1445 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1446 N0 == N1.getOperand(1).getOperand(1)) 1447 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1448 N1.getOperand(1).getOperand(0)); 1449 // fold (A+((B-A)+or-C)) to (B+or-C) 1450 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1451 N1.getOperand(0).getOpcode() == ISD::SUB && 1452 N0 == N1.getOperand(0).getOperand(1)) 1453 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1454 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1455 1456 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1457 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1458 SDValue N00 = N0.getOperand(0); 1459 SDValue N01 = N0.getOperand(1); 1460 SDValue N10 = N1.getOperand(0); 1461 SDValue N11 = N1.getOperand(1); 1462 1463 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1464 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1465 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1466 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1467 } 1468 1469 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1470 return SDValue(N, 0); 1471 1472 // fold (a+b) -> (a|b) iff a and b share no bits. 1473 if (VT.isInteger() && !VT.isVector()) { 1474 APInt LHSZero, LHSOne; 1475 APInt RHSZero, RHSOne; 1476 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne); 1477 1478 if (LHSZero.getBoolValue()) { 1479 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne); 1480 1481 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1482 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1483 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero) 1484 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1485 } 1486 } 1487 1488 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1489 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1490 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1491 if (Result.getNode()) return Result; 1492 } 1493 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1494 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1495 if (Result.getNode()) return Result; 1496 } 1497 1498 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n)) 1499 if (N1.getOpcode() == ISD::SHL && 1500 N1.getOperand(0).getOpcode() == ISD::SUB) 1501 if (ConstantSDNode *C = 1502 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0))) 1503 if (C->getAPIntValue() == 0) 1504 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, 1505 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1506 N1.getOperand(0).getOperand(1), 1507 N1.getOperand(1))); 1508 if (N0.getOpcode() == ISD::SHL && 1509 N0.getOperand(0).getOpcode() == ISD::SUB) 1510 if (ConstantSDNode *C = 1511 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0))) 1512 if (C->getAPIntValue() == 0) 1513 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, 1514 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1515 N0.getOperand(0).getOperand(1), 1516 N0.getOperand(1))); 1517 1518 if (N1.getOpcode() == ISD::AND) { 1519 SDValue AndOp0 = N1.getOperand(0); 1520 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1)); 1521 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0); 1522 unsigned DestBits = VT.getScalarType().getSizeInBits(); 1523 1524 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x)) 1525 // and similar xforms where the inner op is either ~0 or 0. 1526 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) { 1527 DebugLoc DL = N->getDebugLoc(); 1528 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0); 1529 } 1530 } 1531 1532 // add (sext i1), X -> sub X, (zext i1) 1533 if (N0.getOpcode() == ISD::SIGN_EXTEND && 1534 N0.getOperand(0).getValueType() == MVT::i1 && 1535 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) { 1536 DebugLoc DL = N->getDebugLoc(); 1537 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); 1538 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt); 1539 } 1540 1541 return SDValue(); 1542} 1543 1544SDValue DAGCombiner::visitADDC(SDNode *N) { 1545 SDValue N0 = N->getOperand(0); 1546 SDValue N1 = N->getOperand(1); 1547 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1548 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1549 EVT VT = N0.getValueType(); 1550 1551 // If the flag result is dead, turn this into an ADD. 1552 if (!N->hasAnyUseOfValue(1)) 1553 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N1), 1554 DAG.getNode(ISD::CARRY_FALSE, 1555 N->getDebugLoc(), MVT::Glue)); 1556 1557 // canonicalize constant to RHS. 1558 if (N0C && !N1C) 1559 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1560 1561 // fold (addc x, 0) -> x + no carry out 1562 if (N1C && N1C->isNullValue()) 1563 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1564 N->getDebugLoc(), MVT::Glue)); 1565 1566 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1567 APInt LHSZero, LHSOne; 1568 APInt RHSZero, RHSOne; 1569 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne); 1570 1571 if (LHSZero.getBoolValue()) { 1572 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne); 1573 1574 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1575 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1576 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero) 1577 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1578 DAG.getNode(ISD::CARRY_FALSE, 1579 N->getDebugLoc(), MVT::Glue)); 1580 } 1581 1582 return SDValue(); 1583} 1584 1585SDValue DAGCombiner::visitADDE(SDNode *N) { 1586 SDValue N0 = N->getOperand(0); 1587 SDValue N1 = N->getOperand(1); 1588 SDValue CarryIn = N->getOperand(2); 1589 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1590 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1591 1592 // canonicalize constant to RHS 1593 if (N0C && !N1C) 1594 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1595 N1, N0, CarryIn); 1596 1597 // fold (adde x, y, false) -> (addc x, y) 1598 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1599 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N0, N1); 1600 1601 return SDValue(); 1602} 1603 1604// Since it may not be valid to emit a fold to zero for vector initializers 1605// check if we can before folding. 1606static SDValue tryFoldToZero(DebugLoc DL, const TargetLowering &TLI, EVT VT, 1607 SelectionDAG &DAG, bool LegalOperations) { 1608 if (!VT.isVector()) { 1609 return DAG.getConstant(0, VT); 1610 } 1611 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 1612 // Produce a vector of zeros. 1613 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 1614 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 1615 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, 1616 &Ops[0], Ops.size()); 1617 } 1618 return SDValue(); 1619} 1620 1621SDValue DAGCombiner::visitSUB(SDNode *N) { 1622 SDValue N0 = N->getOperand(0); 1623 SDValue N1 = N->getOperand(1); 1624 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1625 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1626 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? 0 : 1627 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode()); 1628 EVT VT = N0.getValueType(); 1629 1630 // fold vector ops 1631 if (VT.isVector()) { 1632 SDValue FoldedVOp = SimplifyVBinOp(N); 1633 if (FoldedVOp.getNode()) return FoldedVOp; 1634 1635 // fold (sub x, 0) -> x, vector edition 1636 if (ISD::isBuildVectorAllZeros(N1.getNode())) 1637 return N0; 1638 } 1639 1640 // fold (sub x, x) -> 0 1641 // FIXME: Refactor this and xor and other similar operations together. 1642 if (N0 == N1) 1643 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 1644 // fold (sub c1, c2) -> c1-c2 1645 if (N0C && N1C) 1646 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1647 // fold (sub x, c) -> (add x, -c) 1648 if (N1C) 1649 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1650 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1651 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) 1652 if (N0C && N0C->isAllOnesValue()) 1653 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 1654 // fold A-(A-B) -> B 1655 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0)) 1656 return N1.getOperand(1); 1657 // fold (A+B)-A -> B 1658 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1659 return N0.getOperand(1); 1660 // fold (A+B)-B -> A 1661 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1662 return N0.getOperand(0); 1663 // fold C2-(A+C1) -> (C2-C1)-A 1664 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) { 1665 SDValue NewC = DAG.getConstant(N0C->getAPIntValue() - N1C1->getAPIntValue(), 1666 VT); 1667 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, NewC, 1668 N1.getOperand(0)); 1669 } 1670 // fold ((A+(B+or-C))-B) -> A+or-C 1671 if (N0.getOpcode() == ISD::ADD && 1672 (N0.getOperand(1).getOpcode() == ISD::SUB || 1673 N0.getOperand(1).getOpcode() == ISD::ADD) && 1674 N0.getOperand(1).getOperand(0) == N1) 1675 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1676 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1677 // fold ((A+(C+B))-B) -> A+C 1678 if (N0.getOpcode() == ISD::ADD && 1679 N0.getOperand(1).getOpcode() == ISD::ADD && 1680 N0.getOperand(1).getOperand(1) == N1) 1681 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1682 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1683 // fold ((A-(B-C))-C) -> A-B 1684 if (N0.getOpcode() == ISD::SUB && 1685 N0.getOperand(1).getOpcode() == ISD::SUB && 1686 N0.getOperand(1).getOperand(1) == N1) 1687 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1688 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1689 1690 // If either operand of a sub is undef, the result is undef 1691 if (N0.getOpcode() == ISD::UNDEF) 1692 return N0; 1693 if (N1.getOpcode() == ISD::UNDEF) 1694 return N1; 1695 1696 // If the relocation model supports it, consider symbol offsets. 1697 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1698 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1699 // fold (sub Sym, c) -> Sym-c 1700 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1701 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1702 GA->getOffset() - 1703 (uint64_t)N1C->getSExtValue()); 1704 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1705 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1706 if (GA->getGlobal() == GB->getGlobal()) 1707 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1708 VT); 1709 } 1710 1711 return SDValue(); 1712} 1713 1714SDValue DAGCombiner::visitSUBC(SDNode *N) { 1715 SDValue N0 = N->getOperand(0); 1716 SDValue N1 = N->getOperand(1); 1717 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1718 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1719 EVT VT = N0.getValueType(); 1720 1721 // If the flag result is dead, turn this into an SUB. 1722 if (!N->hasAnyUseOfValue(1)) 1723 return CombineTo(N, DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1), 1724 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1725 MVT::Glue)); 1726 1727 // fold (subc x, x) -> 0 + no borrow 1728 if (N0 == N1) 1729 return CombineTo(N, DAG.getConstant(0, VT), 1730 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1731 MVT::Glue)); 1732 1733 // fold (subc x, 0) -> x + no borrow 1734 if (N1C && N1C->isNullValue()) 1735 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1736 MVT::Glue)); 1737 1738 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow 1739 if (N0C && N0C->isAllOnesValue()) 1740 return CombineTo(N, DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0), 1741 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1742 MVT::Glue)); 1743 1744 return SDValue(); 1745} 1746 1747SDValue DAGCombiner::visitSUBE(SDNode *N) { 1748 SDValue N0 = N->getOperand(0); 1749 SDValue N1 = N->getOperand(1); 1750 SDValue CarryIn = N->getOperand(2); 1751 1752 // fold (sube x, y, false) -> (subc x, y) 1753 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1754 return DAG.getNode(ISD::SUBC, N->getDebugLoc(), N->getVTList(), N0, N1); 1755 1756 return SDValue(); 1757} 1758 1759SDValue DAGCombiner::visitMUL(SDNode *N) { 1760 SDValue N0 = N->getOperand(0); 1761 SDValue N1 = N->getOperand(1); 1762 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1763 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1764 EVT VT = N0.getValueType(); 1765 1766 // fold vector ops 1767 if (VT.isVector()) { 1768 SDValue FoldedVOp = SimplifyVBinOp(N); 1769 if (FoldedVOp.getNode()) return FoldedVOp; 1770 } 1771 1772 // fold (mul x, undef) -> 0 1773 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1774 return DAG.getConstant(0, VT); 1775 // fold (mul c1, c2) -> c1*c2 1776 if (N0C && N1C) 1777 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1778 // canonicalize constant to RHS 1779 if (N0C && !N1C) 1780 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1781 // fold (mul x, 0) -> 0 1782 if (N1C && N1C->isNullValue()) 1783 return N1; 1784 // fold (mul x, -1) -> 0-x 1785 if (N1C && N1C->isAllOnesValue()) 1786 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1787 DAG.getConstant(0, VT), N0); 1788 // fold (mul x, (1 << c)) -> x << c 1789 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1790 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1791 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1792 getShiftAmountTy(N0.getValueType()))); 1793 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1794 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1795 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1796 // FIXME: If the input is something that is easily negated (e.g. a 1797 // single-use add), we should put the negate there. 1798 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1799 DAG.getConstant(0, VT), 1800 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1801 DAG.getConstant(Log2Val, 1802 getShiftAmountTy(N0.getValueType())))); 1803 } 1804 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1805 if (N1C && N0.getOpcode() == ISD::SHL && 1806 isa<ConstantSDNode>(N0.getOperand(1))) { 1807 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1808 N1, N0.getOperand(1)); 1809 AddToWorkList(C3.getNode()); 1810 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1811 N0.getOperand(0), C3); 1812 } 1813 1814 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1815 // use. 1816 { 1817 SDValue Sh(0,0), Y(0,0); 1818 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1819 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1820 N0.getNode()->hasOneUse()) { 1821 Sh = N0; Y = N1; 1822 } else if (N1.getOpcode() == ISD::SHL && 1823 isa<ConstantSDNode>(N1.getOperand(1)) && 1824 N1.getNode()->hasOneUse()) { 1825 Sh = N1; Y = N0; 1826 } 1827 1828 if (Sh.getNode()) { 1829 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1830 Sh.getOperand(0), Y); 1831 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1832 Mul, Sh.getOperand(1)); 1833 } 1834 } 1835 1836 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1837 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1838 isa<ConstantSDNode>(N0.getOperand(1))) 1839 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1840 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1841 N0.getOperand(0), N1), 1842 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1843 N0.getOperand(1), N1)); 1844 1845 // reassociate mul 1846 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1847 if (RMUL.getNode() != 0) 1848 return RMUL; 1849 1850 return SDValue(); 1851} 1852 1853SDValue DAGCombiner::visitSDIV(SDNode *N) { 1854 SDValue N0 = N->getOperand(0); 1855 SDValue N1 = N->getOperand(1); 1856 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1857 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1858 EVT VT = N->getValueType(0); 1859 1860 // fold vector ops 1861 if (VT.isVector()) { 1862 SDValue FoldedVOp = SimplifyVBinOp(N); 1863 if (FoldedVOp.getNode()) return FoldedVOp; 1864 } 1865 1866 // fold (sdiv c1, c2) -> c1/c2 1867 if (N0C && N1C && !N1C->isNullValue()) 1868 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1869 // fold (sdiv X, 1) -> X 1870 if (N1C && N1C->getAPIntValue() == 1LL) 1871 return N0; 1872 // fold (sdiv X, -1) -> 0-X 1873 if (N1C && N1C->isAllOnesValue()) 1874 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1875 DAG.getConstant(0, VT), N0); 1876 // If we know the sign bits of both operands are zero, strength reduce to a 1877 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1878 if (!VT.isVector()) { 1879 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1880 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1881 N0, N1); 1882 } 1883 // fold (sdiv X, pow2) -> simple ops after legalize 1884 if (N1C && !N1C->isNullValue() && 1885 (N1C->getAPIntValue().isPowerOf2() || 1886 (-N1C->getAPIntValue()).isPowerOf2())) { 1887 // If dividing by powers of two is cheap, then don't perform the following 1888 // fold. 1889 if (TLI.isPow2DivCheap()) 1890 return SDValue(); 1891 1892 unsigned lg2 = N1C->getAPIntValue().countTrailingZeros(); 1893 1894 // Splat the sign bit into the register 1895 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1896 DAG.getConstant(VT.getSizeInBits()-1, 1897 getShiftAmountTy(N0.getValueType()))); 1898 AddToWorkList(SGN.getNode()); 1899 1900 // Add (N0 < 0) ? abs2 - 1 : 0; 1901 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1902 DAG.getConstant(VT.getSizeInBits() - lg2, 1903 getShiftAmountTy(SGN.getValueType()))); 1904 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1905 AddToWorkList(SRL.getNode()); 1906 AddToWorkList(ADD.getNode()); // Divide by pow2 1907 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1908 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType()))); 1909 1910 // If we're dividing by a positive value, we're done. Otherwise, we must 1911 // negate the result. 1912 if (N1C->getAPIntValue().isNonNegative()) 1913 return SRA; 1914 1915 AddToWorkList(SRA.getNode()); 1916 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1917 DAG.getConstant(0, VT), SRA); 1918 } 1919 1920 // if integer divide is expensive and we satisfy the requirements, emit an 1921 // alternate sequence. 1922 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1923 SDValue Op = BuildSDIV(N); 1924 if (Op.getNode()) return Op; 1925 } 1926 1927 // undef / X -> 0 1928 if (N0.getOpcode() == ISD::UNDEF) 1929 return DAG.getConstant(0, VT); 1930 // X / undef -> undef 1931 if (N1.getOpcode() == ISD::UNDEF) 1932 return N1; 1933 1934 return SDValue(); 1935} 1936 1937SDValue DAGCombiner::visitUDIV(SDNode *N) { 1938 SDValue N0 = N->getOperand(0); 1939 SDValue N1 = N->getOperand(1); 1940 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1941 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1942 EVT VT = N->getValueType(0); 1943 1944 // fold vector ops 1945 if (VT.isVector()) { 1946 SDValue FoldedVOp = SimplifyVBinOp(N); 1947 if (FoldedVOp.getNode()) return FoldedVOp; 1948 } 1949 1950 // fold (udiv c1, c2) -> c1/c2 1951 if (N0C && N1C && !N1C->isNullValue()) 1952 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1953 // fold (udiv x, (1 << c)) -> x >>u c 1954 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1955 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1956 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1957 getShiftAmountTy(N0.getValueType()))); 1958 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1959 if (N1.getOpcode() == ISD::SHL) { 1960 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1961 if (SHC->getAPIntValue().isPowerOf2()) { 1962 EVT ADDVT = N1.getOperand(1).getValueType(); 1963 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1964 N1.getOperand(1), 1965 DAG.getConstant(SHC->getAPIntValue() 1966 .logBase2(), 1967 ADDVT)); 1968 AddToWorkList(Add.getNode()); 1969 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1970 } 1971 } 1972 } 1973 // fold (udiv x, c) -> alternate 1974 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1975 SDValue Op = BuildUDIV(N); 1976 if (Op.getNode()) return Op; 1977 } 1978 1979 // undef / X -> 0 1980 if (N0.getOpcode() == ISD::UNDEF) 1981 return DAG.getConstant(0, VT); 1982 // X / undef -> undef 1983 if (N1.getOpcode() == ISD::UNDEF) 1984 return N1; 1985 1986 return SDValue(); 1987} 1988 1989SDValue DAGCombiner::visitSREM(SDNode *N) { 1990 SDValue N0 = N->getOperand(0); 1991 SDValue N1 = N->getOperand(1); 1992 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1993 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1994 EVT VT = N->getValueType(0); 1995 1996 // fold (srem c1, c2) -> c1%c2 1997 if (N0C && N1C && !N1C->isNullValue()) 1998 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1999 // If we know the sign bits of both operands are zero, strength reduce to a 2000 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 2001 if (!VT.isVector()) { 2002 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 2003 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 2004 } 2005 2006 // If X/C can be simplified by the division-by-constant logic, lower 2007 // X%C to the equivalent of X-X/C*C. 2008 if (N1C && !N1C->isNullValue()) { 2009 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 2010 AddToWorkList(Div.getNode()); 2011 SDValue OptimizedDiv = combine(Div.getNode()); 2012 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 2013 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 2014 OptimizedDiv, N1); 2015 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 2016 AddToWorkList(Mul.getNode()); 2017 return Sub; 2018 } 2019 } 2020 2021 // undef % X -> 0 2022 if (N0.getOpcode() == ISD::UNDEF) 2023 return DAG.getConstant(0, VT); 2024 // X % undef -> undef 2025 if (N1.getOpcode() == ISD::UNDEF) 2026 return N1; 2027 2028 return SDValue(); 2029} 2030 2031SDValue DAGCombiner::visitUREM(SDNode *N) { 2032 SDValue N0 = N->getOperand(0); 2033 SDValue N1 = N->getOperand(1); 2034 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2035 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2036 EVT VT = N->getValueType(0); 2037 2038 // fold (urem c1, c2) -> c1%c2 2039 if (N0C && N1C && !N1C->isNullValue()) 2040 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 2041 // fold (urem x, pow2) -> (and x, pow2-1) 2042 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 2043 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 2044 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 2045 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 2046 if (N1.getOpcode() == ISD::SHL) { 2047 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 2048 if (SHC->getAPIntValue().isPowerOf2()) { 2049 SDValue Add = 2050 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 2051 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 2052 VT)); 2053 AddToWorkList(Add.getNode()); 2054 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 2055 } 2056 } 2057 } 2058 2059 // If X/C can be simplified by the division-by-constant logic, lower 2060 // X%C to the equivalent of X-X/C*C. 2061 if (N1C && !N1C->isNullValue()) { 2062 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 2063 AddToWorkList(Div.getNode()); 2064 SDValue OptimizedDiv = combine(Div.getNode()); 2065 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 2066 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 2067 OptimizedDiv, N1); 2068 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 2069 AddToWorkList(Mul.getNode()); 2070 return Sub; 2071 } 2072 } 2073 2074 // undef % X -> 0 2075 if (N0.getOpcode() == ISD::UNDEF) 2076 return DAG.getConstant(0, VT); 2077 // X % undef -> undef 2078 if (N1.getOpcode() == ISD::UNDEF) 2079 return N1; 2080 2081 return SDValue(); 2082} 2083 2084SDValue DAGCombiner::visitMULHS(SDNode *N) { 2085 SDValue N0 = N->getOperand(0); 2086 SDValue N1 = N->getOperand(1); 2087 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2088 EVT VT = N->getValueType(0); 2089 DebugLoc DL = N->getDebugLoc(); 2090 2091 // fold (mulhs x, 0) -> 0 2092 if (N1C && N1C->isNullValue()) 2093 return N1; 2094 // fold (mulhs x, 1) -> (sra x, size(x)-1) 2095 if (N1C && N1C->getAPIntValue() == 1) 2096 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 2097 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 2098 getShiftAmountTy(N0.getValueType()))); 2099 // fold (mulhs x, undef) -> 0 2100 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2101 return DAG.getConstant(0, VT); 2102 2103 // If the type twice as wide is legal, transform the mulhs to a wider multiply 2104 // plus a shift. 2105 if (VT.isSimple() && !VT.isVector()) { 2106 MVT Simple = VT.getSimpleVT(); 2107 unsigned SimpleSize = Simple.getSizeInBits(); 2108 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2109 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2110 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); 2111 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); 2112 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2113 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2114 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2115 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2116 } 2117 } 2118 2119 return SDValue(); 2120} 2121 2122SDValue DAGCombiner::visitMULHU(SDNode *N) { 2123 SDValue N0 = N->getOperand(0); 2124 SDValue N1 = N->getOperand(1); 2125 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2126 EVT VT = N->getValueType(0); 2127 DebugLoc DL = N->getDebugLoc(); 2128 2129 // fold (mulhu x, 0) -> 0 2130 if (N1C && N1C->isNullValue()) 2131 return N1; 2132 // fold (mulhu x, 1) -> 0 2133 if (N1C && N1C->getAPIntValue() == 1) 2134 return DAG.getConstant(0, N0.getValueType()); 2135 // fold (mulhu x, undef) -> 0 2136 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2137 return DAG.getConstant(0, VT); 2138 2139 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2140 // plus a shift. 2141 if (VT.isSimple() && !VT.isVector()) { 2142 MVT Simple = VT.getSimpleVT(); 2143 unsigned SimpleSize = Simple.getSizeInBits(); 2144 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2145 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2146 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); 2147 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1); 2148 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2149 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2150 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2151 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2152 } 2153 } 2154 2155 return SDValue(); 2156} 2157 2158/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 2159/// compute two values. LoOp and HiOp give the opcodes for the two computations 2160/// that are being performed. Return true if a simplification was made. 2161/// 2162SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 2163 unsigned HiOp) { 2164 // If the high half is not needed, just compute the low half. 2165 bool HiExists = N->hasAnyUseOfValue(1); 2166 if (!HiExists && 2167 (!LegalOperations || 2168 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 2169 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2170 N->op_begin(), N->getNumOperands()); 2171 return CombineTo(N, Res, Res); 2172 } 2173 2174 // If the low half is not needed, just compute the high half. 2175 bool LoExists = N->hasAnyUseOfValue(0); 2176 if (!LoExists && 2177 (!LegalOperations || 2178 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 2179 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2180 N->op_begin(), N->getNumOperands()); 2181 return CombineTo(N, Res, Res); 2182 } 2183 2184 // If both halves are used, return as it is. 2185 if (LoExists && HiExists) 2186 return SDValue(); 2187 2188 // If the two computed results can be simplified separately, separate them. 2189 if (LoExists) { 2190 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2191 N->op_begin(), N->getNumOperands()); 2192 AddToWorkList(Lo.getNode()); 2193 SDValue LoOpt = combine(Lo.getNode()); 2194 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 2195 (!LegalOperations || 2196 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 2197 return CombineTo(N, LoOpt, LoOpt); 2198 } 2199 2200 if (HiExists) { 2201 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2202 N->op_begin(), N->getNumOperands()); 2203 AddToWorkList(Hi.getNode()); 2204 SDValue HiOpt = combine(Hi.getNode()); 2205 if (HiOpt.getNode() && HiOpt != Hi && 2206 (!LegalOperations || 2207 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 2208 return CombineTo(N, HiOpt, HiOpt); 2209 } 2210 2211 return SDValue(); 2212} 2213 2214SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 2215 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 2216 if (Res.getNode()) return Res; 2217 2218 EVT VT = N->getValueType(0); 2219 DebugLoc DL = N->getDebugLoc(); 2220 2221 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2222 // plus a shift. 2223 if (VT.isSimple() && !VT.isVector()) { 2224 MVT Simple = VT.getSimpleVT(); 2225 unsigned SimpleSize = Simple.getSizeInBits(); 2226 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2227 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2228 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0)); 2229 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1)); 2230 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2231 // Compute the high part as N1. 2232 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2233 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2234 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2235 // Compute the low part as N0. 2236 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2237 return CombineTo(N, Lo, Hi); 2238 } 2239 } 2240 2241 return SDValue(); 2242} 2243 2244SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 2245 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 2246 if (Res.getNode()) return Res; 2247 2248 EVT VT = N->getValueType(0); 2249 DebugLoc DL = N->getDebugLoc(); 2250 2251 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2252 // plus a shift. 2253 if (VT.isSimple() && !VT.isVector()) { 2254 MVT Simple = VT.getSimpleVT(); 2255 unsigned SimpleSize = Simple.getSizeInBits(); 2256 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2257 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2258 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0)); 2259 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1)); 2260 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2261 // Compute the high part as N1. 2262 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2263 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2264 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2265 // Compute the low part as N0. 2266 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2267 return CombineTo(N, Lo, Hi); 2268 } 2269 } 2270 2271 return SDValue(); 2272} 2273 2274SDValue DAGCombiner::visitSMULO(SDNode *N) { 2275 // (smulo x, 2) -> (saddo x, x) 2276 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2277 if (C2->getAPIntValue() == 2) 2278 return DAG.getNode(ISD::SADDO, N->getDebugLoc(), N->getVTList(), 2279 N->getOperand(0), N->getOperand(0)); 2280 2281 return SDValue(); 2282} 2283 2284SDValue DAGCombiner::visitUMULO(SDNode *N) { 2285 // (umulo x, 2) -> (uaddo x, x) 2286 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2287 if (C2->getAPIntValue() == 2) 2288 return DAG.getNode(ISD::UADDO, N->getDebugLoc(), N->getVTList(), 2289 N->getOperand(0), N->getOperand(0)); 2290 2291 return SDValue(); 2292} 2293 2294SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 2295 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 2296 if (Res.getNode()) return Res; 2297 2298 return SDValue(); 2299} 2300 2301SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 2302 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 2303 if (Res.getNode()) return Res; 2304 2305 return SDValue(); 2306} 2307 2308/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 2309/// two operands of the same opcode, try to simplify it. 2310SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 2311 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 2312 EVT VT = N0.getValueType(); 2313 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 2314 2315 // Bail early if none of these transforms apply. 2316 if (N0.getNode()->getNumOperands() == 0) return SDValue(); 2317 2318 // For each of OP in AND/OR/XOR: 2319 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 2320 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 2321 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 2322 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free) 2323 // 2324 // do not sink logical op inside of a vector extend, since it may combine 2325 // into a vsetcc. 2326 EVT Op0VT = N0.getOperand(0).getValueType(); 2327 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 2328 N0.getOpcode() == ISD::SIGN_EXTEND || 2329 // Avoid infinite looping with PromoteIntBinOp. 2330 (N0.getOpcode() == ISD::ANY_EXTEND && 2331 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) || 2332 (N0.getOpcode() == ISD::TRUNCATE && 2333 (!TLI.isZExtFree(VT, Op0VT) || 2334 !TLI.isTruncateFree(Op0VT, VT)) && 2335 TLI.isTypeLegal(Op0VT))) && 2336 !VT.isVector() && 2337 Op0VT == N1.getOperand(0).getValueType() && 2338 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) { 2339 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2340 N0.getOperand(0).getValueType(), 2341 N0.getOperand(0), N1.getOperand(0)); 2342 AddToWorkList(ORNode.getNode()); 2343 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 2344 } 2345 2346 // For each of OP in SHL/SRL/SRA/AND... 2347 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 2348 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 2349 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 2350 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 2351 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 2352 N0.getOperand(1) == N1.getOperand(1)) { 2353 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2354 N0.getOperand(0).getValueType(), 2355 N0.getOperand(0), N1.getOperand(0)); 2356 AddToWorkList(ORNode.getNode()); 2357 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 2358 ORNode, N0.getOperand(1)); 2359 } 2360 2361 // Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B)) 2362 // Only perform this optimization after type legalization and before 2363 // LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by 2364 // adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and 2365 // we don't want to undo this promotion. 2366 // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper 2367 // on scalars. 2368 if ((N0.getOpcode() == ISD::BITCAST || 2369 N0.getOpcode() == ISD::SCALAR_TO_VECTOR) && 2370 Level == AfterLegalizeTypes) { 2371 SDValue In0 = N0.getOperand(0); 2372 SDValue In1 = N1.getOperand(0); 2373 EVT In0Ty = In0.getValueType(); 2374 EVT In1Ty = In1.getValueType(); 2375 DebugLoc DL = N->getDebugLoc(); 2376 // If both incoming values are integers, and the original types are the 2377 // same. 2378 if (In0Ty.isInteger() && In1Ty.isInteger() && In0Ty == In1Ty) { 2379 SDValue Op = DAG.getNode(N->getOpcode(), DL, In0Ty, In0, In1); 2380 SDValue BC = DAG.getNode(N0.getOpcode(), DL, VT, Op); 2381 AddToWorkList(Op.getNode()); 2382 return BC; 2383 } 2384 } 2385 2386 // Xor/and/or are indifferent to the swizzle operation (shuffle of one value). 2387 // Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B)) 2388 // If both shuffles use the same mask, and both shuffle within a single 2389 // vector, then it is worthwhile to move the swizzle after the operation. 2390 // The type-legalizer generates this pattern when loading illegal 2391 // vector types from memory. In many cases this allows additional shuffle 2392 // optimizations. 2393 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG && 2394 N0.getOperand(1).getOpcode() == ISD::UNDEF && 2395 N1.getOperand(1).getOpcode() == ISD::UNDEF) { 2396 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(N0); 2397 ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(N1); 2398 2399 assert(N0.getOperand(0).getValueType() == N1.getOperand(1).getValueType() && 2400 "Inputs to shuffles are not the same type"); 2401 2402 unsigned NumElts = VT.getVectorNumElements(); 2403 2404 // Check that both shuffles use the same mask. The masks are known to be of 2405 // the same length because the result vector type is the same. 2406 bool SameMask = true; 2407 for (unsigned i = 0; i != NumElts; ++i) { 2408 int Idx0 = SVN0->getMaskElt(i); 2409 int Idx1 = SVN1->getMaskElt(i); 2410 if (Idx0 != Idx1) { 2411 SameMask = false; 2412 break; 2413 } 2414 } 2415 2416 if (SameMask) { 2417 SDValue Op = DAG.getNode(N->getOpcode(), N->getDebugLoc(), VT, 2418 N0.getOperand(0), N1.getOperand(0)); 2419 AddToWorkList(Op.getNode()); 2420 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Op, 2421 DAG.getUNDEF(VT), &SVN0->getMask()[0]); 2422 } 2423 } 2424 2425 return SDValue(); 2426} 2427 2428SDValue DAGCombiner::visitAND(SDNode *N) { 2429 SDValue N0 = N->getOperand(0); 2430 SDValue N1 = N->getOperand(1); 2431 SDValue LL, LR, RL, RR, CC0, CC1; 2432 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2433 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2434 EVT VT = N1.getValueType(); 2435 unsigned BitWidth = VT.getScalarType().getSizeInBits(); 2436 2437 // fold vector ops 2438 if (VT.isVector()) { 2439 SDValue FoldedVOp = SimplifyVBinOp(N); 2440 if (FoldedVOp.getNode()) return FoldedVOp; 2441 2442 // fold (and x, 0) -> 0, vector edition 2443 if (ISD::isBuildVectorAllZeros(N0.getNode())) 2444 return N0; 2445 if (ISD::isBuildVectorAllZeros(N1.getNode())) 2446 return N1; 2447 2448 // fold (and x, -1) -> x, vector edition 2449 if (ISD::isBuildVectorAllOnes(N0.getNode())) 2450 return N1; 2451 if (ISD::isBuildVectorAllOnes(N1.getNode())) 2452 return N0; 2453 } 2454 2455 // fold (and x, undef) -> 0 2456 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2457 return DAG.getConstant(0, VT); 2458 // fold (and c1, c2) -> c1&c2 2459 if (N0C && N1C) 2460 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 2461 // canonicalize constant to RHS 2462 if (N0C && !N1C) 2463 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 2464 // fold (and x, -1) -> x 2465 if (N1C && N1C->isAllOnesValue()) 2466 return N0; 2467 // if (and x, c) is known to be zero, return 0 2468 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2469 APInt::getAllOnesValue(BitWidth))) 2470 return DAG.getConstant(0, VT); 2471 // reassociate and 2472 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 2473 if (RAND.getNode() != 0) 2474 return RAND; 2475 // fold (and (or x, C), D) -> D if (C & D) == D 2476 if (N1C && N0.getOpcode() == ISD::OR) 2477 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2478 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 2479 return N1; 2480 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 2481 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2482 SDValue N0Op0 = N0.getOperand(0); 2483 APInt Mask = ~N1C->getAPIntValue(); 2484 Mask = Mask.trunc(N0Op0.getValueSizeInBits()); 2485 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 2486 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 2487 N0.getValueType(), N0Op0); 2488 2489 // Replace uses of the AND with uses of the Zero extend node. 2490 CombineTo(N, Zext); 2491 2492 // We actually want to replace all uses of the any_extend with the 2493 // zero_extend, to avoid duplicating things. This will later cause this 2494 // AND to be folded. 2495 CombineTo(N0.getNode(), Zext); 2496 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2497 } 2498 } 2499 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) -> 2500 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must 2501 // already be zero by virtue of the width of the base type of the load. 2502 // 2503 // the 'X' node here can either be nothing or an extract_vector_elt to catch 2504 // more cases. 2505 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && 2506 N0.getOperand(0).getOpcode() == ISD::LOAD) || 2507 N0.getOpcode() == ISD::LOAD) { 2508 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ? 2509 N0 : N0.getOperand(0) ); 2510 2511 // Get the constant (if applicable) the zero'th operand is being ANDed with. 2512 // This can be a pure constant or a vector splat, in which case we treat the 2513 // vector as a scalar and use the splat value. 2514 APInt Constant = APInt::getNullValue(1); 2515 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { 2516 Constant = C->getAPIntValue(); 2517 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) { 2518 APInt SplatValue, SplatUndef; 2519 unsigned SplatBitSize; 2520 bool HasAnyUndefs; 2521 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef, 2522 SplatBitSize, HasAnyUndefs); 2523 if (IsSplat) { 2524 // Undef bits can contribute to a possible optimisation if set, so 2525 // set them. 2526 SplatValue |= SplatUndef; 2527 2528 // The splat value may be something like "0x00FFFFFF", which means 0 for 2529 // the first vector value and FF for the rest, repeating. We need a mask 2530 // that will apply equally to all members of the vector, so AND all the 2531 // lanes of the constant together. 2532 EVT VT = Vector->getValueType(0); 2533 unsigned BitWidth = VT.getVectorElementType().getSizeInBits(); 2534 2535 // If the splat value has been compressed to a bitlength lower 2536 // than the size of the vector lane, we need to re-expand it to 2537 // the lane size. 2538 if (BitWidth > SplatBitSize) 2539 for (SplatValue = SplatValue.zextOrTrunc(BitWidth); 2540 SplatBitSize < BitWidth; 2541 SplatBitSize = SplatBitSize * 2) 2542 SplatValue |= SplatValue.shl(SplatBitSize); 2543 2544 Constant = APInt::getAllOnesValue(BitWidth); 2545 for (unsigned i = 0, n = SplatBitSize/BitWidth; i < n; ++i) 2546 Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth); 2547 } 2548 } 2549 2550 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is 2551 // actually legal and isn't going to get expanded, else this is a false 2552 // optimisation. 2553 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD, 2554 Load->getMemoryVT()); 2555 2556 // Resize the constant to the same size as the original memory access before 2557 // extension. If it is still the AllOnesValue then this AND is completely 2558 // unneeded. 2559 Constant = 2560 Constant.zextOrTrunc(Load->getMemoryVT().getScalarType().getSizeInBits()); 2561 2562 bool B; 2563 switch (Load->getExtensionType()) { 2564 default: B = false; break; 2565 case ISD::EXTLOAD: B = CanZextLoadProfitably; break; 2566 case ISD::ZEXTLOAD: 2567 case ISD::NON_EXTLOAD: B = true; break; 2568 } 2569 2570 if (B && Constant.isAllOnesValue()) { 2571 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to 2572 // preserve semantics once we get rid of the AND. 2573 SDValue NewLoad(Load, 0); 2574 if (Load->getExtensionType() == ISD::EXTLOAD) { 2575 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD, 2576 Load->getValueType(0), Load->getDebugLoc(), 2577 Load->getChain(), Load->getBasePtr(), 2578 Load->getOffset(), Load->getMemoryVT(), 2579 Load->getMemOperand()); 2580 // Replace uses of the EXTLOAD with the new ZEXTLOAD. 2581 if (Load->getNumValues() == 3) { 2582 // PRE/POST_INC loads have 3 values. 2583 SDValue To[] = { NewLoad.getValue(0), NewLoad.getValue(1), 2584 NewLoad.getValue(2) }; 2585 CombineTo(Load, To, 3, true); 2586 } else { 2587 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1)); 2588 } 2589 } 2590 2591 // Fold the AND away, taking care not to fold to the old load node if we 2592 // replaced it. 2593 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0); 2594 2595 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2596 } 2597 } 2598 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 2599 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2600 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2601 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2602 2603 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2604 LL.getValueType().isInteger()) { 2605 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 2606 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 2607 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2608 LR.getValueType(), LL, RL); 2609 AddToWorkList(ORNode.getNode()); 2610 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2611 } 2612 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 2613 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 2614 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 2615 LR.getValueType(), LL, RL); 2616 AddToWorkList(ANDNode.getNode()); 2617 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2618 } 2619 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 2620 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 2621 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2622 LR.getValueType(), LL, RL); 2623 AddToWorkList(ORNode.getNode()); 2624 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2625 } 2626 } 2627 // canonicalize equivalent to ll == rl 2628 if (LL == RR && LR == RL) { 2629 Op1 = ISD::getSetCCSwappedOperands(Op1); 2630 std::swap(RL, RR); 2631 } 2632 if (LL == RL && LR == RR) { 2633 bool isInteger = LL.getValueType().isInteger(); 2634 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 2635 if (Result != ISD::SETCC_INVALID && 2636 (!LegalOperations || 2637 (TLI.isCondCodeLegal(Result, LL.getSimpleValueType()) && 2638 TLI.isOperationLegal(ISD::SETCC, 2639 TLI.getSetCCResultType(N0.getSimpleValueType()))))) 2640 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2641 LL, LR, Result); 2642 } 2643 } 2644 2645 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 2646 if (N0.getOpcode() == N1.getOpcode()) { 2647 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2648 if (Tmp.getNode()) return Tmp; 2649 } 2650 2651 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 2652 // fold (and (sra)) -> (and (srl)) when possible. 2653 if (!VT.isVector() && 2654 SimplifyDemandedBits(SDValue(N, 0))) 2655 return SDValue(N, 0); 2656 2657 // fold (zext_inreg (extload x)) -> (zextload x) 2658 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 2659 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2660 EVT MemVT = LN0->getMemoryVT(); 2661 // If we zero all the possible extended bits, then we can turn this into 2662 // a zextload if we are running before legalize or the operation is legal. 2663 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2664 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2665 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2666 ((!LegalOperations && !LN0->isVolatile()) || 2667 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2668 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2669 LN0->getChain(), LN0->getBasePtr(), 2670 LN0->getPointerInfo(), MemVT, 2671 LN0->isVolatile(), LN0->isNonTemporal(), 2672 LN0->getAlignment()); 2673 AddToWorkList(N); 2674 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2675 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2676 } 2677 } 2678 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 2679 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 2680 N0.hasOneUse()) { 2681 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2682 EVT MemVT = LN0->getMemoryVT(); 2683 // If we zero all the possible extended bits, then we can turn this into 2684 // a zextload if we are running before legalize or the operation is legal. 2685 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2686 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2687 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2688 ((!LegalOperations && !LN0->isVolatile()) || 2689 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2690 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2691 LN0->getChain(), 2692 LN0->getBasePtr(), LN0->getPointerInfo(), 2693 MemVT, 2694 LN0->isVolatile(), LN0->isNonTemporal(), 2695 LN0->getAlignment()); 2696 AddToWorkList(N); 2697 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2698 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2699 } 2700 } 2701 2702 // fold (and (load x), 255) -> (zextload x, i8) 2703 // fold (and (extload x, i16), 255) -> (zextload x, i8) 2704 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8) 2705 if (N1C && (N0.getOpcode() == ISD::LOAD || 2706 (N0.getOpcode() == ISD::ANY_EXTEND && 2707 N0.getOperand(0).getOpcode() == ISD::LOAD))) { 2708 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; 2709 LoadSDNode *LN0 = HasAnyExt 2710 ? cast<LoadSDNode>(N0.getOperand(0)) 2711 : cast<LoadSDNode>(N0); 2712 if (LN0->getExtensionType() != ISD::SEXTLOAD && 2713 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) { 2714 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 2715 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){ 2716 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); 2717 EVT LoadedVT = LN0->getMemoryVT(); 2718 2719 if (ExtVT == LoadedVT && 2720 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2721 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2722 2723 SDValue NewLoad = 2724 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2725 LN0->getChain(), LN0->getBasePtr(), 2726 LN0->getPointerInfo(), 2727 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2728 LN0->getAlignment()); 2729 AddToWorkList(N); 2730 CombineTo(LN0, NewLoad, NewLoad.getValue(1)); 2731 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2732 } 2733 2734 // Do not change the width of a volatile load. 2735 // Do not generate loads of non-round integer types since these can 2736 // be expensive (and would be wrong if the type is not byte sized). 2737 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && 2738 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2739 EVT PtrType = LN0->getOperand(1).getValueType(); 2740 2741 unsigned Alignment = LN0->getAlignment(); 2742 SDValue NewPtr = LN0->getBasePtr(); 2743 2744 // For big endian targets, we need to add an offset to the pointer 2745 // to load the correct bytes. For little endian systems, we merely 2746 // need to read fewer bytes from the same pointer. 2747 if (TLI.isBigEndian()) { 2748 unsigned LVTStoreBytes = LoadedVT.getStoreSize(); 2749 unsigned EVTStoreBytes = ExtVT.getStoreSize(); 2750 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 2751 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 2752 NewPtr, DAG.getConstant(PtrOff, PtrType)); 2753 Alignment = MinAlign(Alignment, PtrOff); 2754 } 2755 2756 AddToWorkList(NewPtr.getNode()); 2757 2758 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2759 SDValue Load = 2760 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2761 LN0->getChain(), NewPtr, 2762 LN0->getPointerInfo(), 2763 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2764 Alignment); 2765 AddToWorkList(N); 2766 CombineTo(LN0, Load, Load.getValue(1)); 2767 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2768 } 2769 } 2770 } 2771 } 2772 2773 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL && 2774 VT.getSizeInBits() <= 64) { 2775 if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2776 APInt ADDC = ADDI->getAPIntValue(); 2777 if (!TLI.isLegalAddImmediate(ADDC.getSExtValue())) { 2778 // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal 2779 // immediate for an add, but it is legal if its top c2 bits are set, 2780 // transform the ADD so the immediate doesn't need to be materialized 2781 // in a register. 2782 if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 2783 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 2784 SRLI->getZExtValue()); 2785 if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) { 2786 ADDC |= Mask; 2787 if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) { 2788 SDValue NewAdd = 2789 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 2790 N0.getOperand(0), DAG.getConstant(ADDC, VT)); 2791 CombineTo(N0.getNode(), NewAdd); 2792 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2793 } 2794 } 2795 } 2796 } 2797 } 2798 } 2799 2800 return SDValue(); 2801} 2802 2803/// MatchBSwapHWord - Match (a >> 8) | (a << 8) as (bswap a) >> 16 2804/// 2805SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, 2806 bool DemandHighBits) { 2807 if (!LegalOperations) 2808 return SDValue(); 2809 2810 EVT VT = N->getValueType(0); 2811 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16) 2812 return SDValue(); 2813 if (!TLI.isOperationLegal(ISD::BSWAP, VT)) 2814 return SDValue(); 2815 2816 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00) 2817 bool LookPassAnd0 = false; 2818 bool LookPassAnd1 = false; 2819 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL) 2820 std::swap(N0, N1); 2821 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL) 2822 std::swap(N0, N1); 2823 if (N0.getOpcode() == ISD::AND) { 2824 if (!N0.getNode()->hasOneUse()) 2825 return SDValue(); 2826 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2827 if (!N01C || N01C->getZExtValue() != 0xFF00) 2828 return SDValue(); 2829 N0 = N0.getOperand(0); 2830 LookPassAnd0 = true; 2831 } 2832 2833 if (N1.getOpcode() == ISD::AND) { 2834 if (!N1.getNode()->hasOneUse()) 2835 return SDValue(); 2836 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 2837 if (!N11C || N11C->getZExtValue() != 0xFF) 2838 return SDValue(); 2839 N1 = N1.getOperand(0); 2840 LookPassAnd1 = true; 2841 } 2842 2843 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 2844 std::swap(N0, N1); 2845 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 2846 return SDValue(); 2847 if (!N0.getNode()->hasOneUse() || 2848 !N1.getNode()->hasOneUse()) 2849 return SDValue(); 2850 2851 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2852 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 2853 if (!N01C || !N11C) 2854 return SDValue(); 2855 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8) 2856 return SDValue(); 2857 2858 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8) 2859 SDValue N00 = N0->getOperand(0); 2860 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) { 2861 if (!N00.getNode()->hasOneUse()) 2862 return SDValue(); 2863 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1)); 2864 if (!N001C || N001C->getZExtValue() != 0xFF) 2865 return SDValue(); 2866 N00 = N00.getOperand(0); 2867 LookPassAnd0 = true; 2868 } 2869 2870 SDValue N10 = N1->getOperand(0); 2871 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) { 2872 if (!N10.getNode()->hasOneUse()) 2873 return SDValue(); 2874 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1)); 2875 if (!N101C || N101C->getZExtValue() != 0xFF00) 2876 return SDValue(); 2877 N10 = N10.getOperand(0); 2878 LookPassAnd1 = true; 2879 } 2880 2881 if (N00 != N10) 2882 return SDValue(); 2883 2884 // Make sure everything beyond the low halfword is zero since the SRL 16 2885 // will clear the top bits. 2886 unsigned OpSizeInBits = VT.getSizeInBits(); 2887 if (DemandHighBits && OpSizeInBits > 16 && 2888 (!LookPassAnd0 || !LookPassAnd1) && 2889 !DAG.MaskedValueIsZero(N10, APInt::getHighBitsSet(OpSizeInBits, 16))) 2890 return SDValue(); 2891 2892 SDValue Res = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, N00); 2893 if (OpSizeInBits > 16) 2894 Res = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Res, 2895 DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT))); 2896 return Res; 2897} 2898 2899/// isBSwapHWordElement - Return true if the specified node is an element 2900/// that makes up a 32-bit packed halfword byteswap. i.e. 2901/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8) 2902static bool isBSwapHWordElement(SDValue N, SmallVector<SDNode*,4> &Parts) { 2903 if (!N.getNode()->hasOneUse()) 2904 return false; 2905 2906 unsigned Opc = N.getOpcode(); 2907 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL) 2908 return false; 2909 2910 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2911 if (!N1C) 2912 return false; 2913 2914 unsigned Num; 2915 switch (N1C->getZExtValue()) { 2916 default: 2917 return false; 2918 case 0xFF: Num = 0; break; 2919 case 0xFF00: Num = 1; break; 2920 case 0xFF0000: Num = 2; break; 2921 case 0xFF000000: Num = 3; break; 2922 } 2923 2924 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00). 2925 SDValue N0 = N.getOperand(0); 2926 if (Opc == ISD::AND) { 2927 if (Num == 0 || Num == 2) { 2928 // (x >> 8) & 0xff 2929 // (x >> 8) & 0xff0000 2930 if (N0.getOpcode() != ISD::SRL) 2931 return false; 2932 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2933 if (!C || C->getZExtValue() != 8) 2934 return false; 2935 } else { 2936 // (x << 8) & 0xff00 2937 // (x << 8) & 0xff000000 2938 if (N0.getOpcode() != ISD::SHL) 2939 return false; 2940 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2941 if (!C || C->getZExtValue() != 8) 2942 return false; 2943 } 2944 } else if (Opc == ISD::SHL) { 2945 // (x & 0xff) << 8 2946 // (x & 0xff0000) << 8 2947 if (Num != 0 && Num != 2) 2948 return false; 2949 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2950 if (!C || C->getZExtValue() != 8) 2951 return false; 2952 } else { // Opc == ISD::SRL 2953 // (x & 0xff00) >> 8 2954 // (x & 0xff000000) >> 8 2955 if (Num != 1 && Num != 3) 2956 return false; 2957 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2958 if (!C || C->getZExtValue() != 8) 2959 return false; 2960 } 2961 2962 if (Parts[Num]) 2963 return false; 2964 2965 Parts[Num] = N0.getOperand(0).getNode(); 2966 return true; 2967} 2968 2969/// MatchBSwapHWord - Match a 32-bit packed halfword bswap. That is 2970/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8) 2971/// => (rotl (bswap x), 16) 2972SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) { 2973 if (!LegalOperations) 2974 return SDValue(); 2975 2976 EVT VT = N->getValueType(0); 2977 if (VT != MVT::i32) 2978 return SDValue(); 2979 if (!TLI.isOperationLegal(ISD::BSWAP, VT)) 2980 return SDValue(); 2981 2982 SmallVector<SDNode*,4> Parts(4, (SDNode*)0); 2983 // Look for either 2984 // (or (or (and), (and)), (or (and), (and))) 2985 // (or (or (or (and), (and)), (and)), (and)) 2986 if (N0.getOpcode() != ISD::OR) 2987 return SDValue(); 2988 SDValue N00 = N0.getOperand(0); 2989 SDValue N01 = N0.getOperand(1); 2990 2991 if (N1.getOpcode() == ISD::OR && 2992 N00.getNumOperands() == 2 && N01.getNumOperands() == 2) { 2993 // (or (or (and), (and)), (or (and), (and))) 2994 SDValue N000 = N00.getOperand(0); 2995 if (!isBSwapHWordElement(N000, Parts)) 2996 return SDValue(); 2997 2998 SDValue N001 = N00.getOperand(1); 2999 if (!isBSwapHWordElement(N001, Parts)) 3000 return SDValue(); 3001 SDValue N010 = N01.getOperand(0); 3002 if (!isBSwapHWordElement(N010, Parts)) 3003 return SDValue(); 3004 SDValue N011 = N01.getOperand(1); 3005 if (!isBSwapHWordElement(N011, Parts)) 3006 return SDValue(); 3007 } else { 3008 // (or (or (or (and), (and)), (and)), (and)) 3009 if (!isBSwapHWordElement(N1, Parts)) 3010 return SDValue(); 3011 if (!isBSwapHWordElement(N01, Parts)) 3012 return SDValue(); 3013 if (N00.getOpcode() != ISD::OR) 3014 return SDValue(); 3015 SDValue N000 = N00.getOperand(0); 3016 if (!isBSwapHWordElement(N000, Parts)) 3017 return SDValue(); 3018 SDValue N001 = N00.getOperand(1); 3019 if (!isBSwapHWordElement(N001, Parts)) 3020 return SDValue(); 3021 } 3022 3023 // Make sure the parts are all coming from the same node. 3024 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3]) 3025 return SDValue(); 3026 3027 SDValue BSwap = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, 3028 SDValue(Parts[0],0)); 3029 3030 // Result of the bswap should be rotated by 16. If it's not legal, than 3031 // do (x << 16) | (x >> 16). 3032 SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT)); 3033 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT)) 3034 return DAG.getNode(ISD::ROTL, N->getDebugLoc(), VT, BSwap, ShAmt); 3035 if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT)) 3036 return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, BSwap, ShAmt); 3037 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, 3038 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, BSwap, ShAmt), 3039 DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, BSwap, ShAmt)); 3040} 3041 3042SDValue DAGCombiner::visitOR(SDNode *N) { 3043 SDValue N0 = N->getOperand(0); 3044 SDValue N1 = N->getOperand(1); 3045 SDValue LL, LR, RL, RR, CC0, CC1; 3046 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3047 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3048 EVT VT = N1.getValueType(); 3049 3050 // fold vector ops 3051 if (VT.isVector()) { 3052 SDValue FoldedVOp = SimplifyVBinOp(N); 3053 if (FoldedVOp.getNode()) return FoldedVOp; 3054 3055 // fold (or x, 0) -> x, vector edition 3056 if (ISD::isBuildVectorAllZeros(N0.getNode())) 3057 return N1; 3058 if (ISD::isBuildVectorAllZeros(N1.getNode())) 3059 return N0; 3060 3061 // fold (or x, -1) -> -1, vector edition 3062 if (ISD::isBuildVectorAllOnes(N0.getNode())) 3063 return N0; 3064 if (ISD::isBuildVectorAllOnes(N1.getNode())) 3065 return N1; 3066 } 3067 3068 // fold (or x, undef) -> -1 3069 if (!LegalOperations && 3070 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) { 3071 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 3072 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 3073 } 3074 // fold (or c1, c2) -> c1|c2 3075 if (N0C && N1C) 3076 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 3077 // canonicalize constant to RHS 3078 if (N0C && !N1C) 3079 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 3080 // fold (or x, 0) -> x 3081 if (N1C && N1C->isNullValue()) 3082 return N0; 3083 // fold (or x, -1) -> -1 3084 if (N1C && N1C->isAllOnesValue()) 3085 return N1; 3086 // fold (or x, c) -> c iff (x & ~c) == 0 3087 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 3088 return N1; 3089 3090 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16) 3091 SDValue BSwap = MatchBSwapHWord(N, N0, N1); 3092 if (BSwap.getNode() != 0) 3093 return BSwap; 3094 BSwap = MatchBSwapHWordLow(N, N0, N1); 3095 if (BSwap.getNode() != 0) 3096 return BSwap; 3097 3098 // reassociate or 3099 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 3100 if (ROR.getNode() != 0) 3101 return ROR; 3102 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 3103 // iff (c1 & c2) == 0. 3104 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 3105 isa<ConstantSDNode>(N0.getOperand(1))) { 3106 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 3107 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) 3108 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3109 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 3110 N0.getOperand(0), N1), 3111 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 3112 } 3113 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 3114 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 3115 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 3116 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 3117 3118 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 3119 LL.getValueType().isInteger()) { 3120 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 3121 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 3122 if (cast<ConstantSDNode>(LR)->isNullValue() && 3123 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 3124 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 3125 LR.getValueType(), LL, RL); 3126 AddToWorkList(ORNode.getNode()); 3127 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 3128 } 3129 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 3130 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 3131 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 3132 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 3133 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 3134 LR.getValueType(), LL, RL); 3135 AddToWorkList(ANDNode.getNode()); 3136 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 3137 } 3138 } 3139 // canonicalize equivalent to ll == rl 3140 if (LL == RR && LR == RL) { 3141 Op1 = ISD::getSetCCSwappedOperands(Op1); 3142 std::swap(RL, RR); 3143 } 3144 if (LL == RL && LR == RR) { 3145 bool isInteger = LL.getValueType().isInteger(); 3146 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 3147 if (Result != ISD::SETCC_INVALID && 3148 (!LegalOperations || 3149 (TLI.isCondCodeLegal(Result, LL.getSimpleValueType()) && 3150 TLI.isOperationLegal(ISD::SETCC, 3151 TLI.getSetCCResultType(N0.getValueType()))))) 3152 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 3153 LL, LR, Result); 3154 } 3155 } 3156 3157 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 3158 if (N0.getOpcode() == N1.getOpcode()) { 3159 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 3160 if (Tmp.getNode()) return Tmp; 3161 } 3162 3163 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 3164 if (N0.getOpcode() == ISD::AND && 3165 N1.getOpcode() == ISD::AND && 3166 N0.getOperand(1).getOpcode() == ISD::Constant && 3167 N1.getOperand(1).getOpcode() == ISD::Constant && 3168 // Don't increase # computations. 3169 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 3170 // We can only do this xform if we know that bits from X that are set in C2 3171 // but not in C1 are already zero. Likewise for Y. 3172 const APInt &LHSMask = 3173 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3174 const APInt &RHSMask = 3175 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 3176 3177 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 3178 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 3179 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 3180 N0.getOperand(0), N1.getOperand(0)); 3181 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 3182 DAG.getConstant(LHSMask | RHSMask, VT)); 3183 } 3184 } 3185 3186 // See if this is some rotate idiom. 3187 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 3188 return SDValue(Rot, 0); 3189 3190 // Simplify the operands using demanded-bits information. 3191 if (!VT.isVector() && 3192 SimplifyDemandedBits(SDValue(N, 0))) 3193 return SDValue(N, 0); 3194 3195 return SDValue(); 3196} 3197 3198/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 3199static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 3200 if (Op.getOpcode() == ISD::AND) { 3201 if (isa<ConstantSDNode>(Op.getOperand(1))) { 3202 Mask = Op.getOperand(1); 3203 Op = Op.getOperand(0); 3204 } else { 3205 return false; 3206 } 3207 } 3208 3209 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 3210 Shift = Op; 3211 return true; 3212 } 3213 3214 return false; 3215} 3216 3217// MatchRotate - Handle an 'or' of two operands. If this is one of the many 3218// idioms for rotate, and if the target supports rotation instructions, generate 3219// a rot[lr]. 3220SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 3221 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 3222 EVT VT = LHS.getValueType(); 3223 if (!TLI.isTypeLegal(VT)) return 0; 3224 3225 // The target must have at least one rotate flavor. 3226 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 3227 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 3228 if (!HasROTL && !HasROTR) return 0; 3229 3230 // Match "(X shl/srl V1) & V2" where V2 may not be present. 3231 SDValue LHSShift; // The shift. 3232 SDValue LHSMask; // AND value if any. 3233 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 3234 return 0; // Not part of a rotate. 3235 3236 SDValue RHSShift; // The shift. 3237 SDValue RHSMask; // AND value if any. 3238 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 3239 return 0; // Not part of a rotate. 3240 3241 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 3242 return 0; // Not shifting the same value. 3243 3244 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 3245 return 0; // Shifts must disagree. 3246 3247 // Canonicalize shl to left side in a shl/srl pair. 3248 if (RHSShift.getOpcode() == ISD::SHL) { 3249 std::swap(LHS, RHS); 3250 std::swap(LHSShift, RHSShift); 3251 std::swap(LHSMask , RHSMask ); 3252 } 3253 3254 unsigned OpSizeInBits = VT.getSizeInBits(); 3255 SDValue LHSShiftArg = LHSShift.getOperand(0); 3256 SDValue LHSShiftAmt = LHSShift.getOperand(1); 3257 SDValue RHSShiftAmt = RHSShift.getOperand(1); 3258 3259 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 3260 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 3261 if (LHSShiftAmt.getOpcode() == ISD::Constant && 3262 RHSShiftAmt.getOpcode() == ISD::Constant) { 3263 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 3264 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 3265 if ((LShVal + RShVal) != OpSizeInBits) 3266 return 0; 3267 3268 SDValue Rot = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 3269 LHSShiftArg, HasROTL ? LHSShiftAmt : RHSShiftAmt); 3270 3271 // If there is an AND of either shifted operand, apply it to the result. 3272 if (LHSMask.getNode() || RHSMask.getNode()) { 3273 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 3274 3275 if (LHSMask.getNode()) { 3276 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 3277 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 3278 } 3279 if (RHSMask.getNode()) { 3280 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 3281 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 3282 } 3283 3284 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 3285 } 3286 3287 return Rot.getNode(); 3288 } 3289 3290 // If there is a mask here, and we have a variable shift, we can't be sure 3291 // that we're masking out the right stuff. 3292 if (LHSMask.getNode() || RHSMask.getNode()) 3293 return 0; 3294 3295 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 3296 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 3297 if (RHSShiftAmt.getOpcode() == ISD::SUB && 3298 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 3299 if (ConstantSDNode *SUBC = 3300 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 3301 if (SUBC->getAPIntValue() == OpSizeInBits) { 3302 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, LHSShiftArg, 3303 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 3304 } 3305 } 3306 } 3307 3308 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 3309 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 3310 if (LHSShiftAmt.getOpcode() == ISD::SUB && 3311 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 3312 if (ConstantSDNode *SUBC = 3313 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 3314 if (SUBC->getAPIntValue() == OpSizeInBits) { 3315 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, LHSShiftArg, 3316 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 3317 } 3318 } 3319 } 3320 3321 // Look for sign/zext/any-extended or truncate cases: 3322 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND || 3323 LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND || 3324 LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND || 3325 LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 3326 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND || 3327 RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND || 3328 RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND || 3329 RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 3330 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 3331 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 3332 if (RExtOp0.getOpcode() == ISD::SUB && 3333 RExtOp0.getOperand(1) == LExtOp0) { 3334 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 3335 // (rotl x, y) 3336 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 3337 // (rotr x, (sub 32, y)) 3338 if (ConstantSDNode *SUBC = 3339 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 3340 if (SUBC->getAPIntValue() == OpSizeInBits) { 3341 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 3342 LHSShiftArg, 3343 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 3344 } 3345 } 3346 } else if (LExtOp0.getOpcode() == ISD::SUB && 3347 RExtOp0 == LExtOp0.getOperand(1)) { 3348 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 3349 // (rotr x, y) 3350 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 3351 // (rotl x, (sub 32, y)) 3352 if (ConstantSDNode *SUBC = 3353 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 3354 if (SUBC->getAPIntValue() == OpSizeInBits) { 3355 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 3356 LHSShiftArg, 3357 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 3358 } 3359 } 3360 } 3361 } 3362 3363 return 0; 3364} 3365 3366SDValue DAGCombiner::visitXOR(SDNode *N) { 3367 SDValue N0 = N->getOperand(0); 3368 SDValue N1 = N->getOperand(1); 3369 SDValue LHS, RHS, CC; 3370 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3371 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3372 EVT VT = N0.getValueType(); 3373 3374 // fold vector ops 3375 if (VT.isVector()) { 3376 SDValue FoldedVOp = SimplifyVBinOp(N); 3377 if (FoldedVOp.getNode()) return FoldedVOp; 3378 3379 // fold (xor x, 0) -> x, vector edition 3380 if (ISD::isBuildVectorAllZeros(N0.getNode())) 3381 return N1; 3382 if (ISD::isBuildVectorAllZeros(N1.getNode())) 3383 return N0; 3384 } 3385 3386 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 3387 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 3388 return DAG.getConstant(0, VT); 3389 // fold (xor x, undef) -> undef 3390 if (N0.getOpcode() == ISD::UNDEF) 3391 return N0; 3392 if (N1.getOpcode() == ISD::UNDEF) 3393 return N1; 3394 // fold (xor c1, c2) -> c1^c2 3395 if (N0C && N1C) 3396 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 3397 // canonicalize constant to RHS 3398 if (N0C && !N1C) 3399 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 3400 // fold (xor x, 0) -> x 3401 if (N1C && N1C->isNullValue()) 3402 return N0; 3403 // reassociate xor 3404 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 3405 if (RXOR.getNode() != 0) 3406 return RXOR; 3407 3408 // fold !(x cc y) -> (x !cc y) 3409 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 3410 bool isInt = LHS.getValueType().isInteger(); 3411 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 3412 isInt); 3413 3414 if (!LegalOperations || 3415 TLI.isCondCodeLegal(NotCC, LHS.getSimpleValueType())) { 3416 switch (N0.getOpcode()) { 3417 default: 3418 llvm_unreachable("Unhandled SetCC Equivalent!"); 3419 case ISD::SETCC: 3420 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 3421 case ISD::SELECT_CC: 3422 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 3423 N0.getOperand(3), NotCC); 3424 } 3425 } 3426 } 3427 3428 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 3429 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 3430 N0.getNode()->hasOneUse() && 3431 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 3432 SDValue V = N0.getOperand(0); 3433 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 3434 DAG.getConstant(1, V.getValueType())); 3435 AddToWorkList(V.getNode()); 3436 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 3437 } 3438 3439 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 3440 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 3441 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 3442 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 3443 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 3444 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 3445 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 3446 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 3447 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 3448 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 3449 } 3450 } 3451 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 3452 if (N1C && N1C->isAllOnesValue() && 3453 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 3454 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 3455 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 3456 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 3457 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 3458 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 3459 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 3460 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 3461 } 3462 } 3463 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 3464 if (N1C && N0.getOpcode() == ISD::XOR) { 3465 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 3466 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3467 if (N00C) 3468 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 3469 DAG.getConstant(N1C->getAPIntValue() ^ 3470 N00C->getAPIntValue(), VT)); 3471 if (N01C) 3472 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 3473 DAG.getConstant(N1C->getAPIntValue() ^ 3474 N01C->getAPIntValue(), VT)); 3475 } 3476 // fold (xor x, x) -> 0 3477 if (N0 == N1) 3478 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 3479 3480 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 3481 if (N0.getOpcode() == N1.getOpcode()) { 3482 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 3483 if (Tmp.getNode()) return Tmp; 3484 } 3485 3486 // Simplify the expression using non-local knowledge. 3487 if (!VT.isVector() && 3488 SimplifyDemandedBits(SDValue(N, 0))) 3489 return SDValue(N, 0); 3490 3491 return SDValue(); 3492} 3493 3494/// visitShiftByConstant - Handle transforms common to the three shifts, when 3495/// the shift amount is a constant. 3496SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 3497 SDNode *LHS = N->getOperand(0).getNode(); 3498 if (!LHS->hasOneUse()) return SDValue(); 3499 3500 // We want to pull some binops through shifts, so that we have (and (shift)) 3501 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 3502 // thing happens with address calculations, so it's important to canonicalize 3503 // it. 3504 bool HighBitSet = false; // Can we transform this if the high bit is set? 3505 3506 switch (LHS->getOpcode()) { 3507 default: return SDValue(); 3508 case ISD::OR: 3509 case ISD::XOR: 3510 HighBitSet = false; // We can only transform sra if the high bit is clear. 3511 break; 3512 case ISD::AND: 3513 HighBitSet = true; // We can only transform sra if the high bit is set. 3514 break; 3515 case ISD::ADD: 3516 if (N->getOpcode() != ISD::SHL) 3517 return SDValue(); // only shl(add) not sr[al](add). 3518 HighBitSet = false; // We can only transform sra if the high bit is clear. 3519 break; 3520 } 3521 3522 // We require the RHS of the binop to be a constant as well. 3523 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 3524 if (!BinOpCst) return SDValue(); 3525 3526 // FIXME: disable this unless the input to the binop is a shift by a constant. 3527 // If it is not a shift, it pessimizes some common cases like: 3528 // 3529 // void foo(int *X, int i) { X[i & 1235] = 1; } 3530 // int bar(int *X, int i) { return X[i & 255]; } 3531 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 3532 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 3533 BinOpLHSVal->getOpcode() != ISD::SRA && 3534 BinOpLHSVal->getOpcode() != ISD::SRL) || 3535 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 3536 return SDValue(); 3537 3538 EVT VT = N->getValueType(0); 3539 3540 // If this is a signed shift right, and the high bit is modified by the 3541 // logical operation, do not perform the transformation. The highBitSet 3542 // boolean indicates the value of the high bit of the constant which would 3543 // cause it to be modified for this operation. 3544 if (N->getOpcode() == ISD::SRA) { 3545 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 3546 if (BinOpRHSSignSet != HighBitSet) 3547 return SDValue(); 3548 } 3549 3550 // Fold the constants, shifting the binop RHS by the shift amount. 3551 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 3552 N->getValueType(0), 3553 LHS->getOperand(1), N->getOperand(1)); 3554 3555 // Create the new shift. 3556 SDValue NewShift = DAG.getNode(N->getOpcode(), 3557 LHS->getOperand(0).getDebugLoc(), 3558 VT, LHS->getOperand(0), N->getOperand(1)); 3559 3560 // Create the new binop. 3561 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 3562} 3563 3564SDValue DAGCombiner::visitSHL(SDNode *N) { 3565 SDValue N0 = N->getOperand(0); 3566 SDValue N1 = N->getOperand(1); 3567 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3568 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3569 EVT VT = N0.getValueType(); 3570 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3571 3572 // fold (shl c1, c2) -> c1<<c2 3573 if (N0C && N1C) 3574 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 3575 // fold (shl 0, x) -> 0 3576 if (N0C && N0C->isNullValue()) 3577 return N0; 3578 // fold (shl x, c >= size(x)) -> undef 3579 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3580 return DAG.getUNDEF(VT); 3581 // fold (shl x, 0) -> x 3582 if (N1C && N1C->isNullValue()) 3583 return N0; 3584 // fold (shl undef, x) -> 0 3585 if (N0.getOpcode() == ISD::UNDEF) 3586 return DAG.getConstant(0, VT); 3587 // if (shl x, c) is known to be zero, return 0 3588 if (DAG.MaskedValueIsZero(SDValue(N, 0), 3589 APInt::getAllOnesValue(OpSizeInBits))) 3590 return DAG.getConstant(0, VT); 3591 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 3592 if (N1.getOpcode() == ISD::TRUNCATE && 3593 N1.getOperand(0).getOpcode() == ISD::AND && 3594 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3595 SDValue N101 = N1.getOperand(0).getOperand(1); 3596 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3597 EVT TruncVT = N1.getValueType(); 3598 SDValue N100 = N1.getOperand(0).getOperand(0); 3599 APInt TruncC = N101C->getAPIntValue(); 3600 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3601 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 3602 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 3603 DAG.getNode(ISD::TRUNCATE, 3604 N->getDebugLoc(), 3605 TruncVT, N100), 3606 DAG.getConstant(TruncC, TruncVT))); 3607 } 3608 } 3609 3610 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3611 return SDValue(N, 0); 3612 3613 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 3614 if (N1C && N0.getOpcode() == ISD::SHL && 3615 N0.getOperand(1).getOpcode() == ISD::Constant) { 3616 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3617 uint64_t c2 = N1C->getZExtValue(); 3618 if (c1 + c2 >= OpSizeInBits) 3619 return DAG.getConstant(0, VT); 3620 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 3621 DAG.getConstant(c1 + c2, N1.getValueType())); 3622 } 3623 3624 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2))) 3625 // For this to be valid, the second form must not preserve any of the bits 3626 // that are shifted out by the inner shift in the first form. This means 3627 // the outer shift size must be >= the number of bits added by the ext. 3628 // As a corollary, we don't care what kind of ext it is. 3629 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND || 3630 N0.getOpcode() == ISD::ANY_EXTEND || 3631 N0.getOpcode() == ISD::SIGN_EXTEND) && 3632 N0.getOperand(0).getOpcode() == ISD::SHL && 3633 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3634 uint64_t c1 = 3635 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3636 uint64_t c2 = N1C->getZExtValue(); 3637 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3638 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3639 if (c2 >= OpSizeInBits - InnerShiftSize) { 3640 if (c1 + c2 >= OpSizeInBits) 3641 return DAG.getConstant(0, VT); 3642 return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT, 3643 DAG.getNode(N0.getOpcode(), N0->getDebugLoc(), VT, 3644 N0.getOperand(0)->getOperand(0)), 3645 DAG.getConstant(c1 + c2, N1.getValueType())); 3646 } 3647 } 3648 3649 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or 3650 // (and (srl x, (sub c1, c2), MASK) 3651 // Only fold this if the inner shift has no other uses -- if it does, folding 3652 // this will increase the total number of instructions. 3653 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse() && 3654 N0.getOperand(1).getOpcode() == ISD::Constant) { 3655 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3656 if (c1 < VT.getSizeInBits()) { 3657 uint64_t c2 = N1C->getZExtValue(); 3658 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 3659 VT.getSizeInBits() - c1); 3660 SDValue Shift; 3661 if (c2 > c1) { 3662 Mask = Mask.shl(c2-c1); 3663 Shift = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 3664 DAG.getConstant(c2-c1, N1.getValueType())); 3665 } else { 3666 Mask = Mask.lshr(c1-c2); 3667 Shift = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3668 DAG.getConstant(c1-c2, N1.getValueType())); 3669 } 3670 return DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, Shift, 3671 DAG.getConstant(Mask, VT)); 3672 } 3673 } 3674 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 3675 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { 3676 SDValue HiBitsMask = 3677 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 3678 VT.getSizeInBits() - 3679 N1C->getZExtValue()), 3680 VT); 3681 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3682 HiBitsMask); 3683 } 3684 3685 if (N1C) { 3686 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue()); 3687 if (NewSHL.getNode()) 3688 return NewSHL; 3689 } 3690 3691 return SDValue(); 3692} 3693 3694SDValue DAGCombiner::visitSRA(SDNode *N) { 3695 SDValue N0 = N->getOperand(0); 3696 SDValue N1 = N->getOperand(1); 3697 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3698 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3699 EVT VT = N0.getValueType(); 3700 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3701 3702 // fold (sra c1, c2) -> (sra c1, c2) 3703 if (N0C && N1C) 3704 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 3705 // fold (sra 0, x) -> 0 3706 if (N0C && N0C->isNullValue()) 3707 return N0; 3708 // fold (sra -1, x) -> -1 3709 if (N0C && N0C->isAllOnesValue()) 3710 return N0; 3711 // fold (sra x, (setge c, size(x))) -> undef 3712 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3713 return DAG.getUNDEF(VT); 3714 // fold (sra x, 0) -> x 3715 if (N1C && N1C->isNullValue()) 3716 return N0; 3717 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 3718 // sext_inreg. 3719 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 3720 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue(); 3721 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); 3722 if (VT.isVector()) 3723 ExtVT = EVT::getVectorVT(*DAG.getContext(), 3724 ExtVT, VT.getVectorNumElements()); 3725 if ((!LegalOperations || 3726 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT))) 3727 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3728 N0.getOperand(0), DAG.getValueType(ExtVT)); 3729 } 3730 3731 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 3732 if (N1C && N0.getOpcode() == ISD::SRA) { 3733 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3734 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 3735 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1; 3736 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 3737 DAG.getConstant(Sum, N1C->getValueType(0))); 3738 } 3739 } 3740 3741 // fold (sra (shl X, m), (sub result_size, n)) 3742 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 3743 // result_size - n != m. 3744 // If truncate is free for the target sext(shl) is likely to result in better 3745 // code. 3746 if (N0.getOpcode() == ISD::SHL) { 3747 // Get the two constanst of the shifts, CN0 = m, CN = n. 3748 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3749 if (N01C && N1C) { 3750 // Determine what the truncate's result bitsize and type would be. 3751 EVT TruncVT = 3752 EVT::getIntegerVT(*DAG.getContext(), 3753 OpSizeInBits - N1C->getZExtValue()); 3754 // Determine the residual right-shift amount. 3755 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 3756 3757 // If the shift is not a no-op (in which case this should be just a sign 3758 // extend already), the truncated to type is legal, sign_extend is legal 3759 // on that type, and the truncate to that type is both legal and free, 3760 // perform the transform. 3761 if ((ShiftAmt > 0) && 3762 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 3763 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 3764 TLI.isTruncateFree(VT, TruncVT)) { 3765 3766 SDValue Amt = DAG.getConstant(ShiftAmt, 3767 getShiftAmountTy(N0.getOperand(0).getValueType())); 3768 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 3769 N0.getOperand(0), Amt); 3770 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 3771 Shift); 3772 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 3773 N->getValueType(0), Trunc); 3774 } 3775 } 3776 } 3777 3778 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 3779 if (N1.getOpcode() == ISD::TRUNCATE && 3780 N1.getOperand(0).getOpcode() == ISD::AND && 3781 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3782 SDValue N101 = N1.getOperand(0).getOperand(1); 3783 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3784 EVT TruncVT = N1.getValueType(); 3785 SDValue N100 = N1.getOperand(0).getOperand(0); 3786 APInt TruncC = N101C->getAPIntValue(); 3787 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits()); 3788 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 3789 DAG.getNode(ISD::AND, N->getDebugLoc(), 3790 TruncVT, 3791 DAG.getNode(ISD::TRUNCATE, 3792 N->getDebugLoc(), 3793 TruncVT, N100), 3794 DAG.getConstant(TruncC, TruncVT))); 3795 } 3796 } 3797 3798 // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2)) 3799 // if c1 is equal to the number of bits the trunc removes 3800 if (N0.getOpcode() == ISD::TRUNCATE && 3801 (N0.getOperand(0).getOpcode() == ISD::SRL || 3802 N0.getOperand(0).getOpcode() == ISD::SRA) && 3803 N0.getOperand(0).hasOneUse() && 3804 N0.getOperand(0).getOperand(1).hasOneUse() && 3805 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) { 3806 EVT LargeVT = N0.getOperand(0).getValueType(); 3807 ConstantSDNode *LargeShiftAmt = 3808 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1)); 3809 3810 if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits == 3811 LargeShiftAmt->getZExtValue()) { 3812 SDValue Amt = 3813 DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(), 3814 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType())); 3815 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT, 3816 N0.getOperand(0).getOperand(0), Amt); 3817 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, SRA); 3818 } 3819 } 3820 3821 // Simplify, based on bits shifted out of the LHS. 3822 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3823 return SDValue(N, 0); 3824 3825 3826 // If the sign bit is known to be zero, switch this to a SRL. 3827 if (DAG.SignBitIsZero(N0)) 3828 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 3829 3830 if (N1C) { 3831 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue()); 3832 if (NewSRA.getNode()) 3833 return NewSRA; 3834 } 3835 3836 return SDValue(); 3837} 3838 3839SDValue DAGCombiner::visitSRL(SDNode *N) { 3840 SDValue N0 = N->getOperand(0); 3841 SDValue N1 = N->getOperand(1); 3842 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3843 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3844 EVT VT = N0.getValueType(); 3845 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3846 3847 // fold (srl c1, c2) -> c1 >>u c2 3848 if (N0C && N1C) 3849 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 3850 // fold (srl 0, x) -> 0 3851 if (N0C && N0C->isNullValue()) 3852 return N0; 3853 // fold (srl x, c >= size(x)) -> undef 3854 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3855 return DAG.getUNDEF(VT); 3856 // fold (srl x, 0) -> x 3857 if (N1C && N1C->isNullValue()) 3858 return N0; 3859 // if (srl x, c) is known to be zero, return 0 3860 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 3861 APInt::getAllOnesValue(OpSizeInBits))) 3862 return DAG.getConstant(0, VT); 3863 3864 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 3865 if (N1C && N0.getOpcode() == ISD::SRL && 3866 N0.getOperand(1).getOpcode() == ISD::Constant) { 3867 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3868 uint64_t c2 = N1C->getZExtValue(); 3869 if (c1 + c2 >= OpSizeInBits) 3870 return DAG.getConstant(0, VT); 3871 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3872 DAG.getConstant(c1 + c2, N1.getValueType())); 3873 } 3874 3875 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2))) 3876 if (N1C && N0.getOpcode() == ISD::TRUNCATE && 3877 N0.getOperand(0).getOpcode() == ISD::SRL && 3878 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3879 uint64_t c1 = 3880 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3881 uint64_t c2 = N1C->getZExtValue(); 3882 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3883 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType(); 3884 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3885 // This is only valid if the OpSizeInBits + c1 = size of inner shift. 3886 if (c1 + OpSizeInBits == InnerShiftSize) { 3887 if (c1 + c2 >= InnerShiftSize) 3888 return DAG.getConstant(0, VT); 3889 return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT, 3890 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT, 3891 N0.getOperand(0)->getOperand(0), 3892 DAG.getConstant(c1 + c2, ShiftCountVT))); 3893 } 3894 } 3895 3896 // fold (srl (shl x, c), c) -> (and x, cst2) 3897 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 && 3898 N0.getValueSizeInBits() <= 64) { 3899 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits(); 3900 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3901 DAG.getConstant(~0ULL >> ShAmt, VT)); 3902 } 3903 3904 3905 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 3906 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 3907 // Shifting in all undef bits? 3908 EVT SmallVT = N0.getOperand(0).getValueType(); 3909 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 3910 return DAG.getUNDEF(VT); 3911 3912 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { 3913 uint64_t ShiftAmt = N1C->getZExtValue(); 3914 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 3915 N0.getOperand(0), 3916 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT))); 3917 AddToWorkList(SmallShift.getNode()); 3918 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 3919 } 3920 } 3921 3922 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 3923 // bit, which is unmodified by sra. 3924 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 3925 if (N0.getOpcode() == ISD::SRA) 3926 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 3927 } 3928 3929 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 3930 if (N1C && N0.getOpcode() == ISD::CTLZ && 3931 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 3932 APInt KnownZero, KnownOne; 3933 DAG.ComputeMaskedBits(N0.getOperand(0), KnownZero, KnownOne); 3934 3935 // If any of the input bits are KnownOne, then the input couldn't be all 3936 // zeros, thus the result of the srl will always be zero. 3937 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 3938 3939 // If all of the bits input the to ctlz node are known to be zero, then 3940 // the result of the ctlz is "32" and the result of the shift is one. 3941 APInt UnknownBits = ~KnownZero; 3942 if (UnknownBits == 0) return DAG.getConstant(1, VT); 3943 3944 // Otherwise, check to see if there is exactly one bit input to the ctlz. 3945 if ((UnknownBits & (UnknownBits - 1)) == 0) { 3946 // Okay, we know that only that the single bit specified by UnknownBits 3947 // could be set on input to the CTLZ node. If this bit is set, the SRL 3948 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 3949 // to an SRL/XOR pair, which is likely to simplify more. 3950 unsigned ShAmt = UnknownBits.countTrailingZeros(); 3951 SDValue Op = N0.getOperand(0); 3952 3953 if (ShAmt) { 3954 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 3955 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType()))); 3956 AddToWorkList(Op.getNode()); 3957 } 3958 3959 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3960 Op, DAG.getConstant(1, VT)); 3961 } 3962 } 3963 3964 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 3965 if (N1.getOpcode() == ISD::TRUNCATE && 3966 N1.getOperand(0).getOpcode() == ISD::AND && 3967 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3968 SDValue N101 = N1.getOperand(0).getOperand(1); 3969 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3970 EVT TruncVT = N1.getValueType(); 3971 SDValue N100 = N1.getOperand(0).getOperand(0); 3972 APInt TruncC = N101C->getAPIntValue(); 3973 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3974 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 3975 DAG.getNode(ISD::AND, N->getDebugLoc(), 3976 TruncVT, 3977 DAG.getNode(ISD::TRUNCATE, 3978 N->getDebugLoc(), 3979 TruncVT, N100), 3980 DAG.getConstant(TruncC, TruncVT))); 3981 } 3982 } 3983 3984 // fold operands of srl based on knowledge that the low bits are not 3985 // demanded. 3986 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3987 return SDValue(N, 0); 3988 3989 if (N1C) { 3990 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue()); 3991 if (NewSRL.getNode()) 3992 return NewSRL; 3993 } 3994 3995 // Attempt to convert a srl of a load into a narrower zero-extending load. 3996 SDValue NarrowLoad = ReduceLoadWidth(N); 3997 if (NarrowLoad.getNode()) 3998 return NarrowLoad; 3999 4000 // Here is a common situation. We want to optimize: 4001 // 4002 // %a = ... 4003 // %b = and i32 %a, 2 4004 // %c = srl i32 %b, 1 4005 // brcond i32 %c ... 4006 // 4007 // into 4008 // 4009 // %a = ... 4010 // %b = and %a, 2 4011 // %c = setcc eq %b, 0 4012 // brcond %c ... 4013 // 4014 // However when after the source operand of SRL is optimized into AND, the SRL 4015 // itself may not be optimized further. Look for it and add the BRCOND into 4016 // the worklist. 4017 if (N->hasOneUse()) { 4018 SDNode *Use = *N->use_begin(); 4019 if (Use->getOpcode() == ISD::BRCOND) 4020 AddToWorkList(Use); 4021 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) { 4022 // Also look pass the truncate. 4023 Use = *Use->use_begin(); 4024 if (Use->getOpcode() == ISD::BRCOND) 4025 AddToWorkList(Use); 4026 } 4027 } 4028 4029 return SDValue(); 4030} 4031 4032SDValue DAGCombiner::visitCTLZ(SDNode *N) { 4033 SDValue N0 = N->getOperand(0); 4034 EVT VT = N->getValueType(0); 4035 4036 // fold (ctlz c1) -> c2 4037 if (isa<ConstantSDNode>(N0)) 4038 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 4039 return SDValue(); 4040} 4041 4042SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) { 4043 SDValue N0 = N->getOperand(0); 4044 EVT VT = N->getValueType(0); 4045 4046 // fold (ctlz_zero_undef c1) -> c2 4047 if (isa<ConstantSDNode>(N0)) 4048 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0); 4049 return SDValue(); 4050} 4051 4052SDValue DAGCombiner::visitCTTZ(SDNode *N) { 4053 SDValue N0 = N->getOperand(0); 4054 EVT VT = N->getValueType(0); 4055 4056 // fold (cttz c1) -> c2 4057 if (isa<ConstantSDNode>(N0)) 4058 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 4059 return SDValue(); 4060} 4061 4062SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) { 4063 SDValue N0 = N->getOperand(0); 4064 EVT VT = N->getValueType(0); 4065 4066 // fold (cttz_zero_undef c1) -> c2 4067 if (isa<ConstantSDNode>(N0)) 4068 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0); 4069 return SDValue(); 4070} 4071 4072SDValue DAGCombiner::visitCTPOP(SDNode *N) { 4073 SDValue N0 = N->getOperand(0); 4074 EVT VT = N->getValueType(0); 4075 4076 // fold (ctpop c1) -> c2 4077 if (isa<ConstantSDNode>(N0)) 4078 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 4079 return SDValue(); 4080} 4081 4082SDValue DAGCombiner::visitSELECT(SDNode *N) { 4083 SDValue N0 = N->getOperand(0); 4084 SDValue N1 = N->getOperand(1); 4085 SDValue N2 = N->getOperand(2); 4086 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4087 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 4088 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 4089 EVT VT = N->getValueType(0); 4090 EVT VT0 = N0.getValueType(); 4091 4092 // fold (select C, X, X) -> X 4093 if (N1 == N2) 4094 return N1; 4095 // fold (select true, X, Y) -> X 4096 if (N0C && !N0C->isNullValue()) 4097 return N1; 4098 // fold (select false, X, Y) -> Y 4099 if (N0C && N0C->isNullValue()) 4100 return N2; 4101 // fold (select C, 1, X) -> (or C, X) 4102 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 4103 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 4104 // fold (select C, 0, 1) -> (xor C, 1) 4105 if (VT.isInteger() && 4106 (VT0 == MVT::i1 || 4107 (VT0.isInteger() && 4108 TLI.getBooleanContents(false) == 4109 TargetLowering::ZeroOrOneBooleanContent)) && 4110 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 4111 SDValue XORNode; 4112 if (VT == VT0) 4113 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 4114 N0, DAG.getConstant(1, VT0)); 4115 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 4116 N0, DAG.getConstant(1, VT0)); 4117 AddToWorkList(XORNode.getNode()); 4118 if (VT.bitsGT(VT0)) 4119 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 4120 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 4121 } 4122 // fold (select C, 0, X) -> (and (not C), X) 4123 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 4124 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 4125 AddToWorkList(NOTNode.getNode()); 4126 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 4127 } 4128 // fold (select C, X, 1) -> (or (not C), X) 4129 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 4130 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 4131 AddToWorkList(NOTNode.getNode()); 4132 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 4133 } 4134 // fold (select C, X, 0) -> (and C, X) 4135 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 4136 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 4137 // fold (select X, X, Y) -> (or X, Y) 4138 // fold (select X, 1, Y) -> (or X, Y) 4139 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 4140 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 4141 // fold (select X, Y, X) -> (and X, Y) 4142 // fold (select X, Y, 0) -> (and X, Y) 4143 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 4144 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 4145 4146 // If we can fold this based on the true/false value, do so. 4147 if (SimplifySelectOps(N, N1, N2)) 4148 return SDValue(N, 0); // Don't revisit N. 4149 4150 // fold selects based on a setcc into other things, such as min/max/abs 4151 if (N0.getOpcode() == ISD::SETCC) { 4152 // FIXME: 4153 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 4154 // having to say they don't support SELECT_CC on every type the DAG knows 4155 // about, since there is no way to mark an opcode illegal at all value types 4156 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && 4157 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) 4158 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 4159 N0.getOperand(0), N0.getOperand(1), 4160 N1, N2, N0.getOperand(2)); 4161 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 4162 } 4163 4164 return SDValue(); 4165} 4166 4167SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 4168 SDValue N0 = N->getOperand(0); 4169 SDValue N1 = N->getOperand(1); 4170 SDValue N2 = N->getOperand(2); 4171 SDValue N3 = N->getOperand(3); 4172 SDValue N4 = N->getOperand(4); 4173 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 4174 4175 // fold select_cc lhs, rhs, x, x, cc -> x 4176 if (N2 == N3) 4177 return N2; 4178 4179 // Determine if the condition we're dealing with is constant 4180 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 4181 N0, N1, CC, N->getDebugLoc(), false); 4182 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 4183 4184 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 4185 if (!SCCC->isNullValue()) 4186 return N2; // cond always true -> true val 4187 else 4188 return N3; // cond always false -> false val 4189 } 4190 4191 // Fold to a simpler select_cc 4192 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 4193 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 4194 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 4195 SCC.getOperand(2)); 4196 4197 // If we can fold this based on the true/false value, do so. 4198 if (SimplifySelectOps(N, N2, N3)) 4199 return SDValue(N, 0); // Don't revisit N. 4200 4201 // fold select_cc into other things, such as min/max/abs 4202 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 4203} 4204 4205SDValue DAGCombiner::visitSETCC(SDNode *N) { 4206 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 4207 cast<CondCodeSDNode>(N->getOperand(2))->get(), 4208 N->getDebugLoc()); 4209} 4210 4211// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 4212// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 4213// transformation. Returns true if extension are possible and the above 4214// mentioned transformation is profitable. 4215static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 4216 unsigned ExtOpc, 4217 SmallVector<SDNode*, 4> &ExtendNodes, 4218 const TargetLowering &TLI) { 4219 bool HasCopyToRegUses = false; 4220 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 4221 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 4222 UE = N0.getNode()->use_end(); 4223 UI != UE; ++UI) { 4224 SDNode *User = *UI; 4225 if (User == N) 4226 continue; 4227 if (UI.getUse().getResNo() != N0.getResNo()) 4228 continue; 4229 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 4230 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 4231 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 4232 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 4233 // Sign bits will be lost after a zext. 4234 return false; 4235 bool Add = false; 4236 for (unsigned i = 0; i != 2; ++i) { 4237 SDValue UseOp = User->getOperand(i); 4238 if (UseOp == N0) 4239 continue; 4240 if (!isa<ConstantSDNode>(UseOp)) 4241 return false; 4242 Add = true; 4243 } 4244 if (Add) 4245 ExtendNodes.push_back(User); 4246 continue; 4247 } 4248 // If truncates aren't free and there are users we can't 4249 // extend, it isn't worthwhile. 4250 if (!isTruncFree) 4251 return false; 4252 // Remember if this value is live-out. 4253 if (User->getOpcode() == ISD::CopyToReg) 4254 HasCopyToRegUses = true; 4255 } 4256 4257 if (HasCopyToRegUses) { 4258 bool BothLiveOut = false; 4259 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 4260 UI != UE; ++UI) { 4261 SDUse &Use = UI.getUse(); 4262 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 4263 BothLiveOut = true; 4264 break; 4265 } 4266 } 4267 if (BothLiveOut) 4268 // Both unextended and extended values are live out. There had better be 4269 // a good reason for the transformation. 4270 return ExtendNodes.size(); 4271 } 4272 return true; 4273} 4274 4275void DAGCombiner::ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs, 4276 SDValue Trunc, SDValue ExtLoad, DebugLoc DL, 4277 ISD::NodeType ExtType) { 4278 // Extend SetCC uses if necessary. 4279 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 4280 SDNode *SetCC = SetCCs[i]; 4281 SmallVector<SDValue, 4> Ops; 4282 4283 for (unsigned j = 0; j != 2; ++j) { 4284 SDValue SOp = SetCC->getOperand(j); 4285 if (SOp == Trunc) 4286 Ops.push_back(ExtLoad); 4287 else 4288 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp)); 4289 } 4290 4291 Ops.push_back(SetCC->getOperand(2)); 4292 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), 4293 &Ops[0], Ops.size())); 4294 } 4295} 4296 4297SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 4298 SDValue N0 = N->getOperand(0); 4299 EVT VT = N->getValueType(0); 4300 4301 // fold (sext c1) -> c1 4302 if (isa<ConstantSDNode>(N0)) 4303 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 4304 4305 // fold (sext (sext x)) -> (sext x) 4306 // fold (sext (aext x)) -> (sext x) 4307 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 4308 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 4309 N0.getOperand(0)); 4310 4311 if (N0.getOpcode() == ISD::TRUNCATE) { 4312 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 4313 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 4314 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4315 if (NarrowLoad.getNode()) { 4316 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4317 if (NarrowLoad.getNode() != N0.getNode()) { 4318 CombineTo(N0.getNode(), NarrowLoad); 4319 // CombineTo deleted the truncate, if needed, but not what's under it. 4320 AddToWorkList(oye); 4321 } 4322 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4323 } 4324 4325 // See if the value being truncated is already sign extended. If so, just 4326 // eliminate the trunc/sext pair. 4327 SDValue Op = N0.getOperand(0); 4328 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits(); 4329 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits(); 4330 unsigned DestBits = VT.getScalarType().getSizeInBits(); 4331 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 4332 4333 if (OpBits == DestBits) { 4334 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 4335 // bits, it is already ready. 4336 if (NumSignBits > DestBits-MidBits) 4337 return Op; 4338 } else if (OpBits < DestBits) { 4339 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 4340 // bits, just sext from i32. 4341 if (NumSignBits > OpBits-MidBits) 4342 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 4343 } else { 4344 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 4345 // bits, just truncate to i32. 4346 if (NumSignBits > OpBits-MidBits) 4347 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4348 } 4349 4350 // fold (sext (truncate x)) -> (sextinreg x). 4351 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 4352 N0.getValueType())) { 4353 if (OpBits < DestBits) 4354 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 4355 else if (OpBits > DestBits) 4356 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 4357 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 4358 DAG.getValueType(N0.getValueType())); 4359 } 4360 } 4361 4362 // fold (sext (load x)) -> (sext (truncate (sextload x))) 4363 // None of the supported targets knows how to perform load and sign extend 4364 // on vectors in one instruction. We only perform this transformation on 4365 // scalars. 4366 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4367 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4368 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 4369 bool DoXform = true; 4370 SmallVector<SDNode*, 4> SetCCs; 4371 if (!N0.hasOneUse()) 4372 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 4373 if (DoXform) { 4374 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4375 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4376 LN0->getChain(), 4377 LN0->getBasePtr(), LN0->getPointerInfo(), 4378 N0.getValueType(), 4379 LN0->isVolatile(), LN0->isNonTemporal(), 4380 LN0->getAlignment()); 4381 CombineTo(N, ExtLoad); 4382 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4383 N0.getValueType(), ExtLoad); 4384 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4385 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4386 ISD::SIGN_EXTEND); 4387 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4388 } 4389 } 4390 4391 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 4392 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 4393 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 4394 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 4395 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4396 EVT MemVT = LN0->getMemoryVT(); 4397 if ((!LegalOperations && !LN0->isVolatile()) || 4398 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { 4399 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4400 LN0->getChain(), 4401 LN0->getBasePtr(), LN0->getPointerInfo(), 4402 MemVT, 4403 LN0->isVolatile(), LN0->isNonTemporal(), 4404 LN0->getAlignment()); 4405 CombineTo(N, ExtLoad); 4406 CombineTo(N0.getNode(), 4407 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4408 N0.getValueType(), ExtLoad), 4409 ExtLoad.getValue(1)); 4410 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4411 } 4412 } 4413 4414 // fold (sext (and/or/xor (load x), cst)) -> 4415 // (and/or/xor (sextload x), (sext cst)) 4416 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || 4417 N0.getOpcode() == ISD::XOR) && 4418 isa<LoadSDNode>(N0.getOperand(0)) && 4419 N0.getOperand(1).getOpcode() == ISD::Constant && 4420 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) && 4421 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { 4422 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0)); 4423 if (LN0->getExtensionType() != ISD::ZEXTLOAD) { 4424 bool DoXform = true; 4425 SmallVector<SDNode*, 4> SetCCs; 4426 if (!N0.hasOneUse()) 4427 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND, 4428 SetCCs, TLI); 4429 if (DoXform) { 4430 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, LN0->getDebugLoc(), VT, 4431 LN0->getChain(), LN0->getBasePtr(), 4432 LN0->getPointerInfo(), 4433 LN0->getMemoryVT(), 4434 LN0->isVolatile(), 4435 LN0->isNonTemporal(), 4436 LN0->getAlignment()); 4437 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4438 Mask = Mask.sext(VT.getSizeInBits()); 4439 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4440 ExtLoad, DAG.getConstant(Mask, VT)); 4441 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, 4442 N0.getOperand(0).getDebugLoc(), 4443 N0.getOperand(0).getValueType(), ExtLoad); 4444 CombineTo(N, And); 4445 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1)); 4446 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4447 ISD::SIGN_EXTEND); 4448 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4449 } 4450 } 4451 } 4452 4453 if (N0.getOpcode() == ISD::SETCC) { 4454 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 4455 // Only do this before legalize for now. 4456 if (VT.isVector() && !LegalOperations) { 4457 EVT N0VT = N0.getOperand(0).getValueType(); 4458 // On some architectures (such as SSE/NEON/etc) the SETCC result type is 4459 // of the same size as the compared operands. Only optimize sext(setcc()) 4460 // if this is the case. 4461 EVT SVT = TLI.getSetCCResultType(N0VT); 4462 4463 // We know that the # elements of the results is the same as the 4464 // # elements of the compare (and the # elements of the compare result 4465 // for that matter). Check to see that they are the same size. If so, 4466 // we know that the element size of the sext'd result matches the 4467 // element size of the compare operands. 4468 if (VT.getSizeInBits() == SVT.getSizeInBits()) 4469 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4470 N0.getOperand(1), 4471 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4472 // If the desired elements are smaller or larger than the source 4473 // elements we can use a matching integer vector type and then 4474 // truncate/sign extend 4475 EVT MatchingElementType = 4476 EVT::getIntegerVT(*DAG.getContext(), 4477 N0VT.getScalarType().getSizeInBits()); 4478 EVT MatchingVectorType = 4479 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4480 N0VT.getVectorNumElements()); 4481 4482 if (SVT == MatchingVectorType) { 4483 SDValue VsetCC = DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, 4484 N0.getOperand(0), N0.getOperand(1), 4485 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4486 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4487 } 4488 } 4489 4490 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 4491 unsigned ElementWidth = VT.getScalarType().getSizeInBits(); 4492 SDValue NegOne = 4493 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT); 4494 SDValue SCC = 4495 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4496 NegOne, DAG.getConstant(0, VT), 4497 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4498 if (SCC.getNode()) return SCC; 4499 if (!VT.isVector() && (!LegalOperations || 4500 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT)))) 4501 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 4502 DAG.getSetCC(N->getDebugLoc(), 4503 TLI.getSetCCResultType(VT), 4504 N0.getOperand(0), N0.getOperand(1), 4505 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4506 NegOne, DAG.getConstant(0, VT)); 4507 } 4508 4509 // fold (sext x) -> (zext x) if the sign bit is known zero. 4510 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 4511 DAG.SignBitIsZero(N0)) 4512 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 4513 4514 return SDValue(); 4515} 4516 4517// isTruncateOf - If N is a truncate of some other value, return true, record 4518// the value being truncated in Op and which of Op's bits are zero in KnownZero. 4519// This function computes KnownZero to avoid a duplicated call to 4520// ComputeMaskedBits in the caller. 4521static bool isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op, 4522 APInt &KnownZero) { 4523 APInt KnownOne; 4524 if (N->getOpcode() == ISD::TRUNCATE) { 4525 Op = N->getOperand(0); 4526 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne); 4527 return true; 4528 } 4529 4530 if (N->getOpcode() != ISD::SETCC || N->getValueType(0) != MVT::i1 || 4531 cast<CondCodeSDNode>(N->getOperand(2))->get() != ISD::SETNE) 4532 return false; 4533 4534 SDValue Op0 = N->getOperand(0); 4535 SDValue Op1 = N->getOperand(1); 4536 assert(Op0.getValueType() == Op1.getValueType()); 4537 4538 ConstantSDNode *COp0 = dyn_cast<ConstantSDNode>(Op0); 4539 ConstantSDNode *COp1 = dyn_cast<ConstantSDNode>(Op1); 4540 if (COp0 && COp0->isNullValue()) 4541 Op = Op1; 4542 else if (COp1 && COp1->isNullValue()) 4543 Op = Op0; 4544 else 4545 return false; 4546 4547 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne); 4548 4549 if (!(KnownZero | APInt(Op.getValueSizeInBits(), 1)).isAllOnesValue()) 4550 return false; 4551 4552 return true; 4553} 4554 4555SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 4556 SDValue N0 = N->getOperand(0); 4557 EVT VT = N->getValueType(0); 4558 4559 // fold (zext c1) -> c1 4560 if (isa<ConstantSDNode>(N0)) 4561 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 4562 // fold (zext (zext x)) -> (zext x) 4563 // fold (zext (aext x)) -> (zext x) 4564 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 4565 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 4566 N0.getOperand(0)); 4567 4568 // fold (zext (truncate x)) -> (zext x) or 4569 // (zext (truncate x)) -> (truncate x) 4570 // This is valid when the truncated bits of x are already zero. 4571 // FIXME: We should extend this to work for vectors too. 4572 SDValue Op; 4573 APInt KnownZero; 4574 if (!VT.isVector() && isTruncateOf(DAG, N0, Op, KnownZero)) { 4575 APInt TruncatedBits = 4576 (Op.getValueSizeInBits() == N0.getValueSizeInBits()) ? 4577 APInt(Op.getValueSizeInBits(), 0) : 4578 APInt::getBitsSet(Op.getValueSizeInBits(), 4579 N0.getValueSizeInBits(), 4580 std::min(Op.getValueSizeInBits(), 4581 VT.getSizeInBits())); 4582 if (TruncatedBits == (KnownZero & TruncatedBits)) { 4583 if (VT.bitsGT(Op.getValueType())) 4584 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, Op); 4585 if (VT.bitsLT(Op.getValueType())) 4586 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4587 4588 return Op; 4589 } 4590 } 4591 4592 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 4593 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 4594 if (N0.getOpcode() == ISD::TRUNCATE) { 4595 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4596 if (NarrowLoad.getNode()) { 4597 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4598 if (NarrowLoad.getNode() != N0.getNode()) { 4599 CombineTo(N0.getNode(), NarrowLoad); 4600 // CombineTo deleted the truncate, if needed, but not what's under it. 4601 AddToWorkList(oye); 4602 } 4603 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4604 } 4605 } 4606 4607 // fold (zext (truncate x)) -> (and x, mask) 4608 if (N0.getOpcode() == ISD::TRUNCATE && 4609 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 4610 4611 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 4612 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n))) 4613 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4614 if (NarrowLoad.getNode()) { 4615 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4616 if (NarrowLoad.getNode() != N0.getNode()) { 4617 CombineTo(N0.getNode(), NarrowLoad); 4618 // CombineTo deleted the truncate, if needed, but not what's under it. 4619 AddToWorkList(oye); 4620 } 4621 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4622 } 4623 4624 SDValue Op = N0.getOperand(0); 4625 if (Op.getValueType().bitsLT(VT)) { 4626 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 4627 AddToWorkList(Op.getNode()); 4628 } else if (Op.getValueType().bitsGT(VT)) { 4629 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4630 AddToWorkList(Op.getNode()); 4631 } 4632 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), 4633 N0.getValueType().getScalarType()); 4634 } 4635 4636 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 4637 // if either of the casts is not free. 4638 if (N0.getOpcode() == ISD::AND && 4639 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4640 N0.getOperand(1).getOpcode() == ISD::Constant && 4641 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4642 N0.getValueType()) || 4643 !TLI.isZExtFree(N0.getValueType(), VT))) { 4644 SDValue X = N0.getOperand(0).getOperand(0); 4645 if (X.getValueType().bitsLT(VT)) { 4646 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 4647 } else if (X.getValueType().bitsGT(VT)) { 4648 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 4649 } 4650 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4651 Mask = Mask.zext(VT.getSizeInBits()); 4652 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4653 X, DAG.getConstant(Mask, VT)); 4654 } 4655 4656 // fold (zext (load x)) -> (zext (truncate (zextload x))) 4657 // None of the supported targets knows how to perform load and vector_zext 4658 // on vectors in one instruction. We only perform this transformation on 4659 // scalars. 4660 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4661 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4662 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 4663 bool DoXform = true; 4664 SmallVector<SDNode*, 4> SetCCs; 4665 if (!N0.hasOneUse()) 4666 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 4667 if (DoXform) { 4668 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4669 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 4670 LN0->getChain(), 4671 LN0->getBasePtr(), LN0->getPointerInfo(), 4672 N0.getValueType(), 4673 LN0->isVolatile(), LN0->isNonTemporal(), 4674 LN0->getAlignment()); 4675 CombineTo(N, ExtLoad); 4676 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4677 N0.getValueType(), ExtLoad); 4678 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4679 4680 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4681 ISD::ZERO_EXTEND); 4682 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4683 } 4684 } 4685 4686 // fold (zext (and/or/xor (load x), cst)) -> 4687 // (and/or/xor (zextload x), (zext cst)) 4688 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || 4689 N0.getOpcode() == ISD::XOR) && 4690 isa<LoadSDNode>(N0.getOperand(0)) && 4691 N0.getOperand(1).getOpcode() == ISD::Constant && 4692 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) && 4693 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { 4694 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0)); 4695 if (LN0->getExtensionType() != ISD::SEXTLOAD) { 4696 bool DoXform = true; 4697 SmallVector<SDNode*, 4> SetCCs; 4698 if (!N0.hasOneUse()) 4699 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND, 4700 SetCCs, TLI); 4701 if (DoXform) { 4702 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, 4703 LN0->getChain(), LN0->getBasePtr(), 4704 LN0->getPointerInfo(), 4705 LN0->getMemoryVT(), 4706 LN0->isVolatile(), 4707 LN0->isNonTemporal(), 4708 LN0->getAlignment()); 4709 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4710 Mask = Mask.zext(VT.getSizeInBits()); 4711 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4712 ExtLoad, DAG.getConstant(Mask, VT)); 4713 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, 4714 N0.getOperand(0).getDebugLoc(), 4715 N0.getOperand(0).getValueType(), ExtLoad); 4716 CombineTo(N, And); 4717 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1)); 4718 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4719 ISD::ZERO_EXTEND); 4720 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4721 } 4722 } 4723 } 4724 4725 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 4726 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 4727 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 4728 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 4729 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4730 EVT MemVT = LN0->getMemoryVT(); 4731 if ((!LegalOperations && !LN0->isVolatile()) || 4732 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) { 4733 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 4734 LN0->getChain(), 4735 LN0->getBasePtr(), LN0->getPointerInfo(), 4736 MemVT, 4737 LN0->isVolatile(), LN0->isNonTemporal(), 4738 LN0->getAlignment()); 4739 CombineTo(N, ExtLoad); 4740 CombineTo(N0.getNode(), 4741 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 4742 ExtLoad), 4743 ExtLoad.getValue(1)); 4744 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4745 } 4746 } 4747 4748 if (N0.getOpcode() == ISD::SETCC) { 4749 if (!LegalOperations && VT.isVector()) { 4750 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors. 4751 // Only do this before legalize for now. 4752 EVT N0VT = N0.getOperand(0).getValueType(); 4753 EVT EltVT = VT.getVectorElementType(); 4754 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(), 4755 DAG.getConstant(1, EltVT)); 4756 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4757 // We know that the # elements of the results is the same as the 4758 // # elements of the compare (and the # elements of the compare result 4759 // for that matter). Check to see that they are the same size. If so, 4760 // we know that the element size of the sext'd result matches the 4761 // element size of the compare operands. 4762 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4763 DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4764 N0.getOperand(1), 4765 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4766 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4767 &OneOps[0], OneOps.size())); 4768 4769 // If the desired elements are smaller or larger than the source 4770 // elements we can use a matching integer vector type and then 4771 // truncate/sign extend 4772 EVT MatchingElementType = 4773 EVT::getIntegerVT(*DAG.getContext(), 4774 N0VT.getScalarType().getSizeInBits()); 4775 EVT MatchingVectorType = 4776 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4777 N0VT.getVectorNumElements()); 4778 SDValue VsetCC = 4779 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4780 N0.getOperand(1), 4781 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4782 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4783 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT), 4784 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4785 &OneOps[0], OneOps.size())); 4786 } 4787 4788 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4789 SDValue SCC = 4790 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4791 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4792 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4793 if (SCC.getNode()) return SCC; 4794 } 4795 4796 // (zext (shl (zext x), cst)) -> (shl (zext x), cst) 4797 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && 4798 isa<ConstantSDNode>(N0.getOperand(1)) && 4799 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && 4800 N0.hasOneUse()) { 4801 SDValue ShAmt = N0.getOperand(1); 4802 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue(); 4803 if (N0.getOpcode() == ISD::SHL) { 4804 SDValue InnerZExt = N0.getOperand(0); 4805 // If the original shl may be shifting out bits, do not perform this 4806 // transformation. 4807 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() - 4808 InnerZExt.getOperand(0).getValueType().getSizeInBits(); 4809 if (ShAmtVal > KnownZeroBits) 4810 return SDValue(); 4811 } 4812 4813 DebugLoc DL = N->getDebugLoc(); 4814 4815 // Ensure that the shift amount is wide enough for the shifted value. 4816 if (VT.getSizeInBits() >= 256) 4817 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt); 4818 4819 return DAG.getNode(N0.getOpcode(), DL, VT, 4820 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)), 4821 ShAmt); 4822 } 4823 4824 return SDValue(); 4825} 4826 4827SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 4828 SDValue N0 = N->getOperand(0); 4829 EVT VT = N->getValueType(0); 4830 4831 // fold (aext c1) -> c1 4832 if (isa<ConstantSDNode>(N0)) 4833 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 4834 // fold (aext (aext x)) -> (aext x) 4835 // fold (aext (zext x)) -> (zext x) 4836 // fold (aext (sext x)) -> (sext x) 4837 if (N0.getOpcode() == ISD::ANY_EXTEND || 4838 N0.getOpcode() == ISD::ZERO_EXTEND || 4839 N0.getOpcode() == ISD::SIGN_EXTEND) 4840 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 4841 4842 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 4843 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 4844 if (N0.getOpcode() == ISD::TRUNCATE) { 4845 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4846 if (NarrowLoad.getNode()) { 4847 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4848 if (NarrowLoad.getNode() != N0.getNode()) { 4849 CombineTo(N0.getNode(), NarrowLoad); 4850 // CombineTo deleted the truncate, if needed, but not what's under it. 4851 AddToWorkList(oye); 4852 } 4853 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4854 } 4855 } 4856 4857 // fold (aext (truncate x)) 4858 if (N0.getOpcode() == ISD::TRUNCATE) { 4859 SDValue TruncOp = N0.getOperand(0); 4860 if (TruncOp.getValueType() == VT) 4861 return TruncOp; // x iff x size == zext size. 4862 if (TruncOp.getValueType().bitsGT(VT)) 4863 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 4864 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 4865 } 4866 4867 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 4868 // if the trunc is not free. 4869 if (N0.getOpcode() == ISD::AND && 4870 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4871 N0.getOperand(1).getOpcode() == ISD::Constant && 4872 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4873 N0.getValueType())) { 4874 SDValue X = N0.getOperand(0).getOperand(0); 4875 if (X.getValueType().bitsLT(VT)) { 4876 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 4877 } else if (X.getValueType().bitsGT(VT)) { 4878 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 4879 } 4880 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4881 Mask = Mask.zext(VT.getSizeInBits()); 4882 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4883 X, DAG.getConstant(Mask, VT)); 4884 } 4885 4886 // fold (aext (load x)) -> (aext (truncate (extload x))) 4887 // None of the supported targets knows how to perform load and any_ext 4888 // on vectors in one instruction. We only perform this transformation on 4889 // scalars. 4890 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4891 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4892 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4893 bool DoXform = true; 4894 SmallVector<SDNode*, 4> SetCCs; 4895 if (!N0.hasOneUse()) 4896 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 4897 if (DoXform) { 4898 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4899 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4900 LN0->getChain(), 4901 LN0->getBasePtr(), LN0->getPointerInfo(), 4902 N0.getValueType(), 4903 LN0->isVolatile(), LN0->isNonTemporal(), 4904 LN0->getAlignment()); 4905 CombineTo(N, ExtLoad); 4906 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4907 N0.getValueType(), ExtLoad); 4908 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4909 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4910 ISD::ANY_EXTEND); 4911 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4912 } 4913 } 4914 4915 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 4916 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 4917 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 4918 if (N0.getOpcode() == ISD::LOAD && 4919 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 4920 N0.hasOneUse()) { 4921 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4922 EVT MemVT = LN0->getMemoryVT(); 4923 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 4924 VT, LN0->getChain(), LN0->getBasePtr(), 4925 LN0->getPointerInfo(), MemVT, 4926 LN0->isVolatile(), LN0->isNonTemporal(), 4927 LN0->getAlignment()); 4928 CombineTo(N, ExtLoad); 4929 CombineTo(N0.getNode(), 4930 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4931 N0.getValueType(), ExtLoad), 4932 ExtLoad.getValue(1)); 4933 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4934 } 4935 4936 if (N0.getOpcode() == ISD::SETCC) { 4937 // aext(setcc) -> sext_in_reg(vsetcc) for vectors. 4938 // Only do this before legalize for now. 4939 if (VT.isVector() && !LegalOperations) { 4940 EVT N0VT = N0.getOperand(0).getValueType(); 4941 // We know that the # elements of the results is the same as the 4942 // # elements of the compare (and the # elements of the compare result 4943 // for that matter). Check to see that they are the same size. If so, 4944 // we know that the element size of the sext'd result matches the 4945 // element size of the compare operands. 4946 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4947 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4948 N0.getOperand(1), 4949 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4950 // If the desired elements are smaller or larger than the source 4951 // elements we can use a matching integer vector type and then 4952 // truncate/sign extend 4953 else { 4954 EVT MatchingElementType = 4955 EVT::getIntegerVT(*DAG.getContext(), 4956 N0VT.getScalarType().getSizeInBits()); 4957 EVT MatchingVectorType = 4958 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4959 N0VT.getVectorNumElements()); 4960 SDValue VsetCC = 4961 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4962 N0.getOperand(1), 4963 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4964 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4965 } 4966 } 4967 4968 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4969 SDValue SCC = 4970 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4971 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4972 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4973 if (SCC.getNode()) 4974 return SCC; 4975 } 4976 4977 return SDValue(); 4978} 4979 4980/// GetDemandedBits - See if the specified operand can be simplified with the 4981/// knowledge that only the bits specified by Mask are used. If so, return the 4982/// simpler operand, otherwise return a null SDValue. 4983SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 4984 switch (V.getOpcode()) { 4985 default: break; 4986 case ISD::Constant: { 4987 const ConstantSDNode *CV = cast<ConstantSDNode>(V.getNode()); 4988 assert(CV != 0 && "Const value should be ConstSDNode."); 4989 const APInt &CVal = CV->getAPIntValue(); 4990 APInt NewVal = CVal & Mask; 4991 if (NewVal != CVal) { 4992 return DAG.getConstant(NewVal, V.getValueType()); 4993 } 4994 break; 4995 } 4996 case ISD::OR: 4997 case ISD::XOR: 4998 // If the LHS or RHS don't contribute bits to the or, drop them. 4999 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 5000 return V.getOperand(1); 5001 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 5002 return V.getOperand(0); 5003 break; 5004 case ISD::SRL: 5005 // Only look at single-use SRLs. 5006 if (!V.getNode()->hasOneUse()) 5007 break; 5008 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 5009 // See if we can recursively simplify the LHS. 5010 unsigned Amt = RHSC->getZExtValue(); 5011 5012 // Watch out for shift count overflow though. 5013 if (Amt >= Mask.getBitWidth()) break; 5014 APInt NewMask = Mask << Amt; 5015 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 5016 if (SimplifyLHS.getNode()) 5017 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 5018 SimplifyLHS, V.getOperand(1)); 5019 } 5020 } 5021 return SDValue(); 5022} 5023 5024/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 5025/// bits and then truncated to a narrower type and where N is a multiple 5026/// of number of bits of the narrower type, transform it to a narrower load 5027/// from address + N / num of bits of new type. If the result is to be 5028/// extended, also fold the extension to form a extending load. 5029SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 5030 unsigned Opc = N->getOpcode(); 5031 5032 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 5033 SDValue N0 = N->getOperand(0); 5034 EVT VT = N->getValueType(0); 5035 EVT ExtVT = VT; 5036 5037 // This transformation isn't valid for vector loads. 5038 if (VT.isVector()) 5039 return SDValue(); 5040 5041 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then 5042 // extended to VT. 5043 if (Opc == ISD::SIGN_EXTEND_INREG) { 5044 ExtType = ISD::SEXTLOAD; 5045 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 5046 } else if (Opc == ISD::SRL) { 5047 // Another special-case: SRL is basically zero-extending a narrower value. 5048 ExtType = ISD::ZEXTLOAD; 5049 N0 = SDValue(N, 0); 5050 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 5051 if (!N01) return SDValue(); 5052 ExtVT = EVT::getIntegerVT(*DAG.getContext(), 5053 VT.getSizeInBits() - N01->getZExtValue()); 5054 } 5055 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT)) 5056 return SDValue(); 5057 5058 unsigned EVTBits = ExtVT.getSizeInBits(); 5059 5060 // Do not generate loads of non-round integer types since these can 5061 // be expensive (and would be wrong if the type is not byte sized). 5062 if (!ExtVT.isRound()) 5063 return SDValue(); 5064 5065 unsigned ShAmt = 0; 5066 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 5067 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 5068 ShAmt = N01->getZExtValue(); 5069 // Is the shift amount a multiple of size of VT? 5070 if ((ShAmt & (EVTBits-1)) == 0) { 5071 N0 = N0.getOperand(0); 5072 // Is the load width a multiple of size of VT? 5073 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0) 5074 return SDValue(); 5075 } 5076 5077 // At this point, we must have a load or else we can't do the transform. 5078 if (!isa<LoadSDNode>(N0)) return SDValue(); 5079 5080 // Because a SRL must be assumed to *need* to zero-extend the high bits 5081 // (as opposed to anyext the high bits), we can't combine the zextload 5082 // lowering of SRL and an sextload. 5083 if (cast<LoadSDNode>(N0)->getExtensionType() == ISD::SEXTLOAD) 5084 return SDValue(); 5085 5086 // If the shift amount is larger than the input type then we're not 5087 // accessing any of the loaded bytes. If the load was a zextload/extload 5088 // then the result of the shift+trunc is zero/undef (handled elsewhere). 5089 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits()) 5090 return SDValue(); 5091 } 5092 } 5093 5094 // If the load is shifted left (and the result isn't shifted back right), 5095 // we can fold the truncate through the shift. 5096 unsigned ShLeftAmt = 0; 5097 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() && 5098 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) { 5099 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 5100 ShLeftAmt = N01->getZExtValue(); 5101 N0 = N0.getOperand(0); 5102 } 5103 } 5104 5105 // If we haven't found a load, we can't narrow it. Don't transform one with 5106 // multiple uses, this would require adding a new load. 5107 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse()) 5108 return SDValue(); 5109 5110 // Don't change the width of a volatile load. 5111 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5112 if (LN0->isVolatile()) 5113 return SDValue(); 5114 5115 // Verify that we are actually reducing a load width here. 5116 if (LN0->getMemoryVT().getSizeInBits() < EVTBits) 5117 return SDValue(); 5118 5119 // For the transform to be legal, the load must produce only two values 5120 // (the value loaded and the chain). Don't transform a pre-increment 5121 // load, for example, which produces an extra value. Otherwise the 5122 // transformation is not equivalent, and the downstream logic to replace 5123 // uses gets things wrong. 5124 if (LN0->getNumValues() > 2) 5125 return SDValue(); 5126 5127 EVT PtrType = N0.getOperand(1).getValueType(); 5128 5129 if (PtrType == MVT::Untyped || PtrType.isExtended()) 5130 // It's not possible to generate a constant of extended or untyped type. 5131 return SDValue(); 5132 5133 // For big endian targets, we need to adjust the offset to the pointer to 5134 // load the correct bytes. 5135 if (TLI.isBigEndian()) { 5136 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 5137 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits(); 5138 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 5139 } 5140 5141 uint64_t PtrOff = ShAmt / 8; 5142 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 5143 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 5144 PtrType, LN0->getBasePtr(), 5145 DAG.getConstant(PtrOff, PtrType)); 5146 AddToWorkList(NewPtr.getNode()); 5147 5148 SDValue Load; 5149 if (ExtType == ISD::NON_EXTLOAD) 5150 Load = DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 5151 LN0->getPointerInfo().getWithOffset(PtrOff), 5152 LN0->isVolatile(), LN0->isNonTemporal(), 5153 LN0->isInvariant(), NewAlign); 5154 else 5155 Load = DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(),NewPtr, 5156 LN0->getPointerInfo().getWithOffset(PtrOff), 5157 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 5158 NewAlign); 5159 5160 // Replace the old load's chain with the new load's chain. 5161 WorkListRemover DeadNodes(*this); 5162 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1)); 5163 5164 // Shift the result left, if we've swallowed a left shift. 5165 SDValue Result = Load; 5166 if (ShLeftAmt != 0) { 5167 EVT ShImmTy = getShiftAmountTy(Result.getValueType()); 5168 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt)) 5169 ShImmTy = VT; 5170 // If the shift amount is as large as the result size (but, presumably, 5171 // no larger than the source) then the useful bits of the result are 5172 // zero; we can't simply return the shortened shift, because the result 5173 // of that operation is undefined. 5174 if (ShLeftAmt >= VT.getSizeInBits()) 5175 Result = DAG.getConstant(0, VT); 5176 else 5177 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, 5178 Result, DAG.getConstant(ShLeftAmt, ShImmTy)); 5179 } 5180 5181 // Return the new loaded value. 5182 return Result; 5183} 5184 5185SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 5186 SDValue N0 = N->getOperand(0); 5187 SDValue N1 = N->getOperand(1); 5188 EVT VT = N->getValueType(0); 5189 EVT EVT = cast<VTSDNode>(N1)->getVT(); 5190 unsigned VTBits = VT.getScalarType().getSizeInBits(); 5191 unsigned EVTBits = EVT.getScalarType().getSizeInBits(); 5192 5193 // fold (sext_in_reg c1) -> c1 5194 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 5195 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 5196 5197 // If the input is already sign extended, just drop the extension. 5198 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1) 5199 return N0; 5200 5201 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 5202 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 5203 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 5204 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 5205 N0.getOperand(0), N1); 5206 } 5207 5208 // fold (sext_in_reg (sext x)) -> (sext x) 5209 // fold (sext_in_reg (aext x)) -> (sext x) 5210 // if x is small enough. 5211 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 5212 SDValue N00 = N0.getOperand(0); 5213 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits && 5214 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT))) 5215 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 5216 } 5217 5218 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 5219 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 5220 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 5221 5222 // fold operands of sext_in_reg based on knowledge that the top bits are not 5223 // demanded. 5224 if (SimplifyDemandedBits(SDValue(N, 0))) 5225 return SDValue(N, 0); 5226 5227 // fold (sext_in_reg (load x)) -> (smaller sextload x) 5228 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 5229 SDValue NarrowLoad = ReduceLoadWidth(N); 5230 if (NarrowLoad.getNode()) 5231 return NarrowLoad; 5232 5233 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 5234 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 5235 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 5236 if (N0.getOpcode() == ISD::SRL) { 5237 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 5238 if (ShAmt->getZExtValue()+EVTBits <= VTBits) { 5239 // We can turn this into an SRA iff the input to the SRL is already sign 5240 // extended enough. 5241 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 5242 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 5243 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 5244 N0.getOperand(0), N0.getOperand(1)); 5245 } 5246 } 5247 5248 // fold (sext_inreg (extload x)) -> (sextload x) 5249 if (ISD::isEXTLoad(N0.getNode()) && 5250 ISD::isUNINDEXEDLoad(N0.getNode()) && 5251 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 5252 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5253 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 5254 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5255 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 5256 LN0->getChain(), 5257 LN0->getBasePtr(), LN0->getPointerInfo(), 5258 EVT, 5259 LN0->isVolatile(), LN0->isNonTemporal(), 5260 LN0->getAlignment()); 5261 CombineTo(N, ExtLoad); 5262 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 5263 AddToWorkList(ExtLoad.getNode()); 5264 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5265 } 5266 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 5267 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 5268 N0.hasOneUse() && 5269 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 5270 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5271 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 5272 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5273 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 5274 LN0->getChain(), 5275 LN0->getBasePtr(), LN0->getPointerInfo(), 5276 EVT, 5277 LN0->isVolatile(), LN0->isNonTemporal(), 5278 LN0->getAlignment()); 5279 CombineTo(N, ExtLoad); 5280 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 5281 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5282 } 5283 5284 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16)) 5285 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) { 5286 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0), 5287 N0.getOperand(1), false); 5288 if (BSwap.getNode() != 0) 5289 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 5290 BSwap, N1); 5291 } 5292 5293 return SDValue(); 5294} 5295 5296SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 5297 SDValue N0 = N->getOperand(0); 5298 EVT VT = N->getValueType(0); 5299 bool isLE = TLI.isLittleEndian(); 5300 5301 // noop truncate 5302 if (N0.getValueType() == N->getValueType(0)) 5303 return N0; 5304 // fold (truncate c1) -> c1 5305 if (isa<ConstantSDNode>(N0)) 5306 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 5307 // fold (truncate (truncate x)) -> (truncate x) 5308 if (N0.getOpcode() == ISD::TRUNCATE) 5309 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 5310 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 5311 if (N0.getOpcode() == ISD::ZERO_EXTEND || 5312 N0.getOpcode() == ISD::SIGN_EXTEND || 5313 N0.getOpcode() == ISD::ANY_EXTEND) { 5314 if (N0.getOperand(0).getValueType().bitsLT(VT)) 5315 // if the source is smaller than the dest, we still need an extend 5316 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 5317 N0.getOperand(0)); 5318 if (N0.getOperand(0).getValueType().bitsGT(VT)) 5319 // if the source is larger than the dest, than we just need the truncate 5320 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 5321 // if the source and dest are the same type, we can drop both the extend 5322 // and the truncate. 5323 return N0.getOperand(0); 5324 } 5325 5326 // Fold extract-and-trunc into a narrow extract. For example: 5327 // i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1) 5328 // i32 y = TRUNCATE(i64 x) 5329 // -- becomes -- 5330 // v16i8 b = BITCAST (v2i64 val) 5331 // i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8) 5332 // 5333 // Note: We only run this optimization after type legalization (which often 5334 // creates this pattern) and before operation legalization after which 5335 // we need to be more careful about the vector instructions that we generate. 5336 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && 5337 LegalTypes && !LegalOperations && N0->hasOneUse()) { 5338 5339 EVT VecTy = N0.getOperand(0).getValueType(); 5340 EVT ExTy = N0.getValueType(); 5341 EVT TrTy = N->getValueType(0); 5342 5343 unsigned NumElem = VecTy.getVectorNumElements(); 5344 unsigned SizeRatio = ExTy.getSizeInBits()/TrTy.getSizeInBits(); 5345 5346 EVT NVT = EVT::getVectorVT(*DAG.getContext(), TrTy, SizeRatio * NumElem); 5347 assert(NVT.getSizeInBits() == VecTy.getSizeInBits() && "Invalid Size"); 5348 5349 SDValue EltNo = N0->getOperand(1); 5350 if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) { 5351 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5352 EVT IndexTy = N0->getOperand(1).getValueType(); 5353 int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1)); 5354 5355 SDValue V = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 5356 NVT, N0.getOperand(0)); 5357 5358 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 5359 N->getDebugLoc(), TrTy, V, 5360 DAG.getConstant(Index, IndexTy)); 5361 } 5362 } 5363 5364 // Fold a series of buildvector, bitcast, and truncate if possible. 5365 // For example fold 5366 // (2xi32 trunc (bitcast ((4xi32)buildvector x, x, y, y) 2xi64)) to 5367 // (2xi32 (buildvector x, y)). 5368 if (Level == AfterLegalizeVectorOps && VT.isVector() && 5369 N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() && 5370 N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR && 5371 N0.getOperand(0).hasOneUse()) { 5372 5373 SDValue BuildVect = N0.getOperand(0); 5374 EVT BuildVectEltTy = BuildVect.getValueType().getVectorElementType(); 5375 EVT TruncVecEltTy = VT.getVectorElementType(); 5376 5377 // Check that the element types match. 5378 if (BuildVectEltTy == TruncVecEltTy) { 5379 // Now we only need to compute the offset of the truncated elements. 5380 unsigned BuildVecNumElts = BuildVect.getNumOperands(); 5381 unsigned TruncVecNumElts = VT.getVectorNumElements(); 5382 unsigned TruncEltOffset = BuildVecNumElts / TruncVecNumElts; 5383 5384 assert((BuildVecNumElts % TruncVecNumElts) == 0 && 5385 "Invalid number of elements"); 5386 5387 SmallVector<SDValue, 8> Opnds; 5388 for (unsigned i = 0, e = BuildVecNumElts; i != e; i += TruncEltOffset) 5389 Opnds.push_back(BuildVect.getOperand(i)); 5390 5391 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, &Opnds[0], 5392 Opnds.size()); 5393 } 5394 } 5395 5396 // See if we can simplify the input to this truncate through knowledge that 5397 // only the low bits are being used. 5398 // For example "trunc (or (shl x, 8), y)" // -> trunc y 5399 // Currently we only perform this optimization on scalars because vectors 5400 // may have different active low bits. 5401 if (!VT.isVector()) { 5402 SDValue Shorter = 5403 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 5404 VT.getSizeInBits())); 5405 if (Shorter.getNode()) 5406 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 5407 } 5408 // fold (truncate (load x)) -> (smaller load x) 5409 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 5410 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) { 5411 SDValue Reduced = ReduceLoadWidth(N); 5412 if (Reduced.getNode()) 5413 return Reduced; 5414 } 5415 // fold (trunc (concat ... x ...)) -> (concat ..., (trunc x), ...)), 5416 // where ... are all 'undef'. 5417 if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) { 5418 SmallVector<EVT, 8> VTs; 5419 SDValue V; 5420 unsigned Idx = 0; 5421 unsigned NumDefs = 0; 5422 5423 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) { 5424 SDValue X = N0.getOperand(i); 5425 if (X.getOpcode() != ISD::UNDEF) { 5426 V = X; 5427 Idx = i; 5428 NumDefs++; 5429 } 5430 // Stop if more than one members are non-undef. 5431 if (NumDefs > 1) 5432 break; 5433 VTs.push_back(EVT::getVectorVT(*DAG.getContext(), 5434 VT.getVectorElementType(), 5435 X.getValueType().getVectorNumElements())); 5436 } 5437 5438 if (NumDefs == 0) 5439 return DAG.getUNDEF(VT); 5440 5441 if (NumDefs == 1) { 5442 assert(V.getNode() && "The single defined operand is empty!"); 5443 SmallVector<SDValue, 8> Opnds; 5444 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 5445 if (i != Idx) { 5446 Opnds.push_back(DAG.getUNDEF(VTs[i])); 5447 continue; 5448 } 5449 SDValue NV = DAG.getNode(ISD::TRUNCATE, V.getDebugLoc(), VTs[i], V); 5450 AddToWorkList(NV.getNode()); 5451 Opnds.push_back(NV); 5452 } 5453 return DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT, 5454 &Opnds[0], Opnds.size()); 5455 } 5456 } 5457 5458 // Simplify the operands using demanded-bits information. 5459 if (!VT.isVector() && 5460 SimplifyDemandedBits(SDValue(N, 0))) 5461 return SDValue(N, 0); 5462 5463 return SDValue(); 5464} 5465 5466static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 5467 SDValue Elt = N->getOperand(i); 5468 if (Elt.getOpcode() != ISD::MERGE_VALUES) 5469 return Elt.getNode(); 5470 return Elt.getOperand(Elt.getResNo()).getNode(); 5471} 5472 5473/// CombineConsecutiveLoads - build_pair (load, load) -> load 5474/// if load locations are consecutive. 5475SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { 5476 assert(N->getOpcode() == ISD::BUILD_PAIR); 5477 5478 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 5479 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 5480 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() || 5481 LD1->getPointerInfo().getAddrSpace() != 5482 LD2->getPointerInfo().getAddrSpace()) 5483 return SDValue(); 5484 EVT LD1VT = LD1->getValueType(0); 5485 5486 if (ISD::isNON_EXTLoad(LD2) && 5487 LD2->hasOneUse() && 5488 // If both are volatile this would reduce the number of volatile loads. 5489 // If one is volatile it might be ok, but play conservative and bail out. 5490 !LD1->isVolatile() && 5491 !LD2->isVolatile() && 5492 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) { 5493 unsigned Align = LD1->getAlignment(); 5494 unsigned NewAlign = TLI.getDataLayout()-> 5495 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 5496 5497 if (NewAlign <= Align && 5498 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 5499 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 5500 LD1->getBasePtr(), LD1->getPointerInfo(), 5501 false, false, false, Align); 5502 } 5503 5504 return SDValue(); 5505} 5506 5507SDValue DAGCombiner::visitBITCAST(SDNode *N) { 5508 SDValue N0 = N->getOperand(0); 5509 EVT VT = N->getValueType(0); 5510 5511 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 5512 // Only do this before legalize, since afterward the target may be depending 5513 // on the bitconvert. 5514 // First check to see if this is all constant. 5515 if (!LegalTypes && 5516 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 5517 VT.isVector()) { 5518 bool isSimple = true; 5519 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 5520 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 5521 N0.getOperand(i).getOpcode() != ISD::Constant && 5522 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 5523 isSimple = false; 5524 break; 5525 } 5526 5527 EVT DestEltVT = N->getValueType(0).getVectorElementType(); 5528 assert(!DestEltVT.isVector() && 5529 "Element type of vector ValueType must not be vector!"); 5530 if (isSimple) 5531 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT); 5532 } 5533 5534 // If the input is a constant, let getNode fold it. 5535 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 5536 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0); 5537 if (Res.getNode() != N) { 5538 if (!LegalOperations || 5539 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT)) 5540 return Res; 5541 5542 // Folding it resulted in an illegal node, and it's too late to 5543 // do that. Clean up the old node and forego the transformation. 5544 // Ideally this won't happen very often, because instcombine 5545 // and the earlier dagcombine runs (where illegal nodes are 5546 // permitted) should have folded most of them already. 5547 DAG.DeleteNode(Res.getNode()); 5548 } 5549 } 5550 5551 // (conv (conv x, t1), t2) -> (conv x, t2) 5552 if (N0.getOpcode() == ISD::BITCAST) 5553 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, 5554 N0.getOperand(0)); 5555 5556 // fold (conv (load x)) -> (load (conv*)x) 5557 // If the resultant load doesn't need a higher alignment than the original! 5558 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 5559 // Do not change the width of a volatile load. 5560 !cast<LoadSDNode>(N0)->isVolatile() && 5561 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 5562 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5563 unsigned Align = TLI.getDataLayout()-> 5564 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 5565 unsigned OrigAlign = LN0->getAlignment(); 5566 5567 if (Align <= OrigAlign) { 5568 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 5569 LN0->getBasePtr(), LN0->getPointerInfo(), 5570 LN0->isVolatile(), LN0->isNonTemporal(), 5571 LN0->isInvariant(), OrigAlign); 5572 AddToWorkList(N); 5573 CombineTo(N0.getNode(), 5574 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5575 N0.getValueType(), Load), 5576 Load.getValue(1)); 5577 return Load; 5578 } 5579 } 5580 5581 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 5582 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 5583 // This often reduces constant pool loads. 5584 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(VT)) || 5585 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(VT))) && 5586 N0.getNode()->hasOneUse() && VT.isInteger() && 5587 !VT.isVector() && !N0.getValueType().isVector()) { 5588 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT, 5589 N0.getOperand(0)); 5590 AddToWorkList(NewConv.getNode()); 5591 5592 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 5593 if (N0.getOpcode() == ISD::FNEG) 5594 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 5595 NewConv, DAG.getConstant(SignBit, VT)); 5596 assert(N0.getOpcode() == ISD::FABS); 5597 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 5598 NewConv, DAG.getConstant(~SignBit, VT)); 5599 } 5600 5601 // fold (bitconvert (fcopysign cst, x)) -> 5602 // (or (and (bitconvert x), sign), (and cst, (not sign))) 5603 // Note that we don't handle (copysign x, cst) because this can always be 5604 // folded to an fneg or fabs. 5605 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 5606 isa<ConstantFPSDNode>(N0.getOperand(0)) && 5607 VT.isInteger() && !VT.isVector()) { 5608 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 5609 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); 5610 if (isTypeLegal(IntXVT)) { 5611 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5612 IntXVT, N0.getOperand(1)); 5613 AddToWorkList(X.getNode()); 5614 5615 // If X has a different width than the result/lhs, sext it or truncate it. 5616 unsigned VTWidth = VT.getSizeInBits(); 5617 if (OrigXWidth < VTWidth) { 5618 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 5619 AddToWorkList(X.getNode()); 5620 } else if (OrigXWidth > VTWidth) { 5621 // To get the sign bit in the right place, we have to shift it right 5622 // before truncating. 5623 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 5624 X.getValueType(), X, 5625 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 5626 AddToWorkList(X.getNode()); 5627 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 5628 AddToWorkList(X.getNode()); 5629 } 5630 5631 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 5632 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 5633 X, DAG.getConstant(SignBit, VT)); 5634 AddToWorkList(X.getNode()); 5635 5636 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5637 VT, N0.getOperand(0)); 5638 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 5639 Cst, DAG.getConstant(~SignBit, VT)); 5640 AddToWorkList(Cst.getNode()); 5641 5642 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 5643 } 5644 } 5645 5646 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 5647 if (N0.getOpcode() == ISD::BUILD_PAIR) { 5648 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 5649 if (CombineLD.getNode()) 5650 return CombineLD; 5651 } 5652 5653 return SDValue(); 5654} 5655 5656SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 5657 EVT VT = N->getValueType(0); 5658 return CombineConsecutiveLoads(N, VT); 5659} 5660 5661/// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector 5662/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 5663/// destination element value type. 5664SDValue DAGCombiner:: 5665ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { 5666 EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 5667 5668 // If this is already the right type, we're done. 5669 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 5670 5671 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 5672 unsigned DstBitSize = DstEltVT.getSizeInBits(); 5673 5674 // If this is a conversion of N elements of one type to N elements of another 5675 // type, convert each element. This handles FP<->INT cases. 5676 if (SrcBitSize == DstBitSize) { 5677 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 5678 BV->getValueType(0).getVectorNumElements()); 5679 5680 // Due to the FP element handling below calling this routine recursively, 5681 // we can end up with a scalar-to-vector node here. 5682 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR) 5683 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 5684 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 5685 DstEltVT, BV->getOperand(0))); 5686 5687 SmallVector<SDValue, 8> Ops; 5688 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 5689 SDValue Op = BV->getOperand(i); 5690 // If the vector element type is not legal, the BUILD_VECTOR operands 5691 // are promoted and implicitly truncated. Make that explicit here. 5692 if (Op.getValueType() != SrcEltVT) 5693 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 5694 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 5695 DstEltVT, Op)); 5696 AddToWorkList(Ops.back().getNode()); 5697 } 5698 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5699 &Ops[0], Ops.size()); 5700 } 5701 5702 // Otherwise, we're growing or shrinking the elements. To avoid having to 5703 // handle annoying details of growing/shrinking FP values, we convert them to 5704 // int first. 5705 if (SrcEltVT.isFloatingPoint()) { 5706 // Convert the input float vector to a int vector where the elements are the 5707 // same sizes. 5708 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 5709 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); 5710 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode(); 5711 SrcEltVT = IntVT; 5712 } 5713 5714 // Now we know the input is an integer vector. If the output is a FP type, 5715 // convert to integer first, then to FP of the right size. 5716 if (DstEltVT.isFloatingPoint()) { 5717 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 5718 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); 5719 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode(); 5720 5721 // Next, convert to FP elements of the same size. 5722 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT); 5723 } 5724 5725 // Okay, we know the src/dst types are both integers of differing types. 5726 // Handling growing first. 5727 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 5728 if (SrcBitSize < DstBitSize) { 5729 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 5730 5731 SmallVector<SDValue, 8> Ops; 5732 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 5733 i += NumInputsPerOutput) { 5734 bool isLE = TLI.isLittleEndian(); 5735 APInt NewBits = APInt(DstBitSize, 0); 5736 bool EltIsUndef = true; 5737 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 5738 // Shift the previously computed bits over. 5739 NewBits <<= SrcBitSize; 5740 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 5741 if (Op.getOpcode() == ISD::UNDEF) continue; 5742 EltIsUndef = false; 5743 5744 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue(). 5745 zextOrTrunc(SrcBitSize).zext(DstBitSize); 5746 } 5747 5748 if (EltIsUndef) 5749 Ops.push_back(DAG.getUNDEF(DstEltVT)); 5750 else 5751 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 5752 } 5753 5754 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); 5755 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5756 &Ops[0], Ops.size()); 5757 } 5758 5759 // Finally, this must be the case where we are shrinking elements: each input 5760 // turns into multiple outputs. 5761 bool isS2V = ISD::isScalarToVector(BV); 5762 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 5763 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 5764 NumOutputsPerInput*BV->getNumOperands()); 5765 SmallVector<SDValue, 8> Ops; 5766 5767 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 5768 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 5769 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 5770 Ops.push_back(DAG.getUNDEF(DstEltVT)); 5771 continue; 5772 } 5773 5774 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))-> 5775 getAPIntValue().zextOrTrunc(SrcBitSize); 5776 5777 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 5778 APInt ThisVal = OpVal.trunc(DstBitSize); 5779 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 5780 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal) 5781 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 5782 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 5783 Ops[0]); 5784 OpVal = OpVal.lshr(DstBitSize); 5785 } 5786 5787 // For big endian targets, swap the order of the pieces of each element. 5788 if (TLI.isBigEndian()) 5789 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 5790 } 5791 5792 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5793 &Ops[0], Ops.size()); 5794} 5795 5796SDValue DAGCombiner::visitFADD(SDNode *N) { 5797 SDValue N0 = N->getOperand(0); 5798 SDValue N1 = N->getOperand(1); 5799 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5800 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5801 EVT VT = N->getValueType(0); 5802 5803 // fold vector ops 5804 if (VT.isVector()) { 5805 SDValue FoldedVOp = SimplifyVBinOp(N); 5806 if (FoldedVOp.getNode()) return FoldedVOp; 5807 } 5808 5809 // fold (fadd c1, c2) -> c1 + c2 5810 if (N0CFP && N1CFP) 5811 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 5812 // canonicalize constant to RHS 5813 if (N0CFP && !N1CFP) 5814 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 5815 // fold (fadd A, 0) -> A 5816 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 5817 N1CFP->getValueAPF().isZero()) 5818 return N0; 5819 // fold (fadd A, (fneg B)) -> (fsub A, B) 5820 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) && 5821 isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options) == 2) 5822 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 5823 GetNegatedExpression(N1, DAG, LegalOperations)); 5824 // fold (fadd (fneg A), B) -> (fsub B, A) 5825 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) && 5826 isNegatibleForFree(N0, LegalOperations, TLI, &DAG.getTarget().Options) == 2) 5827 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 5828 GetNegatedExpression(N0, DAG, LegalOperations)); 5829 5830 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 5831 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 5832 N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() && 5833 isa<ConstantFPSDNode>(N0.getOperand(1))) 5834 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 5835 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5836 N0.getOperand(1), N1)); 5837 5838 // No FP constant should be created after legalization as Instruction 5839 // Selection pass has hard time in dealing with FP constant. 5840 // 5841 // We don't need test this condition for transformation like following, as 5842 // the DAG being transformed implies it is legal to take FP constant as 5843 // operand. 5844 // 5845 // (fadd (fmul c, x), x) -> (fmul c+1, x) 5846 // 5847 bool AllowNewFpConst = (Level < AfterLegalizeDAG); 5848 5849 // If allow, fold (fadd (fneg x), x) -> 0.0 5850 if (AllowNewFpConst && DAG.getTarget().Options.UnsafeFPMath && 5851 N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1) { 5852 return DAG.getConstantFP(0.0, VT); 5853 } 5854 5855 // If allow, fold (fadd x, (fneg x)) -> 0.0 5856 if (AllowNewFpConst && DAG.getTarget().Options.UnsafeFPMath && 5857 N1.getOpcode() == ISD::FNEG && N1.getOperand(0) == N0) { 5858 return DAG.getConstantFP(0.0, VT); 5859 } 5860 5861 // In unsafe math mode, we can fold chains of FADD's of the same value 5862 // into multiplications. This transform is not safe in general because 5863 // we are reducing the number of rounding steps. 5864 if (DAG.getTarget().Options.UnsafeFPMath && 5865 TLI.isOperationLegalOrCustom(ISD::FMUL, VT) && 5866 !N0CFP && !N1CFP) { 5867 if (N0.getOpcode() == ISD::FMUL) { 5868 ConstantFPSDNode *CFP00 = dyn_cast<ConstantFPSDNode>(N0.getOperand(0)); 5869 ConstantFPSDNode *CFP01 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1)); 5870 5871 // (fadd (fmul c, x), x) -> (fmul c+1, x) 5872 if (CFP00 && !CFP01 && N0.getOperand(1) == N1) { 5873 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5874 SDValue(CFP00, 0), 5875 DAG.getConstantFP(1.0, VT)); 5876 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5877 N1, NewCFP); 5878 } 5879 5880 // (fadd (fmul x, c), x) -> (fmul c+1, x) 5881 if (CFP01 && !CFP00 && N0.getOperand(0) == N1) { 5882 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5883 SDValue(CFP01, 0), 5884 DAG.getConstantFP(1.0, VT)); 5885 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5886 N1, NewCFP); 5887 } 5888 5889 // (fadd (fmul c, x), (fadd x, x)) -> (fmul c+2, x) 5890 if (CFP00 && !CFP01 && N1.getOpcode() == ISD::FADD && 5891 N1.getOperand(0) == N1.getOperand(1) && 5892 N0.getOperand(1) == N1.getOperand(0)) { 5893 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5894 SDValue(CFP00, 0), 5895 DAG.getConstantFP(2.0, VT)); 5896 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5897 N0.getOperand(1), NewCFP); 5898 } 5899 5900 // (fadd (fmul x, c), (fadd x, x)) -> (fmul c+2, x) 5901 if (CFP01 && !CFP00 && N1.getOpcode() == ISD::FADD && 5902 N1.getOperand(0) == N1.getOperand(1) && 5903 N0.getOperand(0) == N1.getOperand(0)) { 5904 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5905 SDValue(CFP01, 0), 5906 DAG.getConstantFP(2.0, VT)); 5907 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5908 N0.getOperand(0), NewCFP); 5909 } 5910 } 5911 5912 if (N1.getOpcode() == ISD::FMUL) { 5913 ConstantFPSDNode *CFP10 = dyn_cast<ConstantFPSDNode>(N1.getOperand(0)); 5914 ConstantFPSDNode *CFP11 = dyn_cast<ConstantFPSDNode>(N1.getOperand(1)); 5915 5916 // (fadd x, (fmul c, x)) -> (fmul c+1, x) 5917 if (CFP10 && !CFP11 && N1.getOperand(1) == N0) { 5918 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5919 SDValue(CFP10, 0), 5920 DAG.getConstantFP(1.0, VT)); 5921 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5922 N0, NewCFP); 5923 } 5924 5925 // (fadd x, (fmul x, c)) -> (fmul c+1, x) 5926 if (CFP11 && !CFP10 && N1.getOperand(0) == N0) { 5927 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5928 SDValue(CFP11, 0), 5929 DAG.getConstantFP(1.0, VT)); 5930 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5931 N0, NewCFP); 5932 } 5933 5934 5935 // (fadd (fadd x, x), (fmul c, x)) -> (fmul c+2, x) 5936 if (CFP10 && !CFP11 && N1.getOpcode() == ISD::FADD && 5937 N1.getOperand(0) == N1.getOperand(1) && 5938 N0.getOperand(1) == N1.getOperand(0)) { 5939 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5940 SDValue(CFP10, 0), 5941 DAG.getConstantFP(2.0, VT)); 5942 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5943 N0.getOperand(1), NewCFP); 5944 } 5945 5946 // (fadd (fadd x, x), (fmul x, c)) -> (fmul c+2, x) 5947 if (CFP11 && !CFP10 && N1.getOpcode() == ISD::FADD && 5948 N1.getOperand(0) == N1.getOperand(1) && 5949 N0.getOperand(0) == N1.getOperand(0)) { 5950 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5951 SDValue(CFP11, 0), 5952 DAG.getConstantFP(2.0, VT)); 5953 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5954 N0.getOperand(0), NewCFP); 5955 } 5956 } 5957 5958 if (N0.getOpcode() == ISD::FADD && AllowNewFpConst) { 5959 ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N0.getOperand(0)); 5960 // (fadd (fadd x, x), x) -> (fmul 3.0, x) 5961 if (!CFP && N0.getOperand(0) == N0.getOperand(1) && 5962 (N0.getOperand(0) == N1)) { 5963 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5964 N1, DAG.getConstantFP(3.0, VT)); 5965 } 5966 } 5967 5968 if (N1.getOpcode() == ISD::FADD && AllowNewFpConst) { 5969 ConstantFPSDNode *CFP10 = dyn_cast<ConstantFPSDNode>(N1.getOperand(0)); 5970 // (fadd x, (fadd x, x)) -> (fmul 3.0, x) 5971 if (!CFP10 && N1.getOperand(0) == N1.getOperand(1) && 5972 N1.getOperand(0) == N0) { 5973 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5974 N0, DAG.getConstantFP(3.0, VT)); 5975 } 5976 } 5977 5978 // (fadd (fadd x, x), (fadd x, x)) -> (fmul 4.0, x) 5979 if (AllowNewFpConst && 5980 N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD && 5981 N0.getOperand(0) == N0.getOperand(1) && 5982 N1.getOperand(0) == N1.getOperand(1) && 5983 N0.getOperand(0) == N1.getOperand(0)) { 5984 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5985 N0.getOperand(0), 5986 DAG.getConstantFP(4.0, VT)); 5987 } 5988 } 5989 5990 // FADD -> FMA combines: 5991 if ((DAG.getTarget().Options.AllowFPOpFusion == FPOpFusion::Fast || 5992 DAG.getTarget().Options.UnsafeFPMath) && 5993 DAG.getTarget().getTargetLowering()->isFMAFasterThanMulAndAdd(VT) && 5994 TLI.isOperationLegalOrCustom(ISD::FMA, VT)) { 5995 5996 // fold (fadd (fmul x, y), z) -> (fma x, y, z) 5997 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse()) { 5998 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, 5999 N0.getOperand(0), N0.getOperand(1), N1); 6000 } 6001 6002 // fold (fadd x, (fmul y, z)) -> (fma y, z, x) 6003 // Note: Commutes FADD operands. 6004 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse()) { 6005 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, 6006 N1.getOperand(0), N1.getOperand(1), N0); 6007 } 6008 } 6009 6010 return SDValue(); 6011} 6012 6013SDValue DAGCombiner::visitFSUB(SDNode *N) { 6014 SDValue N0 = N->getOperand(0); 6015 SDValue N1 = N->getOperand(1); 6016 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6017 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6018 EVT VT = N->getValueType(0); 6019 DebugLoc dl = N->getDebugLoc(); 6020 6021 // fold vector ops 6022 if (VT.isVector()) { 6023 SDValue FoldedVOp = SimplifyVBinOp(N); 6024 if (FoldedVOp.getNode()) return FoldedVOp; 6025 } 6026 6027 // fold (fsub c1, c2) -> c1-c2 6028 if (N0CFP && N1CFP) 6029 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 6030 // fold (fsub A, 0) -> A 6031 if (DAG.getTarget().Options.UnsafeFPMath && 6032 N1CFP && N1CFP->getValueAPF().isZero()) 6033 return N0; 6034 // fold (fsub 0, B) -> -B 6035 if (DAG.getTarget().Options.UnsafeFPMath && 6036 N0CFP && N0CFP->getValueAPF().isZero()) { 6037 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options)) 6038 return GetNegatedExpression(N1, DAG, LegalOperations); 6039 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 6040 return DAG.getNode(ISD::FNEG, dl, VT, N1); 6041 } 6042 // fold (fsub A, (fneg B)) -> (fadd A, B) 6043 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options)) 6044 return DAG.getNode(ISD::FADD, dl, VT, N0, 6045 GetNegatedExpression(N1, DAG, LegalOperations)); 6046 6047 // If 'unsafe math' is enabled, fold 6048 // (fsub x, x) -> 0.0 & 6049 // (fsub x, (fadd x, y)) -> (fneg y) & 6050 // (fsub x, (fadd y, x)) -> (fneg y) 6051 if (DAG.getTarget().Options.UnsafeFPMath) { 6052 if (N0 == N1) 6053 return DAG.getConstantFP(0.0f, VT); 6054 6055 if (N1.getOpcode() == ISD::FADD) { 6056 SDValue N10 = N1->getOperand(0); 6057 SDValue N11 = N1->getOperand(1); 6058 6059 if (N10 == N0 && isNegatibleForFree(N11, LegalOperations, TLI, 6060 &DAG.getTarget().Options)) 6061 return GetNegatedExpression(N11, DAG, LegalOperations); 6062 else if (N11 == N0 && isNegatibleForFree(N10, LegalOperations, TLI, 6063 &DAG.getTarget().Options)) 6064 return GetNegatedExpression(N10, DAG, LegalOperations); 6065 } 6066 } 6067 6068 // FSUB -> FMA combines: 6069 if ((DAG.getTarget().Options.AllowFPOpFusion == FPOpFusion::Fast || 6070 DAG.getTarget().Options.UnsafeFPMath) && 6071 DAG.getTarget().getTargetLowering()->isFMAFasterThanMulAndAdd(VT) && 6072 TLI.isOperationLegalOrCustom(ISD::FMA, VT)) { 6073 6074 // fold (fsub (fmul x, y), z) -> (fma x, y, (fneg z)) 6075 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse()) { 6076 return DAG.getNode(ISD::FMA, dl, VT, 6077 N0.getOperand(0), N0.getOperand(1), 6078 DAG.getNode(ISD::FNEG, dl, VT, N1)); 6079 } 6080 6081 // fold (fsub x, (fmul y, z)) -> (fma (fneg y), z, x) 6082 // Note: Commutes FSUB operands. 6083 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse()) { 6084 return DAG.getNode(ISD::FMA, dl, VT, 6085 DAG.getNode(ISD::FNEG, dl, VT, 6086 N1.getOperand(0)), 6087 N1.getOperand(1), N0); 6088 } 6089 6090 // fold (fsub (-(fmul, x, y)), z) -> (fma (fneg x), y, (fneg z)) 6091 if (N0.getOpcode() == ISD::FNEG && 6092 N0.getOperand(0).getOpcode() == ISD::FMUL && 6093 N0->hasOneUse() && N0.getOperand(0).hasOneUse()) { 6094 SDValue N00 = N0.getOperand(0).getOperand(0); 6095 SDValue N01 = N0.getOperand(0).getOperand(1); 6096 return DAG.getNode(ISD::FMA, dl, VT, 6097 DAG.getNode(ISD::FNEG, dl, VT, N00), N01, 6098 DAG.getNode(ISD::FNEG, dl, VT, N1)); 6099 } 6100 } 6101 6102 return SDValue(); 6103} 6104 6105SDValue DAGCombiner::visitFMUL(SDNode *N) { 6106 SDValue N0 = N->getOperand(0); 6107 SDValue N1 = N->getOperand(1); 6108 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6109 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6110 EVT VT = N->getValueType(0); 6111 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 6112 6113 // fold vector ops 6114 if (VT.isVector()) { 6115 SDValue FoldedVOp = SimplifyVBinOp(N); 6116 if (FoldedVOp.getNode()) return FoldedVOp; 6117 } 6118 6119 // fold (fmul c1, c2) -> c1*c2 6120 if (N0CFP && N1CFP) 6121 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 6122 // canonicalize constant to RHS 6123 if (N0CFP && !N1CFP) 6124 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 6125 // fold (fmul A, 0) -> 0 6126 if (DAG.getTarget().Options.UnsafeFPMath && 6127 N1CFP && N1CFP->getValueAPF().isZero()) 6128 return N1; 6129 // fold (fmul A, 0) -> 0, vector edition. 6130 if (DAG.getTarget().Options.UnsafeFPMath && 6131 ISD::isBuildVectorAllZeros(N1.getNode())) 6132 return N1; 6133 // fold (fmul A, 1.0) -> A 6134 if (N1CFP && N1CFP->isExactlyValue(1.0)) 6135 return N0; 6136 // fold (fmul X, 2.0) -> (fadd X, X) 6137 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 6138 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 6139 // fold (fmul X, -1.0) -> (fneg X) 6140 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 6141 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 6142 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 6143 6144 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 6145 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, 6146 &DAG.getTarget().Options)) { 6147 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, 6148 &DAG.getTarget().Options)) { 6149 // Both can be negated for free, check to see if at least one is cheaper 6150 // negated. 6151 if (LHSNeg == 2 || RHSNeg == 2) 6152 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 6153 GetNegatedExpression(N0, DAG, LegalOperations), 6154 GetNegatedExpression(N1, DAG, LegalOperations)); 6155 } 6156 } 6157 6158 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 6159 if (DAG.getTarget().Options.UnsafeFPMath && 6160 N1CFP && N0.getOpcode() == ISD::FMUL && 6161 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 6162 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 6163 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 6164 N0.getOperand(1), N1)); 6165 6166 return SDValue(); 6167} 6168 6169SDValue DAGCombiner::visitFMA(SDNode *N) { 6170 SDValue N0 = N->getOperand(0); 6171 SDValue N1 = N->getOperand(1); 6172 SDValue N2 = N->getOperand(2); 6173 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6174 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6175 EVT VT = N->getValueType(0); 6176 DebugLoc dl = N->getDebugLoc(); 6177 6178 if (DAG.getTarget().Options.UnsafeFPMath) { 6179 if (N0CFP && N0CFP->isZero()) 6180 return N2; 6181 if (N1CFP && N1CFP->isZero()) 6182 return N2; 6183 } 6184 if (N0CFP && N0CFP->isExactlyValue(1.0)) 6185 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N2); 6186 if (N1CFP && N1CFP->isExactlyValue(1.0)) 6187 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N2); 6188 6189 // Canonicalize (fma c, x, y) -> (fma x, c, y) 6190 if (N0CFP && !N1CFP) 6191 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, N1, N0, N2); 6192 6193 // (fma x, c1, (fmul x, c2)) -> (fmul x, c1+c2) 6194 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 6195 N2.getOpcode() == ISD::FMUL && 6196 N0 == N2.getOperand(0) && 6197 N2.getOperand(1).getOpcode() == ISD::ConstantFP) { 6198 return DAG.getNode(ISD::FMUL, dl, VT, N0, 6199 DAG.getNode(ISD::FADD, dl, VT, N1, N2.getOperand(1))); 6200 } 6201 6202 6203 // (fma (fmul x, c1), c2, y) -> (fma x, c1*c2, y) 6204 if (DAG.getTarget().Options.UnsafeFPMath && 6205 N0.getOpcode() == ISD::FMUL && N1CFP && 6206 N0.getOperand(1).getOpcode() == ISD::ConstantFP) { 6207 return DAG.getNode(ISD::FMA, dl, VT, 6208 N0.getOperand(0), 6209 DAG.getNode(ISD::FMUL, dl, VT, N1, N0.getOperand(1)), 6210 N2); 6211 } 6212 6213 // (fma x, 1, y) -> (fadd x, y) 6214 // (fma x, -1, y) -> (fadd (fneg x), y) 6215 if (N1CFP) { 6216 if (N1CFP->isExactlyValue(1.0)) 6217 return DAG.getNode(ISD::FADD, dl, VT, N0, N2); 6218 6219 if (N1CFP->isExactlyValue(-1.0) && 6220 (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))) { 6221 SDValue RHSNeg = DAG.getNode(ISD::FNEG, dl, VT, N0); 6222 AddToWorkList(RHSNeg.getNode()); 6223 return DAG.getNode(ISD::FADD, dl, VT, N2, RHSNeg); 6224 } 6225 } 6226 6227 // (fma x, c, x) -> (fmul x, (c+1)) 6228 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && N0 == N2) { 6229 return DAG.getNode(ISD::FMUL, dl, VT, 6230 N0, 6231 DAG.getNode(ISD::FADD, dl, VT, 6232 N1, DAG.getConstantFP(1.0, VT))); 6233 } 6234 6235 // (fma x, c, (fneg x)) -> (fmul x, (c-1)) 6236 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 6237 N2.getOpcode() == ISD::FNEG && N2.getOperand(0) == N0) { 6238 return DAG.getNode(ISD::FMUL, dl, VT, 6239 N0, 6240 DAG.getNode(ISD::FADD, dl, VT, 6241 N1, DAG.getConstantFP(-1.0, VT))); 6242 } 6243 6244 6245 return SDValue(); 6246} 6247 6248SDValue DAGCombiner::visitFDIV(SDNode *N) { 6249 SDValue N0 = N->getOperand(0); 6250 SDValue N1 = N->getOperand(1); 6251 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6252 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6253 EVT VT = N->getValueType(0); 6254 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 6255 6256 // fold vector ops 6257 if (VT.isVector()) { 6258 SDValue FoldedVOp = SimplifyVBinOp(N); 6259 if (FoldedVOp.getNode()) return FoldedVOp; 6260 } 6261 6262 // fold (fdiv c1, c2) -> c1/c2 6263 if (N0CFP && N1CFP) 6264 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 6265 6266 // fold (fdiv X, c2) -> fmul X, 1/c2 if losing precision is acceptable. 6267 if (N1CFP && DAG.getTarget().Options.UnsafeFPMath) { 6268 // Compute the reciprocal 1.0 / c2. 6269 APFloat N1APF = N1CFP->getValueAPF(); 6270 APFloat Recip(N1APF.getSemantics(), 1); // 1.0 6271 APFloat::opStatus st = Recip.divide(N1APF, APFloat::rmNearestTiesToEven); 6272 // Only do the transform if the reciprocal is a legal fp immediate that 6273 // isn't too nasty (eg NaN, denormal, ...). 6274 if ((st == APFloat::opOK || st == APFloat::opInexact) && // Not too nasty 6275 (!LegalOperations || 6276 // FIXME: custom lowering of ConstantFP might fail (see e.g. ARM 6277 // backend)... we should handle this gracefully after Legalize. 6278 // TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT) || 6279 TLI.isOperationLegal(llvm::ISD::ConstantFP, VT) || 6280 TLI.isFPImmLegal(Recip, VT))) 6281 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, 6282 DAG.getConstantFP(Recip, VT)); 6283 } 6284 6285 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 6286 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, 6287 &DAG.getTarget().Options)) { 6288 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, 6289 &DAG.getTarget().Options)) { 6290 // Both can be negated for free, check to see if at least one is cheaper 6291 // negated. 6292 if (LHSNeg == 2 || RHSNeg == 2) 6293 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 6294 GetNegatedExpression(N0, DAG, LegalOperations), 6295 GetNegatedExpression(N1, DAG, LegalOperations)); 6296 } 6297 } 6298 6299 return SDValue(); 6300} 6301 6302SDValue DAGCombiner::visitFREM(SDNode *N) { 6303 SDValue N0 = N->getOperand(0); 6304 SDValue N1 = N->getOperand(1); 6305 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6306 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6307 EVT VT = N->getValueType(0); 6308 6309 // fold (frem c1, c2) -> fmod(c1,c2) 6310 if (N0CFP && N1CFP) 6311 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 6312 6313 return SDValue(); 6314} 6315 6316SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 6317 SDValue N0 = N->getOperand(0); 6318 SDValue N1 = N->getOperand(1); 6319 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6320 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6321 EVT VT = N->getValueType(0); 6322 6323 if (N0CFP && N1CFP) // Constant fold 6324 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 6325 6326 if (N1CFP) { 6327 const APFloat& V = N1CFP->getValueAPF(); 6328 // copysign(x, c1) -> fabs(x) iff ispos(c1) 6329 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 6330 if (!V.isNegative()) { 6331 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 6332 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 6333 } else { 6334 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 6335 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 6336 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 6337 } 6338 } 6339 6340 // copysign(fabs(x), y) -> copysign(x, y) 6341 // copysign(fneg(x), y) -> copysign(x, y) 6342 // copysign(copysign(x,z), y) -> copysign(x, y) 6343 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 6344 N0.getOpcode() == ISD::FCOPYSIGN) 6345 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 6346 N0.getOperand(0), N1); 6347 6348 // copysign(x, abs(y)) -> abs(x) 6349 if (N1.getOpcode() == ISD::FABS) 6350 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 6351 6352 // copysign(x, copysign(y,z)) -> copysign(x, z) 6353 if (N1.getOpcode() == ISD::FCOPYSIGN) 6354 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 6355 N0, N1.getOperand(1)); 6356 6357 // copysign(x, fp_extend(y)) -> copysign(x, y) 6358 // copysign(x, fp_round(y)) -> copysign(x, y) 6359 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 6360 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 6361 N0, N1.getOperand(0)); 6362 6363 return SDValue(); 6364} 6365 6366SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 6367 SDValue N0 = N->getOperand(0); 6368 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 6369 EVT VT = N->getValueType(0); 6370 EVT OpVT = N0.getValueType(); 6371 6372 // fold (sint_to_fp c1) -> c1fp 6373 if (N0C && 6374 // ...but only if the target supports immediate floating-point values 6375 (!LegalOperations || 6376 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 6377 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 6378 6379 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 6380 // but UINT_TO_FP is legal on this target, try to convert. 6381 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 6382 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 6383 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 6384 if (DAG.SignBitIsZero(N0)) 6385 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 6386 } 6387 6388 // The next optimizations are desireable only if SELECT_CC can be lowered. 6389 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 6390 // having to say they don't support SELECT_CC on every type the DAG knows 6391 // about, since there is no way to mark an opcode illegal at all value types 6392 // (See also visitSELECT) 6393 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) { 6394 // fold (sint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc) 6395 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 && 6396 !VT.isVector() && 6397 (!LegalOperations || 6398 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) { 6399 SDValue Ops[] = 6400 { N0.getOperand(0), N0.getOperand(1), 6401 DAG.getConstantFP(-1.0, VT) , DAG.getConstantFP(0.0, VT), 6402 N0.getOperand(2) }; 6403 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5); 6404 } 6405 6406 // fold (sint_to_fp (zext (setcc x, y, cc))) -> 6407 // (select_cc x, y, 1.0, 0.0,, cc) 6408 if (N0.getOpcode() == ISD::ZERO_EXTEND && 6409 N0.getOperand(0).getOpcode() == ISD::SETCC &&!VT.isVector() && 6410 (!LegalOperations || 6411 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) { 6412 SDValue Ops[] = 6413 { N0.getOperand(0).getOperand(0), N0.getOperand(0).getOperand(1), 6414 DAG.getConstantFP(1.0, VT) , DAG.getConstantFP(0.0, VT), 6415 N0.getOperand(0).getOperand(2) }; 6416 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5); 6417 } 6418 } 6419 6420 return SDValue(); 6421} 6422 6423SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 6424 SDValue N0 = N->getOperand(0); 6425 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 6426 EVT VT = N->getValueType(0); 6427 EVT OpVT = N0.getValueType(); 6428 6429 // fold (uint_to_fp c1) -> c1fp 6430 if (N0C && 6431 // ...but only if the target supports immediate floating-point values 6432 (!LegalOperations || 6433 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 6434 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 6435 6436 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 6437 // but SINT_TO_FP is legal on this target, try to convert. 6438 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 6439 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 6440 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 6441 if (DAG.SignBitIsZero(N0)) 6442 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 6443 } 6444 6445 // The next optimizations are desireable only if SELECT_CC can be lowered. 6446 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 6447 // having to say they don't support SELECT_CC on every type the DAG knows 6448 // about, since there is no way to mark an opcode illegal at all value types 6449 // (See also visitSELECT) 6450 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) { 6451 // fold (uint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc) 6452 6453 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() && 6454 (!LegalOperations || 6455 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) { 6456 SDValue Ops[] = 6457 { N0.getOperand(0), N0.getOperand(1), 6458 DAG.getConstantFP(1.0, VT), DAG.getConstantFP(0.0, VT), 6459 N0.getOperand(2) }; 6460 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5); 6461 } 6462 } 6463 6464 return SDValue(); 6465} 6466 6467SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 6468 SDValue N0 = N->getOperand(0); 6469 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6470 EVT VT = N->getValueType(0); 6471 6472 // fold (fp_to_sint c1fp) -> c1 6473 if (N0CFP) 6474 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 6475 6476 return SDValue(); 6477} 6478 6479SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 6480 SDValue N0 = N->getOperand(0); 6481 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6482 EVT VT = N->getValueType(0); 6483 6484 // fold (fp_to_uint c1fp) -> c1 6485 if (N0CFP) 6486 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 6487 6488 return SDValue(); 6489} 6490 6491SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 6492 SDValue N0 = N->getOperand(0); 6493 SDValue N1 = N->getOperand(1); 6494 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6495 EVT VT = N->getValueType(0); 6496 6497 // fold (fp_round c1fp) -> c1fp 6498 if (N0CFP) 6499 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 6500 6501 // fold (fp_round (fp_extend x)) -> x 6502 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 6503 return N0.getOperand(0); 6504 6505 // fold (fp_round (fp_round x)) -> (fp_round x) 6506 if (N0.getOpcode() == ISD::FP_ROUND) { 6507 // This is a value preserving truncation if both round's are. 6508 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 6509 N0.getNode()->getConstantOperandVal(1) == 1; 6510 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 6511 DAG.getIntPtrConstant(IsTrunc)); 6512 } 6513 6514 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 6515 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 6516 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 6517 N0.getOperand(0), N1); 6518 AddToWorkList(Tmp.getNode()); 6519 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 6520 Tmp, N0.getOperand(1)); 6521 } 6522 6523 return SDValue(); 6524} 6525 6526SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 6527 SDValue N0 = N->getOperand(0); 6528 EVT VT = N->getValueType(0); 6529 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 6530 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6531 6532 // fold (fp_round_inreg c1fp) -> c1fp 6533 if (N0CFP && isTypeLegal(EVT)) { 6534 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 6535 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 6536 } 6537 6538 return SDValue(); 6539} 6540 6541SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 6542 SDValue N0 = N->getOperand(0); 6543 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6544 EVT VT = N->getValueType(0); 6545 6546 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 6547 if (N->hasOneUse() && 6548 N->use_begin()->getOpcode() == ISD::FP_ROUND) 6549 return SDValue(); 6550 6551 // fold (fp_extend c1fp) -> c1fp 6552 if (N0CFP) 6553 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 6554 6555 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 6556 // value of X. 6557 if (N0.getOpcode() == ISD::FP_ROUND 6558 && N0.getNode()->getConstantOperandVal(1) == 1) { 6559 SDValue In = N0.getOperand(0); 6560 if (In.getValueType() == VT) return In; 6561 if (VT.bitsLT(In.getValueType())) 6562 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 6563 In, N0.getOperand(1)); 6564 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 6565 } 6566 6567 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 6568 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 6569 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 6570 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 6571 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 6572 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 6573 LN0->getChain(), 6574 LN0->getBasePtr(), LN0->getPointerInfo(), 6575 N0.getValueType(), 6576 LN0->isVolatile(), LN0->isNonTemporal(), 6577 LN0->getAlignment()); 6578 CombineTo(N, ExtLoad); 6579 CombineTo(N0.getNode(), 6580 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 6581 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 6582 ExtLoad.getValue(1)); 6583 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6584 } 6585 6586 return SDValue(); 6587} 6588 6589SDValue DAGCombiner::visitFNEG(SDNode *N) { 6590 SDValue N0 = N->getOperand(0); 6591 EVT VT = N->getValueType(0); 6592 6593 if (VT.isVector()) { 6594 SDValue FoldedVOp = SimplifyVUnaryOp(N); 6595 if (FoldedVOp.getNode()) return FoldedVOp; 6596 } 6597 6598 if (isNegatibleForFree(N0, LegalOperations, DAG.getTargetLoweringInfo(), 6599 &DAG.getTarget().Options)) 6600 return GetNegatedExpression(N0, DAG, LegalOperations); 6601 6602 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 6603 // constant pool values. 6604 if (!TLI.isFNegFree(VT) && N0.getOpcode() == ISD::BITCAST && 6605 !VT.isVector() && 6606 N0.getNode()->hasOneUse() && 6607 N0.getOperand(0).getValueType().isInteger()) { 6608 SDValue Int = N0.getOperand(0); 6609 EVT IntVT = Int.getValueType(); 6610 if (IntVT.isInteger() && !IntVT.isVector()) { 6611 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 6612 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 6613 AddToWorkList(Int.getNode()); 6614 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 6615 VT, Int); 6616 } 6617 } 6618 6619 // (fneg (fmul c, x)) -> (fmul -c, x) 6620 if (N0.getOpcode() == ISD::FMUL) { 6621 ConstantFPSDNode *CFP1 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1)); 6622 if (CFP1) { 6623 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 6624 N0.getOperand(0), 6625 DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 6626 N0.getOperand(1))); 6627 } 6628 } 6629 6630 return SDValue(); 6631} 6632 6633SDValue DAGCombiner::visitFCEIL(SDNode *N) { 6634 SDValue N0 = N->getOperand(0); 6635 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6636 EVT VT = N->getValueType(0); 6637 6638 // fold (fceil c1) -> fceil(c1) 6639 if (N0CFP) 6640 return DAG.getNode(ISD::FCEIL, N->getDebugLoc(), VT, N0); 6641 6642 return SDValue(); 6643} 6644 6645SDValue DAGCombiner::visitFTRUNC(SDNode *N) { 6646 SDValue N0 = N->getOperand(0); 6647 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6648 EVT VT = N->getValueType(0); 6649 6650 // fold (ftrunc c1) -> ftrunc(c1) 6651 if (N0CFP) 6652 return DAG.getNode(ISD::FTRUNC, N->getDebugLoc(), VT, N0); 6653 6654 return SDValue(); 6655} 6656 6657SDValue DAGCombiner::visitFFLOOR(SDNode *N) { 6658 SDValue N0 = N->getOperand(0); 6659 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6660 EVT VT = N->getValueType(0); 6661 6662 // fold (ffloor c1) -> ffloor(c1) 6663 if (N0CFP) 6664 return DAG.getNode(ISD::FFLOOR, N->getDebugLoc(), VT, N0); 6665 6666 return SDValue(); 6667} 6668 6669SDValue DAGCombiner::visitFABS(SDNode *N) { 6670 SDValue N0 = N->getOperand(0); 6671 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6672 EVT VT = N->getValueType(0); 6673 6674 if (VT.isVector()) { 6675 SDValue FoldedVOp = SimplifyVUnaryOp(N); 6676 if (FoldedVOp.getNode()) return FoldedVOp; 6677 } 6678 6679 // fold (fabs c1) -> fabs(c1) 6680 if (N0CFP) 6681 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 6682 // fold (fabs (fabs x)) -> (fabs x) 6683 if (N0.getOpcode() == ISD::FABS) 6684 return N->getOperand(0); 6685 // fold (fabs (fneg x)) -> (fabs x) 6686 // fold (fabs (fcopysign x, y)) -> (fabs x) 6687 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 6688 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 6689 6690 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 6691 // constant pool values. 6692 if (!TLI.isFAbsFree(VT) && 6693 N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() && 6694 N0.getOperand(0).getValueType().isInteger() && 6695 !N0.getOperand(0).getValueType().isVector()) { 6696 SDValue Int = N0.getOperand(0); 6697 EVT IntVT = Int.getValueType(); 6698 if (IntVT.isInteger() && !IntVT.isVector()) { 6699 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 6700 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 6701 AddToWorkList(Int.getNode()); 6702 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 6703 N->getValueType(0), Int); 6704 } 6705 } 6706 6707 return SDValue(); 6708} 6709 6710SDValue DAGCombiner::visitBRCOND(SDNode *N) { 6711 SDValue Chain = N->getOperand(0); 6712 SDValue N1 = N->getOperand(1); 6713 SDValue N2 = N->getOperand(2); 6714 6715 // If N is a constant we could fold this into a fallthrough or unconditional 6716 // branch. However that doesn't happen very often in normal code, because 6717 // Instcombine/SimplifyCFG should have handled the available opportunities. 6718 // If we did this folding here, it would be necessary to update the 6719 // MachineBasicBlock CFG, which is awkward. 6720 6721 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 6722 // on the target. 6723 if (N1.getOpcode() == ISD::SETCC && 6724 TLI.isOperationLegalOrCustom(ISD::BR_CC, 6725 N1.getOperand(0).getValueType())) { 6726 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 6727 Chain, N1.getOperand(2), 6728 N1.getOperand(0), N1.getOperand(1), N2); 6729 } 6730 6731 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) || 6732 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) && 6733 (N1.getOperand(0).hasOneUse() && 6734 N1.getOperand(0).getOpcode() == ISD::SRL))) { 6735 SDNode *Trunc = 0; 6736 if (N1.getOpcode() == ISD::TRUNCATE) { 6737 // Look pass the truncate. 6738 Trunc = N1.getNode(); 6739 N1 = N1.getOperand(0); 6740 } 6741 6742 // Match this pattern so that we can generate simpler code: 6743 // 6744 // %a = ... 6745 // %b = and i32 %a, 2 6746 // %c = srl i32 %b, 1 6747 // brcond i32 %c ... 6748 // 6749 // into 6750 // 6751 // %a = ... 6752 // %b = and i32 %a, 2 6753 // %c = setcc eq %b, 0 6754 // brcond %c ... 6755 // 6756 // This applies only when the AND constant value has one bit set and the 6757 // SRL constant is equal to the log2 of the AND constant. The back-end is 6758 // smart enough to convert the result into a TEST/JMP sequence. 6759 SDValue Op0 = N1.getOperand(0); 6760 SDValue Op1 = N1.getOperand(1); 6761 6762 if (Op0.getOpcode() == ISD::AND && 6763 Op1.getOpcode() == ISD::Constant) { 6764 SDValue AndOp1 = Op0.getOperand(1); 6765 6766 if (AndOp1.getOpcode() == ISD::Constant) { 6767 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 6768 6769 if (AndConst.isPowerOf2() && 6770 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 6771 SDValue SetCC = 6772 DAG.getSetCC(N->getDebugLoc(), 6773 TLI.getSetCCResultType(Op0.getValueType()), 6774 Op0, DAG.getConstant(0, Op0.getValueType()), 6775 ISD::SETNE); 6776 6777 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6778 MVT::Other, Chain, SetCC, N2); 6779 // Don't add the new BRCond into the worklist or else SimplifySelectCC 6780 // will convert it back to (X & C1) >> C2. 6781 CombineTo(N, NewBRCond, false); 6782 // Truncate is dead. 6783 if (Trunc) { 6784 removeFromWorkList(Trunc); 6785 DAG.DeleteNode(Trunc); 6786 } 6787 // Replace the uses of SRL with SETCC 6788 WorkListRemover DeadNodes(*this); 6789 DAG.ReplaceAllUsesOfValueWith(N1, SetCC); 6790 removeFromWorkList(N1.getNode()); 6791 DAG.DeleteNode(N1.getNode()); 6792 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6793 } 6794 } 6795 } 6796 6797 if (Trunc) 6798 // Restore N1 if the above transformation doesn't match. 6799 N1 = N->getOperand(1); 6800 } 6801 6802 // Transform br(xor(x, y)) -> br(x != y) 6803 // Transform br(xor(xor(x,y), 1)) -> br (x == y) 6804 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) { 6805 SDNode *TheXor = N1.getNode(); 6806 SDValue Op0 = TheXor->getOperand(0); 6807 SDValue Op1 = TheXor->getOperand(1); 6808 if (Op0.getOpcode() == Op1.getOpcode()) { 6809 // Avoid missing important xor optimizations. 6810 SDValue Tmp = visitXOR(TheXor); 6811 if (Tmp.getNode()) { 6812 if (Tmp.getNode() != TheXor) { 6813 DEBUG(dbgs() << "\nReplacing.8 "; 6814 TheXor->dump(&DAG); 6815 dbgs() << "\nWith: "; 6816 Tmp.getNode()->dump(&DAG); 6817 dbgs() << '\n'); 6818 WorkListRemover DeadNodes(*this); 6819 DAG.ReplaceAllUsesOfValueWith(N1, Tmp); 6820 removeFromWorkList(TheXor); 6821 DAG.DeleteNode(TheXor); 6822 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6823 MVT::Other, Chain, Tmp, N2); 6824 } 6825 6826 // visitXOR has changed XOR's operands or replaced the XOR completely, 6827 // bail out. 6828 return SDValue(N, 0); 6829 } 6830 } 6831 6832 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { 6833 bool Equal = false; 6834 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0)) 6835 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() && 6836 Op0.getOpcode() == ISD::XOR) { 6837 TheXor = Op0.getNode(); 6838 Equal = true; 6839 } 6840 6841 EVT SetCCVT = N1.getValueType(); 6842 if (LegalTypes) 6843 SetCCVT = TLI.getSetCCResultType(SetCCVT); 6844 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(), 6845 SetCCVT, 6846 Op0, Op1, 6847 Equal ? ISD::SETEQ : ISD::SETNE); 6848 // Replace the uses of XOR with SETCC 6849 WorkListRemover DeadNodes(*this); 6850 DAG.ReplaceAllUsesOfValueWith(N1, SetCC); 6851 removeFromWorkList(N1.getNode()); 6852 DAG.DeleteNode(N1.getNode()); 6853 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6854 MVT::Other, Chain, SetCC, N2); 6855 } 6856 } 6857 6858 return SDValue(); 6859} 6860 6861// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 6862// 6863SDValue DAGCombiner::visitBR_CC(SDNode *N) { 6864 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 6865 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 6866 6867 // If N is a constant we could fold this into a fallthrough or unconditional 6868 // branch. However that doesn't happen very often in normal code, because 6869 // Instcombine/SimplifyCFG should have handled the available opportunities. 6870 // If we did this folding here, it would be necessary to update the 6871 // MachineBasicBlock CFG, which is awkward. 6872 6873 // Use SimplifySetCC to simplify SETCC's. 6874 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 6875 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 6876 false); 6877 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 6878 6879 // fold to a simpler setcc 6880 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 6881 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 6882 N->getOperand(0), Simp.getOperand(2), 6883 Simp.getOperand(0), Simp.getOperand(1), 6884 N->getOperand(4)); 6885 6886 return SDValue(); 6887} 6888 6889/// canFoldInAddressingMode - Return true if 'Use' is a load or a store that 6890/// uses N as its base pointer and that N may be folded in the load / store 6891/// addressing mode. 6892static bool canFoldInAddressingMode(SDNode *N, SDNode *Use, 6893 SelectionDAG &DAG, 6894 const TargetLowering &TLI) { 6895 EVT VT; 6896 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Use)) { 6897 if (LD->isIndexed() || LD->getBasePtr().getNode() != N) 6898 return false; 6899 VT = Use->getValueType(0); 6900 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(Use)) { 6901 if (ST->isIndexed() || ST->getBasePtr().getNode() != N) 6902 return false; 6903 VT = ST->getValue().getValueType(); 6904 } else 6905 return false; 6906 6907 TargetLowering::AddrMode AM; 6908 if (N->getOpcode() == ISD::ADD) { 6909 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1)); 6910 if (Offset) 6911 // [reg +/- imm] 6912 AM.BaseOffs = Offset->getSExtValue(); 6913 else 6914 // [reg +/- reg] 6915 AM.Scale = 1; 6916 } else if (N->getOpcode() == ISD::SUB) { 6917 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1)); 6918 if (Offset) 6919 // [reg +/- imm] 6920 AM.BaseOffs = -Offset->getSExtValue(); 6921 else 6922 // [reg +/- reg] 6923 AM.Scale = 1; 6924 } else 6925 return false; 6926 6927 return TLI.isLegalAddressingMode(AM, VT.getTypeForEVT(*DAG.getContext())); 6928} 6929 6930/// CombineToPreIndexedLoadStore - Try turning a load / store into a 6931/// pre-indexed load / store when the base pointer is an add or subtract 6932/// and it has other uses besides the load / store. After the 6933/// transformation, the new indexed load / store has effectively folded 6934/// the add / subtract in and all of its other uses are redirected to the 6935/// new load / store. 6936bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 6937 if (Level < AfterLegalizeDAG) 6938 return false; 6939 6940 bool isLoad = true; 6941 SDValue Ptr; 6942 EVT VT; 6943 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6944 if (LD->isIndexed()) 6945 return false; 6946 VT = LD->getMemoryVT(); 6947 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 6948 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 6949 return false; 6950 Ptr = LD->getBasePtr(); 6951 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6952 if (ST->isIndexed()) 6953 return false; 6954 VT = ST->getMemoryVT(); 6955 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 6956 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 6957 return false; 6958 Ptr = ST->getBasePtr(); 6959 isLoad = false; 6960 } else { 6961 return false; 6962 } 6963 6964 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 6965 // out. There is no reason to make this a preinc/predec. 6966 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 6967 Ptr.getNode()->hasOneUse()) 6968 return false; 6969 6970 // Ask the target to do addressing mode selection. 6971 SDValue BasePtr; 6972 SDValue Offset; 6973 ISD::MemIndexedMode AM = ISD::UNINDEXED; 6974 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 6975 return false; 6976 6977 // Backends without true r+i pre-indexed forms may need to pass a 6978 // constant base with a variable offset so that constant coercion 6979 // will work with the patterns in canonical form. 6980 bool Swapped = false; 6981 if (isa<ConstantSDNode>(BasePtr)) { 6982 std::swap(BasePtr, Offset); 6983 Swapped = true; 6984 } 6985 6986 // Don't create a indexed load / store with zero offset. 6987 if (isa<ConstantSDNode>(Offset) && 6988 cast<ConstantSDNode>(Offset)->isNullValue()) 6989 return false; 6990 6991 // Try turning it into a pre-indexed load / store except when: 6992 // 1) The new base ptr is a frame index. 6993 // 2) If N is a store and the new base ptr is either the same as or is a 6994 // predecessor of the value being stored. 6995 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 6996 // that would create a cycle. 6997 // 4) All uses are load / store ops that use it as old base ptr. 6998 6999 // Check #1. Preinc'ing a frame index would require copying the stack pointer 7000 // (plus the implicit offset) to a register to preinc anyway. 7001 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 7002 return false; 7003 7004 // Check #2. 7005 if (!isLoad) { 7006 SDValue Val = cast<StoreSDNode>(N)->getValue(); 7007 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 7008 return false; 7009 } 7010 7011 // If the offset is a constant, there may be other adds of constants that 7012 // can be folded with this one. We should do this to avoid having to keep 7013 // a copy of the original base pointer. 7014 SmallVector<SDNode *, 16> OtherUses; 7015 if (isa<ConstantSDNode>(Offset)) 7016 for (SDNode::use_iterator I = BasePtr.getNode()->use_begin(), 7017 E = BasePtr.getNode()->use_end(); I != E; ++I) { 7018 SDNode *Use = *I; 7019 if (Use == Ptr.getNode()) 7020 continue; 7021 7022 if (Use->isPredecessorOf(N)) 7023 continue; 7024 7025 if (Use->getOpcode() != ISD::ADD && Use->getOpcode() != ISD::SUB) { 7026 OtherUses.clear(); 7027 break; 7028 } 7029 7030 SDValue Op0 = Use->getOperand(0), Op1 = Use->getOperand(1); 7031 if (Op1.getNode() == BasePtr.getNode()) 7032 std::swap(Op0, Op1); 7033 assert(Op0.getNode() == BasePtr.getNode() && 7034 "Use of ADD/SUB but not an operand"); 7035 7036 if (!isa<ConstantSDNode>(Op1)) { 7037 OtherUses.clear(); 7038 break; 7039 } 7040 7041 // FIXME: In some cases, we can be smarter about this. 7042 if (Op1.getValueType() != Offset.getValueType()) { 7043 OtherUses.clear(); 7044 break; 7045 } 7046 7047 OtherUses.push_back(Use); 7048 } 7049 7050 if (Swapped) 7051 std::swap(BasePtr, Offset); 7052 7053 // Now check for #3 and #4. 7054 bool RealUse = false; 7055 7056 // Caches for hasPredecessorHelper 7057 SmallPtrSet<const SDNode *, 32> Visited; 7058 SmallVector<const SDNode *, 16> Worklist; 7059 7060 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 7061 E = Ptr.getNode()->use_end(); I != E; ++I) { 7062 SDNode *Use = *I; 7063 if (Use == N) 7064 continue; 7065 if (N->hasPredecessorHelper(Use, Visited, Worklist)) 7066 return false; 7067 7068 // If Ptr may be folded in addressing mode of other use, then it's 7069 // not profitable to do this transformation. 7070 if (!canFoldInAddressingMode(Ptr.getNode(), Use, DAG, TLI)) 7071 RealUse = true; 7072 } 7073 7074 if (!RealUse) 7075 return false; 7076 7077 SDValue Result; 7078 if (isLoad) 7079 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 7080 BasePtr, Offset, AM); 7081 else 7082 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 7083 BasePtr, Offset, AM); 7084 ++PreIndexedNodes; 7085 ++NodesCombined; 7086 DEBUG(dbgs() << "\nReplacing.4 "; 7087 N->dump(&DAG); 7088 dbgs() << "\nWith: "; 7089 Result.getNode()->dump(&DAG); 7090 dbgs() << '\n'); 7091 WorkListRemover DeadNodes(*this); 7092 if (isLoad) { 7093 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0)); 7094 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2)); 7095 } else { 7096 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1)); 7097 } 7098 7099 // Finally, since the node is now dead, remove it from the graph. 7100 DAG.DeleteNode(N); 7101 7102 if (Swapped) 7103 std::swap(BasePtr, Offset); 7104 7105 // Replace other uses of BasePtr that can be updated to use Ptr 7106 for (unsigned i = 0, e = OtherUses.size(); i != e; ++i) { 7107 unsigned OffsetIdx = 1; 7108 if (OtherUses[i]->getOperand(OffsetIdx).getNode() == BasePtr.getNode()) 7109 OffsetIdx = 0; 7110 assert(OtherUses[i]->getOperand(!OffsetIdx).getNode() == 7111 BasePtr.getNode() && "Expected BasePtr operand"); 7112 7113 APInt OV = 7114 cast<ConstantSDNode>(Offset)->getAPIntValue(); 7115 if (AM == ISD::PRE_DEC) 7116 OV = -OV; 7117 7118 ConstantSDNode *CN = 7119 cast<ConstantSDNode>(OtherUses[i]->getOperand(OffsetIdx)); 7120 APInt CNV = CN->getAPIntValue(); 7121 if (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 1) 7122 CNV += OV; 7123 else 7124 CNV -= OV; 7125 7126 SDValue NewOp1 = Result.getValue(isLoad ? 1 : 0); 7127 SDValue NewOp2 = DAG.getConstant(CNV, CN->getValueType(0)); 7128 if (OffsetIdx == 0) 7129 std::swap(NewOp1, NewOp2); 7130 7131 SDValue NewUse = DAG.getNode(OtherUses[i]->getOpcode(), 7132 OtherUses[i]->getDebugLoc(), 7133 OtherUses[i]->getValueType(0), NewOp1, NewOp2); 7134 DAG.ReplaceAllUsesOfValueWith(SDValue(OtherUses[i], 0), NewUse); 7135 removeFromWorkList(OtherUses[i]); 7136 DAG.DeleteNode(OtherUses[i]); 7137 } 7138 7139 // Replace the uses of Ptr with uses of the updated base value. 7140 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0)); 7141 removeFromWorkList(Ptr.getNode()); 7142 DAG.DeleteNode(Ptr.getNode()); 7143 7144 return true; 7145} 7146 7147/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 7148/// add / sub of the base pointer node into a post-indexed load / store. 7149/// The transformation folded the add / subtract into the new indexed 7150/// load / store effectively and all of its uses are redirected to the 7151/// new load / store. 7152bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 7153 if (Level < AfterLegalizeDAG) 7154 return false; 7155 7156 bool isLoad = true; 7157 SDValue Ptr; 7158 EVT VT; 7159 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 7160 if (LD->isIndexed()) 7161 return false; 7162 VT = LD->getMemoryVT(); 7163 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 7164 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 7165 return false; 7166 Ptr = LD->getBasePtr(); 7167 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 7168 if (ST->isIndexed()) 7169 return false; 7170 VT = ST->getMemoryVT(); 7171 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 7172 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 7173 return false; 7174 Ptr = ST->getBasePtr(); 7175 isLoad = false; 7176 } else { 7177 return false; 7178 } 7179 7180 if (Ptr.getNode()->hasOneUse()) 7181 return false; 7182 7183 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 7184 E = Ptr.getNode()->use_end(); I != E; ++I) { 7185 SDNode *Op = *I; 7186 if (Op == N || 7187 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 7188 continue; 7189 7190 SDValue BasePtr; 7191 SDValue Offset; 7192 ISD::MemIndexedMode AM = ISD::UNINDEXED; 7193 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 7194 // Don't create a indexed load / store with zero offset. 7195 if (isa<ConstantSDNode>(Offset) && 7196 cast<ConstantSDNode>(Offset)->isNullValue()) 7197 continue; 7198 7199 // Try turning it into a post-indexed load / store except when 7200 // 1) All uses are load / store ops that use it as base ptr (and 7201 // it may be folded as addressing mmode). 7202 // 2) Op must be independent of N, i.e. Op is neither a predecessor 7203 // nor a successor of N. Otherwise, if Op is folded that would 7204 // create a cycle. 7205 7206 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 7207 continue; 7208 7209 // Check for #1. 7210 bool TryNext = false; 7211 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 7212 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 7213 SDNode *Use = *II; 7214 if (Use == Ptr.getNode()) 7215 continue; 7216 7217 // If all the uses are load / store addresses, then don't do the 7218 // transformation. 7219 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 7220 bool RealUse = false; 7221 for (SDNode::use_iterator III = Use->use_begin(), 7222 EEE = Use->use_end(); III != EEE; ++III) { 7223 SDNode *UseUse = *III; 7224 if (!canFoldInAddressingMode(Use, UseUse, DAG, TLI)) 7225 RealUse = true; 7226 } 7227 7228 if (!RealUse) { 7229 TryNext = true; 7230 break; 7231 } 7232 } 7233 } 7234 7235 if (TryNext) 7236 continue; 7237 7238 // Check for #2 7239 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 7240 SDValue Result = isLoad 7241 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 7242 BasePtr, Offset, AM) 7243 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 7244 BasePtr, Offset, AM); 7245 ++PostIndexedNodes; 7246 ++NodesCombined; 7247 DEBUG(dbgs() << "\nReplacing.5 "; 7248 N->dump(&DAG); 7249 dbgs() << "\nWith: "; 7250 Result.getNode()->dump(&DAG); 7251 dbgs() << '\n'); 7252 WorkListRemover DeadNodes(*this); 7253 if (isLoad) { 7254 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0)); 7255 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2)); 7256 } else { 7257 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1)); 7258 } 7259 7260 // Finally, since the node is now dead, remove it from the graph. 7261 DAG.DeleteNode(N); 7262 7263 // Replace the uses of Use with uses of the updated base value. 7264 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 7265 Result.getValue(isLoad ? 1 : 0)); 7266 removeFromWorkList(Op); 7267 DAG.DeleteNode(Op); 7268 return true; 7269 } 7270 } 7271 } 7272 7273 return false; 7274} 7275 7276SDValue DAGCombiner::visitLOAD(SDNode *N) { 7277 LoadSDNode *LD = cast<LoadSDNode>(N); 7278 SDValue Chain = LD->getChain(); 7279 SDValue Ptr = LD->getBasePtr(); 7280 7281 // If load is not volatile and there are no uses of the loaded value (and 7282 // the updated indexed value in case of indexed loads), change uses of the 7283 // chain value into uses of the chain input (i.e. delete the dead load). 7284 if (!LD->isVolatile()) { 7285 if (N->getValueType(1) == MVT::Other) { 7286 // Unindexed loads. 7287 if (!N->hasAnyUseOfValue(0)) { 7288 // It's not safe to use the two value CombineTo variant here. e.g. 7289 // v1, chain2 = load chain1, loc 7290 // v2, chain3 = load chain2, loc 7291 // v3 = add v2, c 7292 // Now we replace use of chain2 with chain1. This makes the second load 7293 // isomorphic to the one we are deleting, and thus makes this load live. 7294 DEBUG(dbgs() << "\nReplacing.6 "; 7295 N->dump(&DAG); 7296 dbgs() << "\nWith chain: "; 7297 Chain.getNode()->dump(&DAG); 7298 dbgs() << "\n"); 7299 WorkListRemover DeadNodes(*this); 7300 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain); 7301 7302 if (N->use_empty()) { 7303 removeFromWorkList(N); 7304 DAG.DeleteNode(N); 7305 } 7306 7307 return SDValue(N, 0); // Return N so it doesn't get rechecked! 7308 } 7309 } else { 7310 // Indexed loads. 7311 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 7312 if (!N->hasAnyUseOfValue(0) && !N->hasAnyUseOfValue(1)) { 7313 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 7314 DEBUG(dbgs() << "\nReplacing.7 "; 7315 N->dump(&DAG); 7316 dbgs() << "\nWith: "; 7317 Undef.getNode()->dump(&DAG); 7318 dbgs() << " and 2 other values\n"); 7319 WorkListRemover DeadNodes(*this); 7320 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef); 7321 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 7322 DAG.getUNDEF(N->getValueType(1))); 7323 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain); 7324 removeFromWorkList(N); 7325 DAG.DeleteNode(N); 7326 return SDValue(N, 0); // Return N so it doesn't get rechecked! 7327 } 7328 } 7329 } 7330 7331 // If this load is directly stored, replace the load value with the stored 7332 // value. 7333 // TODO: Handle store large -> read small portion. 7334 // TODO: Handle TRUNCSTORE/LOADEXT 7335 if (ISD::isNormalLoad(N) && !LD->isVolatile()) { 7336 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 7337 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 7338 if (PrevST->getBasePtr() == Ptr && 7339 PrevST->getValue().getValueType() == N->getValueType(0)) 7340 return CombineTo(N, Chain.getOperand(1), Chain); 7341 } 7342 } 7343 7344 // Try to infer better alignment information than the load already has. 7345 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 7346 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 7347 if (Align > LD->getMemOperand()->getBaseAlignment()) { 7348 SDValue NewLoad = 7349 DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 7350 LD->getValueType(0), 7351 Chain, Ptr, LD->getPointerInfo(), 7352 LD->getMemoryVT(), 7353 LD->isVolatile(), LD->isNonTemporal(), Align); 7354 return CombineTo(N, NewLoad, SDValue(NewLoad.getNode(), 1), true); 7355 } 7356 } 7357 } 7358 7359 if (CombinerAA) { 7360 // Walk up chain skipping non-aliasing memory nodes. 7361 SDValue BetterChain = FindBetterChain(N, Chain); 7362 7363 // If there is a better chain. 7364 if (Chain != BetterChain) { 7365 SDValue ReplLoad; 7366 7367 // Replace the chain to void dependency. 7368 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 7369 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 7370 BetterChain, Ptr, LD->getPointerInfo(), 7371 LD->isVolatile(), LD->isNonTemporal(), 7372 LD->isInvariant(), LD->getAlignment()); 7373 } else { 7374 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 7375 LD->getValueType(0), 7376 BetterChain, Ptr, LD->getPointerInfo(), 7377 LD->getMemoryVT(), 7378 LD->isVolatile(), 7379 LD->isNonTemporal(), 7380 LD->getAlignment()); 7381 } 7382 7383 // Create token factor to keep old chain connected. 7384 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 7385 MVT::Other, Chain, ReplLoad.getValue(1)); 7386 7387 // Make sure the new and old chains are cleaned up. 7388 AddToWorkList(Token.getNode()); 7389 7390 // Replace uses with load result and token factor. Don't add users 7391 // to work list. 7392 return CombineTo(N, ReplLoad.getValue(0), Token, false); 7393 } 7394 } 7395 7396 // Try transforming N to an indexed load. 7397 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 7398 return SDValue(N, 0); 7399 7400 return SDValue(); 7401} 7402 7403/// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the 7404/// load is having specific bytes cleared out. If so, return the byte size 7405/// being masked out and the shift amount. 7406static std::pair<unsigned, unsigned> 7407CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) { 7408 std::pair<unsigned, unsigned> Result(0, 0); 7409 7410 // Check for the structure we're looking for. 7411 if (V->getOpcode() != ISD::AND || 7412 !isa<ConstantSDNode>(V->getOperand(1)) || 7413 !ISD::isNormalLoad(V->getOperand(0).getNode())) 7414 return Result; 7415 7416 // Check the chain and pointer. 7417 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0)); 7418 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer. 7419 7420 // The store should be chained directly to the load or be an operand of a 7421 // tokenfactor. 7422 if (LD == Chain.getNode()) 7423 ; // ok. 7424 else if (Chain->getOpcode() != ISD::TokenFactor) 7425 return Result; // Fail. 7426 else { 7427 bool isOk = false; 7428 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) 7429 if (Chain->getOperand(i).getNode() == LD) { 7430 isOk = true; 7431 break; 7432 } 7433 if (!isOk) return Result; 7434 } 7435 7436 // This only handles simple types. 7437 if (V.getValueType() != MVT::i16 && 7438 V.getValueType() != MVT::i32 && 7439 V.getValueType() != MVT::i64) 7440 return Result; 7441 7442 // Check the constant mask. Invert it so that the bits being masked out are 7443 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits 7444 // follow the sign bit for uniformity. 7445 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue(); 7446 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask); 7447 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte. 7448 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask); 7449 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte. 7450 if (NotMaskLZ == 64) return Result; // All zero mask. 7451 7452 // See if we have a continuous run of bits. If so, we have 0*1+0* 7453 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64) 7454 return Result; 7455 7456 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64. 7457 if (V.getValueType() != MVT::i64 && NotMaskLZ) 7458 NotMaskLZ -= 64-V.getValueSizeInBits(); 7459 7460 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8; 7461 switch (MaskedBytes) { 7462 case 1: 7463 case 2: 7464 case 4: break; 7465 default: return Result; // All one mask, or 5-byte mask. 7466 } 7467 7468 // Verify that the first bit starts at a multiple of mask so that the access 7469 // is aligned the same as the access width. 7470 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result; 7471 7472 Result.first = MaskedBytes; 7473 Result.second = NotMaskTZ/8; 7474 return Result; 7475} 7476 7477 7478/// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that 7479/// provides a value as specified by MaskInfo. If so, replace the specified 7480/// store with a narrower store of truncated IVal. 7481static SDNode * 7482ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo, 7483 SDValue IVal, StoreSDNode *St, 7484 DAGCombiner *DC) { 7485 unsigned NumBytes = MaskInfo.first; 7486 unsigned ByteShift = MaskInfo.second; 7487 SelectionDAG &DAG = DC->getDAG(); 7488 7489 // Check to see if IVal is all zeros in the part being masked in by the 'or' 7490 // that uses this. If not, this is not a replacement. 7491 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(), 7492 ByteShift*8, (ByteShift+NumBytes)*8); 7493 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0; 7494 7495 // Check that it is legal on the target to do this. It is legal if the new 7496 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type 7497 // legalization. 7498 MVT VT = MVT::getIntegerVT(NumBytes*8); 7499 if (!DC->isTypeLegal(VT)) 7500 return 0; 7501 7502 // Okay, we can do this! Replace the 'St' store with a store of IVal that is 7503 // shifted by ByteShift and truncated down to NumBytes. 7504 if (ByteShift) 7505 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal, 7506 DAG.getConstant(ByteShift*8, 7507 DC->getShiftAmountTy(IVal.getValueType()))); 7508 7509 // Figure out the offset for the store and the alignment of the access. 7510 unsigned StOffset; 7511 unsigned NewAlign = St->getAlignment(); 7512 7513 if (DAG.getTargetLoweringInfo().isLittleEndian()) 7514 StOffset = ByteShift; 7515 else 7516 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes; 7517 7518 SDValue Ptr = St->getBasePtr(); 7519 if (StOffset) { 7520 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(), 7521 Ptr, DAG.getConstant(StOffset, Ptr.getValueType())); 7522 NewAlign = MinAlign(NewAlign, StOffset); 7523 } 7524 7525 // Truncate down to the new size. 7526 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal); 7527 7528 ++OpsNarrowed; 7529 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr, 7530 St->getPointerInfo().getWithOffset(StOffset), 7531 false, false, NewAlign).getNode(); 7532} 7533 7534 7535/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 7536/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 7537/// of the loaded bits, try narrowing the load and store if it would end up 7538/// being a win for performance or code size. 7539SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 7540 StoreSDNode *ST = cast<StoreSDNode>(N); 7541 if (ST->isVolatile()) 7542 return SDValue(); 7543 7544 SDValue Chain = ST->getChain(); 7545 SDValue Value = ST->getValue(); 7546 SDValue Ptr = ST->getBasePtr(); 7547 EVT VT = Value.getValueType(); 7548 7549 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 7550 return SDValue(); 7551 7552 unsigned Opc = Value.getOpcode(); 7553 7554 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst 7555 // is a byte mask indicating a consecutive number of bytes, check to see if 7556 // Y is known to provide just those bytes. If so, we try to replace the 7557 // load + replace + store sequence with a single (narrower) store, which makes 7558 // the load dead. 7559 if (Opc == ISD::OR) { 7560 std::pair<unsigned, unsigned> MaskedLoad; 7561 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain); 7562 if (MaskedLoad.first) 7563 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 7564 Value.getOperand(1), ST,this)) 7565 return SDValue(NewST, 0); 7566 7567 // Or is commutative, so try swapping X and Y. 7568 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain); 7569 if (MaskedLoad.first) 7570 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 7571 Value.getOperand(0), ST,this)) 7572 return SDValue(NewST, 0); 7573 } 7574 7575 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 7576 Value.getOperand(1).getOpcode() != ISD::Constant) 7577 return SDValue(); 7578 7579 SDValue N0 = Value.getOperand(0); 7580 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 7581 Chain == SDValue(N0.getNode(), 1)) { 7582 LoadSDNode *LD = cast<LoadSDNode>(N0); 7583 if (LD->getBasePtr() != Ptr || 7584 LD->getPointerInfo().getAddrSpace() != 7585 ST->getPointerInfo().getAddrSpace()) 7586 return SDValue(); 7587 7588 // Find the type to narrow it the load / op / store to. 7589 SDValue N1 = Value.getOperand(1); 7590 unsigned BitWidth = N1.getValueSizeInBits(); 7591 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 7592 if (Opc == ISD::AND) 7593 Imm ^= APInt::getAllOnesValue(BitWidth); 7594 if (Imm == 0 || Imm.isAllOnesValue()) 7595 return SDValue(); 7596 unsigned ShAmt = Imm.countTrailingZeros(); 7597 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 7598 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 7599 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 7600 while (NewBW < BitWidth && 7601 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 7602 TLI.isNarrowingProfitable(VT, NewVT))) { 7603 NewBW = NextPowerOf2(NewBW); 7604 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 7605 } 7606 if (NewBW >= BitWidth) 7607 return SDValue(); 7608 7609 // If the lsb changed does not start at the type bitwidth boundary, 7610 // start at the previous one. 7611 if (ShAmt % NewBW) 7612 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 7613 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, 7614 std::min(BitWidth, ShAmt + NewBW)); 7615 if ((Imm & Mask) == Imm) { 7616 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 7617 if (Opc == ISD::AND) 7618 NewImm ^= APInt::getAllOnesValue(NewBW); 7619 uint64_t PtrOff = ShAmt / 8; 7620 // For big endian targets, we need to adjust the offset to the pointer to 7621 // load the correct bytes. 7622 if (TLI.isBigEndian()) 7623 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 7624 7625 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 7626 Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext()); 7627 if (NewAlign < TLI.getDataLayout()->getABITypeAlignment(NewVTTy)) 7628 return SDValue(); 7629 7630 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 7631 Ptr.getValueType(), Ptr, 7632 DAG.getConstant(PtrOff, Ptr.getValueType())); 7633 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 7634 LD->getChain(), NewPtr, 7635 LD->getPointerInfo().getWithOffset(PtrOff), 7636 LD->isVolatile(), LD->isNonTemporal(), 7637 LD->isInvariant(), NewAlign); 7638 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 7639 DAG.getConstant(NewImm, NewVT)); 7640 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 7641 NewVal, NewPtr, 7642 ST->getPointerInfo().getWithOffset(PtrOff), 7643 false, false, NewAlign); 7644 7645 AddToWorkList(NewPtr.getNode()); 7646 AddToWorkList(NewLD.getNode()); 7647 AddToWorkList(NewVal.getNode()); 7648 WorkListRemover DeadNodes(*this); 7649 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1)); 7650 ++OpsNarrowed; 7651 return NewST; 7652 } 7653 } 7654 7655 return SDValue(); 7656} 7657 7658/// TransformFPLoadStorePair - For a given floating point load / store pair, 7659/// if the load value isn't used by any other operations, then consider 7660/// transforming the pair to integer load / store operations if the target 7661/// deems the transformation profitable. 7662SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) { 7663 StoreSDNode *ST = cast<StoreSDNode>(N); 7664 SDValue Chain = ST->getChain(); 7665 SDValue Value = ST->getValue(); 7666 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) && 7667 Value.hasOneUse() && 7668 Chain == SDValue(Value.getNode(), 1)) { 7669 LoadSDNode *LD = cast<LoadSDNode>(Value); 7670 EVT VT = LD->getMemoryVT(); 7671 if (!VT.isFloatingPoint() || 7672 VT != ST->getMemoryVT() || 7673 LD->isNonTemporal() || 7674 ST->isNonTemporal() || 7675 LD->getPointerInfo().getAddrSpace() != 0 || 7676 ST->getPointerInfo().getAddrSpace() != 0) 7677 return SDValue(); 7678 7679 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); 7680 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) || 7681 !TLI.isOperationLegal(ISD::STORE, IntVT) || 7682 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) || 7683 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT)) 7684 return SDValue(); 7685 7686 unsigned LDAlign = LD->getAlignment(); 7687 unsigned STAlign = ST->getAlignment(); 7688 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext()); 7689 unsigned ABIAlign = TLI.getDataLayout()->getABITypeAlignment(IntVTTy); 7690 if (LDAlign < ABIAlign || STAlign < ABIAlign) 7691 return SDValue(); 7692 7693 SDValue NewLD = DAG.getLoad(IntVT, Value.getDebugLoc(), 7694 LD->getChain(), LD->getBasePtr(), 7695 LD->getPointerInfo(), 7696 false, false, false, LDAlign); 7697 7698 SDValue NewST = DAG.getStore(NewLD.getValue(1), N->getDebugLoc(), 7699 NewLD, ST->getBasePtr(), 7700 ST->getPointerInfo(), 7701 false, false, STAlign); 7702 7703 AddToWorkList(NewLD.getNode()); 7704 AddToWorkList(NewST.getNode()); 7705 WorkListRemover DeadNodes(*this); 7706 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1)); 7707 ++LdStFP2Int; 7708 return NewST; 7709 } 7710 7711 return SDValue(); 7712} 7713 7714/// Returns the base pointer and an integer offset from that object. 7715static std::pair<SDValue, int64_t> GetPointerBaseAndOffset(SDValue Ptr) { 7716 if (Ptr->getOpcode() == ISD::ADD && isa<ConstantSDNode>(Ptr->getOperand(1))) { 7717 int64_t Offset = cast<ConstantSDNode>(Ptr->getOperand(1))->getSExtValue(); 7718 SDValue Base = Ptr->getOperand(0); 7719 return std::make_pair(Base, Offset); 7720 } 7721 7722 return std::make_pair(Ptr, 0); 7723} 7724 7725/// Holds a pointer to an LSBaseSDNode as well as information on where it 7726/// is located in a sequence of memory operations connected by a chain. 7727struct MemOpLink { 7728 MemOpLink (LSBaseSDNode *N, int64_t Offset, unsigned Seq): 7729 MemNode(N), OffsetFromBase(Offset), SequenceNum(Seq) { } 7730 // Ptr to the mem node. 7731 LSBaseSDNode *MemNode; 7732 // Offset from the base ptr. 7733 int64_t OffsetFromBase; 7734 // What is the sequence number of this mem node. 7735 // Lowest mem operand in the DAG starts at zero. 7736 unsigned SequenceNum; 7737}; 7738 7739/// Sorts store nodes in a link according to their offset from a shared 7740// base ptr. 7741struct ConsecutiveMemoryChainSorter { 7742 bool operator()(MemOpLink LHS, MemOpLink RHS) { 7743 return LHS.OffsetFromBase < RHS.OffsetFromBase; 7744 } 7745}; 7746 7747bool DAGCombiner::MergeConsecutiveStores(StoreSDNode* St) { 7748 EVT MemVT = St->getMemoryVT(); 7749 int64_t ElementSizeBytes = MemVT.getSizeInBits()/8; 7750 bool NoVectors = DAG.getMachineFunction().getFunction()->getAttributes(). 7751 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat); 7752 7753 // Don't merge vectors into wider inputs. 7754 if (MemVT.isVector() || !MemVT.isSimple()) 7755 return false; 7756 7757 // Perform an early exit check. Do not bother looking at stored values that 7758 // are not constants or loads. 7759 SDValue StoredVal = St->getValue(); 7760 bool IsLoadSrc = isa<LoadSDNode>(StoredVal); 7761 if (!isa<ConstantSDNode>(StoredVal) && !isa<ConstantFPSDNode>(StoredVal) && 7762 !IsLoadSrc) 7763 return false; 7764 7765 // Only look at ends of store sequences. 7766 SDValue Chain = SDValue(St, 1); 7767 if (Chain->hasOneUse() && Chain->use_begin()->getOpcode() == ISD::STORE) 7768 return false; 7769 7770 // This holds the base pointer and the offset in bytes from the base pointer. 7771 std::pair<SDValue, int64_t> BasePtr = 7772 GetPointerBaseAndOffset(St->getBasePtr()); 7773 7774 // We must have a base and an offset. 7775 if (!BasePtr.first.getNode()) 7776 return false; 7777 7778 // Do not handle stores to undef base pointers. 7779 if (BasePtr.first.getOpcode() == ISD::UNDEF) 7780 return false; 7781 7782 // Save the LoadSDNodes that we find in the chain. 7783 // We need to make sure that these nodes do not interfere with 7784 // any of the store nodes. 7785 SmallVector<LSBaseSDNode*, 8> AliasLoadNodes; 7786 7787 // Save the StoreSDNodes that we find in the chain. 7788 SmallVector<MemOpLink, 8> StoreNodes; 7789 7790 // Walk up the chain and look for nodes with offsets from the same 7791 // base pointer. Stop when reaching an instruction with a different kind 7792 // or instruction which has a different base pointer. 7793 unsigned Seq = 0; 7794 StoreSDNode *Index = St; 7795 while (Index) { 7796 // If the chain has more than one use, then we can't reorder the mem ops. 7797 if (Index != St && !SDValue(Index, 1)->hasOneUse()) 7798 break; 7799 7800 // Find the base pointer and offset for this memory node. 7801 std::pair<SDValue, int64_t> Ptr = 7802 GetPointerBaseAndOffset(Index->getBasePtr()); 7803 7804 // Check that the base pointer is the same as the original one. 7805 if (Ptr.first.getNode() != BasePtr.first.getNode()) 7806 break; 7807 7808 // Check that the alignment is the same. 7809 if (Index->getAlignment() != St->getAlignment()) 7810 break; 7811 7812 // The memory operands must not be volatile. 7813 if (Index->isVolatile() || Index->isIndexed()) 7814 break; 7815 7816 // No truncation. 7817 if (StoreSDNode *St = dyn_cast<StoreSDNode>(Index)) 7818 if (St->isTruncatingStore()) 7819 break; 7820 7821 // The stored memory type must be the same. 7822 if (Index->getMemoryVT() != MemVT) 7823 break; 7824 7825 // We do not allow unaligned stores because we want to prevent overriding 7826 // stores. 7827 if (Index->getAlignment()*8 != MemVT.getSizeInBits()) 7828 break; 7829 7830 // We found a potential memory operand to merge. 7831 StoreNodes.push_back(MemOpLink(Index, Ptr.second, Seq++)); 7832 7833 // Find the next memory operand in the chain. If the next operand in the 7834 // chain is a store then move up and continue the scan with the next 7835 // memory operand. If the next operand is a load save it and use alias 7836 // information to check if it interferes with anything. 7837 SDNode *NextInChain = Index->getChain().getNode(); 7838 while (1) { 7839 if (StoreSDNode *STn = dyn_cast<StoreSDNode>(NextInChain)) { 7840 // We found a store node. Use it for the next iteration. 7841 Index = STn; 7842 break; 7843 } else if (LoadSDNode *Ldn = dyn_cast<LoadSDNode>(NextInChain)) { 7844 // Save the load node for later. Continue the scan. 7845 AliasLoadNodes.push_back(Ldn); 7846 NextInChain = Ldn->getChain().getNode(); 7847 continue; 7848 } else { 7849 Index = NULL; 7850 break; 7851 } 7852 } 7853 } 7854 7855 // Check if there is anything to merge. 7856 if (StoreNodes.size() < 2) 7857 return false; 7858 7859 // Sort the memory operands according to their distance from the base pointer. 7860 std::sort(StoreNodes.begin(), StoreNodes.end(), 7861 ConsecutiveMemoryChainSorter()); 7862 7863 // Scan the memory operations on the chain and find the first non-consecutive 7864 // store memory address. 7865 unsigned LastConsecutiveStore = 0; 7866 int64_t StartAddress = StoreNodes[0].OffsetFromBase; 7867 for (unsigned i = 0, e = StoreNodes.size(); i < e; ++i) { 7868 7869 // Check that the addresses are consecutive starting from the second 7870 // element in the list of stores. 7871 if (i > 0) { 7872 int64_t CurrAddress = StoreNodes[i].OffsetFromBase; 7873 if (CurrAddress - StartAddress != (ElementSizeBytes * i)) 7874 break; 7875 } 7876 7877 bool Alias = false; 7878 // Check if this store interferes with any of the loads that we found. 7879 for (unsigned ld = 0, lde = AliasLoadNodes.size(); ld < lde; ++ld) 7880 if (isAlias(AliasLoadNodes[ld], StoreNodes[i].MemNode)) { 7881 Alias = true; 7882 break; 7883 } 7884 // We found a load that alias with this store. Stop the sequence. 7885 if (Alias) 7886 break; 7887 7888 // Mark this node as useful. 7889 LastConsecutiveStore = i; 7890 } 7891 7892 // The node with the lowest store address. 7893 LSBaseSDNode *FirstInChain = StoreNodes[0].MemNode; 7894 7895 // Store the constants into memory as one consecutive store. 7896 if (!IsLoadSrc) { 7897 unsigned LastLegalType = 0; 7898 unsigned LastLegalVectorType = 0; 7899 bool NonZero = false; 7900 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) { 7901 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode); 7902 SDValue StoredVal = St->getValue(); 7903 7904 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(StoredVal)) { 7905 NonZero |= !C->isNullValue(); 7906 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(StoredVal)) { 7907 NonZero |= !C->getConstantFPValue()->isNullValue(); 7908 } else { 7909 // Non constant. 7910 break; 7911 } 7912 7913 // Find a legal type for the constant store. 7914 unsigned StoreBW = (i+1) * ElementSizeBytes * 8; 7915 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW); 7916 if (TLI.isTypeLegal(StoreTy)) 7917 LastLegalType = i+1; 7918 7919 // Find a legal type for the vector store. 7920 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, i+1); 7921 if (TLI.isTypeLegal(Ty)) 7922 LastLegalVectorType = i + 1; 7923 } 7924 7925 // We only use vectors if the constant is known to be zero and the 7926 // function is not marked with the noimplicitfloat attribute. 7927 if (NonZero || NoVectors) 7928 LastLegalVectorType = 0; 7929 7930 // Check if we found a legal integer type to store. 7931 if (LastLegalType == 0 && LastLegalVectorType == 0) 7932 return false; 7933 7934 bool UseVector = (LastLegalVectorType > LastLegalType) && !NoVectors; 7935 unsigned NumElem = UseVector ? LastLegalVectorType : LastLegalType; 7936 7937 // Make sure we have something to merge. 7938 if (NumElem < 2) 7939 return false; 7940 7941 unsigned EarliestNodeUsed = 0; 7942 for (unsigned i=0; i < NumElem; ++i) { 7943 // Find a chain for the new wide-store operand. Notice that some 7944 // of the store nodes that we found may not be selected for inclusion 7945 // in the wide store. The chain we use needs to be the chain of the 7946 // earliest store node which is *used* and replaced by the wide store. 7947 if (StoreNodes[i].SequenceNum > StoreNodes[EarliestNodeUsed].SequenceNum) 7948 EarliestNodeUsed = i; 7949 } 7950 7951 // The earliest Node in the DAG. 7952 LSBaseSDNode *EarliestOp = StoreNodes[EarliestNodeUsed].MemNode; 7953 DebugLoc DL = StoreNodes[0].MemNode->getDebugLoc(); 7954 7955 SDValue StoredVal; 7956 if (UseVector) { 7957 // Find a legal type for the vector store. 7958 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, NumElem); 7959 assert(TLI.isTypeLegal(Ty) && "Illegal vector store"); 7960 StoredVal = DAG.getConstant(0, Ty); 7961 } else { 7962 unsigned StoreBW = NumElem * ElementSizeBytes * 8; 7963 APInt StoreInt(StoreBW, 0); 7964 7965 // Construct a single integer constant which is made of the smaller 7966 // constant inputs. 7967 bool IsLE = TLI.isLittleEndian(); 7968 for (unsigned i = 0; i < NumElem ; ++i) { 7969 unsigned Idx = IsLE ?(NumElem - 1 - i) : i; 7970 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[Idx].MemNode); 7971 SDValue Val = St->getValue(); 7972 StoreInt<<=ElementSizeBytes*8; 7973 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val)) { 7974 StoreInt|=C->getAPIntValue().zext(StoreBW); 7975 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Val)) { 7976 StoreInt|= C->getValueAPF().bitcastToAPInt().zext(StoreBW); 7977 } else { 7978 assert(false && "Invalid constant element type"); 7979 } 7980 } 7981 7982 // Create the new Load and Store operations. 7983 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW); 7984 StoredVal = DAG.getConstant(StoreInt, StoreTy); 7985 } 7986 7987 SDValue NewStore = DAG.getStore(EarliestOp->getChain(), DL, StoredVal, 7988 FirstInChain->getBasePtr(), 7989 FirstInChain->getPointerInfo(), 7990 false, false, 7991 FirstInChain->getAlignment()); 7992 7993 // Replace the first store with the new store 7994 CombineTo(EarliestOp, NewStore); 7995 // Erase all other stores. 7996 for (unsigned i = 0; i < NumElem ; ++i) { 7997 if (StoreNodes[i].MemNode == EarliestOp) 7998 continue; 7999 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode); 8000 // ReplaceAllUsesWith will replace all uses that existed when it was 8001 // called, but graph optimizations may cause new ones to appear. For 8002 // example, the case in pr14333 looks like 8003 // 8004 // St's chain -> St -> another store -> X 8005 // 8006 // And the only difference from St to the other store is the chain. 8007 // When we change it's chain to be St's chain they become identical, 8008 // get CSEed and the net result is that X is now a use of St. 8009 // Since we know that St is redundant, just iterate. 8010 while (!St->use_empty()) 8011 DAG.ReplaceAllUsesWith(SDValue(St, 0), St->getChain()); 8012 removeFromWorkList(St); 8013 DAG.DeleteNode(St); 8014 } 8015 8016 return true; 8017 } 8018 8019 // Below we handle the case of multiple consecutive stores that 8020 // come from multiple consecutive loads. We merge them into a single 8021 // wide load and a single wide store. 8022 8023 // Look for load nodes which are used by the stored values. 8024 SmallVector<MemOpLink, 8> LoadNodes; 8025 8026 // Find acceptable loads. Loads need to have the same chain (token factor), 8027 // must not be zext, volatile, indexed, and they must be consecutive. 8028 SDValue LdBasePtr; 8029 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) { 8030 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode); 8031 LoadSDNode *Ld = dyn_cast<LoadSDNode>(St->getValue()); 8032 if (!Ld) break; 8033 8034 // Loads must only have one use. 8035 if (!Ld->hasNUsesOfValue(1, 0)) 8036 break; 8037 8038 // Check that the alignment is the same as the stores. 8039 if (Ld->getAlignment() != St->getAlignment()) 8040 break; 8041 8042 // The memory operands must not be volatile. 8043 if (Ld->isVolatile() || Ld->isIndexed()) 8044 break; 8045 8046 // We do not accept ext loads. 8047 if (Ld->getExtensionType() != ISD::NON_EXTLOAD) 8048 break; 8049 8050 // The stored memory type must be the same. 8051 if (Ld->getMemoryVT() != MemVT) 8052 break; 8053 8054 std::pair<SDValue, int64_t> LdPtr = 8055 GetPointerBaseAndOffset(Ld->getBasePtr()); 8056 8057 // If this is not the first ptr that we check. 8058 if (LdBasePtr.getNode()) { 8059 // The base ptr must be the same. 8060 if (LdPtr.first != LdBasePtr) 8061 break; 8062 } else { 8063 // Check that all other base pointers are the same as this one. 8064 LdBasePtr = LdPtr.first; 8065 } 8066 8067 // We found a potential memory operand to merge. 8068 LoadNodes.push_back(MemOpLink(Ld, LdPtr.second, 0)); 8069 } 8070 8071 if (LoadNodes.size() < 2) 8072 return false; 8073 8074 // Scan the memory operations on the chain and find the first non-consecutive 8075 // load memory address. These variables hold the index in the store node 8076 // array. 8077 unsigned LastConsecutiveLoad = 0; 8078 // This variable refers to the size and not index in the array. 8079 unsigned LastLegalVectorType = 0; 8080 unsigned LastLegalIntegerType = 0; 8081 StartAddress = LoadNodes[0].OffsetFromBase; 8082 SDValue FirstChain = LoadNodes[0].MemNode->getChain(); 8083 for (unsigned i = 1; i < LoadNodes.size(); ++i) { 8084 // All loads much share the same chain. 8085 if (LoadNodes[i].MemNode->getChain() != FirstChain) 8086 break; 8087 8088 int64_t CurrAddress = LoadNodes[i].OffsetFromBase; 8089 if (CurrAddress - StartAddress != (ElementSizeBytes * i)) 8090 break; 8091 LastConsecutiveLoad = i; 8092 8093 // Find a legal type for the vector store. 8094 EVT StoreTy = EVT::getVectorVT(*DAG.getContext(), MemVT, i+1); 8095 if (TLI.isTypeLegal(StoreTy)) 8096 LastLegalVectorType = i + 1; 8097 8098 // Find a legal type for the integer store. 8099 unsigned StoreBW = (i+1) * ElementSizeBytes * 8; 8100 StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW); 8101 if (TLI.isTypeLegal(StoreTy)) 8102 LastLegalIntegerType = i + 1; 8103 } 8104 8105 // Only use vector types if the vector type is larger than the integer type. 8106 // If they are the same, use integers. 8107 bool UseVectorTy = LastLegalVectorType > LastLegalIntegerType && !NoVectors; 8108 unsigned LastLegalType = std::max(LastLegalVectorType, LastLegalIntegerType); 8109 8110 // We add +1 here because the LastXXX variables refer to location while 8111 // the NumElem refers to array/index size. 8112 unsigned NumElem = std::min(LastConsecutiveStore, LastConsecutiveLoad) + 1; 8113 NumElem = std::min(LastLegalType, NumElem); 8114 8115 if (NumElem < 2) 8116 return false; 8117 8118 // The earliest Node in the DAG. 8119 unsigned EarliestNodeUsed = 0; 8120 LSBaseSDNode *EarliestOp = StoreNodes[EarliestNodeUsed].MemNode; 8121 for (unsigned i=1; i<NumElem; ++i) { 8122 // Find a chain for the new wide-store operand. Notice that some 8123 // of the store nodes that we found may not be selected for inclusion 8124 // in the wide store. The chain we use needs to be the chain of the 8125 // earliest store node which is *used* and replaced by the wide store. 8126 if (StoreNodes[i].SequenceNum > StoreNodes[EarliestNodeUsed].SequenceNum) 8127 EarliestNodeUsed = i; 8128 } 8129 8130 // Find if it is better to use vectors or integers to load and store 8131 // to memory. 8132 EVT JointMemOpVT; 8133 if (UseVectorTy) { 8134 JointMemOpVT = EVT::getVectorVT(*DAG.getContext(), MemVT, NumElem); 8135 } else { 8136 unsigned StoreBW = NumElem * ElementSizeBytes * 8; 8137 JointMemOpVT = EVT::getIntegerVT(*DAG.getContext(), StoreBW); 8138 } 8139 8140 DebugLoc LoadDL = LoadNodes[0].MemNode->getDebugLoc(); 8141 DebugLoc StoreDL = StoreNodes[0].MemNode->getDebugLoc(); 8142 8143 LoadSDNode *FirstLoad = cast<LoadSDNode>(LoadNodes[0].MemNode); 8144 SDValue NewLoad = DAG.getLoad(JointMemOpVT, LoadDL, 8145 FirstLoad->getChain(), 8146 FirstLoad->getBasePtr(), 8147 FirstLoad->getPointerInfo(), 8148 false, false, false, 8149 FirstLoad->getAlignment()); 8150 8151 SDValue NewStore = DAG.getStore(EarliestOp->getChain(), StoreDL, NewLoad, 8152 FirstInChain->getBasePtr(), 8153 FirstInChain->getPointerInfo(), false, false, 8154 FirstInChain->getAlignment()); 8155 8156 // Replace one of the loads with the new load. 8157 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[0].MemNode); 8158 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), 8159 SDValue(NewLoad.getNode(), 1)); 8160 8161 // Remove the rest of the load chains. 8162 for (unsigned i = 1; i < NumElem ; ++i) { 8163 // Replace all chain users of the old load nodes with the chain of the new 8164 // load node. 8165 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[i].MemNode); 8166 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Ld->getChain()); 8167 } 8168 8169 // Replace the first store with the new store. 8170 CombineTo(EarliestOp, NewStore); 8171 // Erase all other stores. 8172 for (unsigned i = 0; i < NumElem ; ++i) { 8173 // Remove all Store nodes. 8174 if (StoreNodes[i].MemNode == EarliestOp) 8175 continue; 8176 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode); 8177 DAG.ReplaceAllUsesOfValueWith(SDValue(St, 0), St->getChain()); 8178 removeFromWorkList(St); 8179 DAG.DeleteNode(St); 8180 } 8181 8182 return true; 8183} 8184 8185SDValue DAGCombiner::visitSTORE(SDNode *N) { 8186 StoreSDNode *ST = cast<StoreSDNode>(N); 8187 SDValue Chain = ST->getChain(); 8188 SDValue Value = ST->getValue(); 8189 SDValue Ptr = ST->getBasePtr(); 8190 8191 // If this is a store of a bit convert, store the input value if the 8192 // resultant store does not need a higher alignment than the original. 8193 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() && 8194 ST->isUnindexed()) { 8195 unsigned OrigAlign = ST->getAlignment(); 8196 EVT SVT = Value.getOperand(0).getValueType(); 8197 unsigned Align = TLI.getDataLayout()-> 8198 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext())); 8199 if (Align <= OrigAlign && 8200 ((!LegalOperations && !ST->isVolatile()) || 8201 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 8202 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 8203 Ptr, ST->getPointerInfo(), ST->isVolatile(), 8204 ST->isNonTemporal(), OrigAlign); 8205 } 8206 8207 // Turn 'store undef, Ptr' -> nothing. 8208 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed()) 8209 return Chain; 8210 8211 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 8212 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 8213 // NOTE: If the original store is volatile, this transform must not increase 8214 // the number of stores. For example, on x86-32 an f64 can be stored in one 8215 // processor operation but an i64 (which is not legal) requires two. So the 8216 // transform should not be done in this case. 8217 if (Value.getOpcode() != ISD::TargetConstantFP) { 8218 SDValue Tmp; 8219 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) { 8220 default: llvm_unreachable("Unknown FP type"); 8221 case MVT::f16: // We don't do this for these yet. 8222 case MVT::f80: 8223 case MVT::f128: 8224 case MVT::ppcf128: 8225 break; 8226 case MVT::f32: 8227 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) || 8228 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 8229 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 8230 bitcastToAPInt().getZExtValue(), MVT::i32); 8231 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 8232 Ptr, ST->getPointerInfo(), ST->isVolatile(), 8233 ST->isNonTemporal(), ST->getAlignment()); 8234 } 8235 break; 8236 case MVT::f64: 8237 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations && 8238 !ST->isVolatile()) || 8239 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 8240 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 8241 getZExtValue(), MVT::i64); 8242 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 8243 Ptr, ST->getPointerInfo(), ST->isVolatile(), 8244 ST->isNonTemporal(), ST->getAlignment()); 8245 } 8246 8247 if (!ST->isVolatile() && 8248 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 8249 // Many FP stores are not made apparent until after legalize, e.g. for 8250 // argument passing. Since this is so common, custom legalize the 8251 // 64-bit integer store into two 32-bit stores. 8252 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 8253 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 8254 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 8255 if (TLI.isBigEndian()) std::swap(Lo, Hi); 8256 8257 unsigned Alignment = ST->getAlignment(); 8258 bool isVolatile = ST->isVolatile(); 8259 bool isNonTemporal = ST->isNonTemporal(); 8260 8261 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 8262 Ptr, ST->getPointerInfo(), 8263 isVolatile, isNonTemporal, 8264 ST->getAlignment()); 8265 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 8266 DAG.getConstant(4, Ptr.getValueType())); 8267 Alignment = MinAlign(Alignment, 4U); 8268 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 8269 Ptr, ST->getPointerInfo().getWithOffset(4), 8270 isVolatile, isNonTemporal, 8271 Alignment); 8272 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 8273 St0, St1); 8274 } 8275 8276 break; 8277 } 8278 } 8279 } 8280 8281 // Try to infer better alignment information than the store already has. 8282 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 8283 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 8284 if (Align > ST->getAlignment()) 8285 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 8286 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 8287 ST->isVolatile(), ST->isNonTemporal(), Align); 8288 } 8289 } 8290 8291 // Try transforming a pair floating point load / store ops to integer 8292 // load / store ops. 8293 SDValue NewST = TransformFPLoadStorePair(N); 8294 if (NewST.getNode()) 8295 return NewST; 8296 8297 if (CombinerAA) { 8298 // Walk up chain skipping non-aliasing memory nodes. 8299 SDValue BetterChain = FindBetterChain(N, Chain); 8300 8301 // If there is a better chain. 8302 if (Chain != BetterChain) { 8303 SDValue ReplStore; 8304 8305 // Replace the chain to avoid dependency. 8306 if (ST->isTruncatingStore()) { 8307 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 8308 ST->getPointerInfo(), 8309 ST->getMemoryVT(), ST->isVolatile(), 8310 ST->isNonTemporal(), ST->getAlignment()); 8311 } else { 8312 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 8313 ST->getPointerInfo(), 8314 ST->isVolatile(), ST->isNonTemporal(), 8315 ST->getAlignment()); 8316 } 8317 8318 // Create token to keep both nodes around. 8319 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 8320 MVT::Other, Chain, ReplStore); 8321 8322 // Make sure the new and old chains are cleaned up. 8323 AddToWorkList(Token.getNode()); 8324 8325 // Don't add users to work list. 8326 return CombineTo(N, Token, false); 8327 } 8328 } 8329 8330 // Try transforming N to an indexed store. 8331 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 8332 return SDValue(N, 0); 8333 8334 // FIXME: is there such a thing as a truncating indexed store? 8335 if (ST->isTruncatingStore() && ST->isUnindexed() && 8336 Value.getValueType().isInteger()) { 8337 // See if we can simplify the input to this truncstore with knowledge that 8338 // only the low bits are being used. For example: 8339 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 8340 SDValue Shorter = 8341 GetDemandedBits(Value, 8342 APInt::getLowBitsSet( 8343 Value.getValueType().getScalarType().getSizeInBits(), 8344 ST->getMemoryVT().getScalarType().getSizeInBits())); 8345 AddToWorkList(Value.getNode()); 8346 if (Shorter.getNode()) 8347 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 8348 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 8349 ST->isVolatile(), ST->isNonTemporal(), 8350 ST->getAlignment()); 8351 8352 // Otherwise, see if we can simplify the operation with 8353 // SimplifyDemandedBits, which only works if the value has a single use. 8354 if (SimplifyDemandedBits(Value, 8355 APInt::getLowBitsSet( 8356 Value.getValueType().getScalarType().getSizeInBits(), 8357 ST->getMemoryVT().getScalarType().getSizeInBits()))) 8358 return SDValue(N, 0); 8359 } 8360 8361 // If this is a load followed by a store to the same location, then the store 8362 // is dead/noop. 8363 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 8364 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 8365 ST->isUnindexed() && !ST->isVolatile() && 8366 // There can't be any side effects between the load and store, such as 8367 // a call or store. 8368 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 8369 // The store is dead, remove it. 8370 return Chain; 8371 } 8372 } 8373 8374 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 8375 // truncating store. We can do this even if this is already a truncstore. 8376 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 8377 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 8378 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 8379 ST->getMemoryVT())) { 8380 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 8381 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 8382 ST->isVolatile(), ST->isNonTemporal(), 8383 ST->getAlignment()); 8384 } 8385 8386 // Only perform this optimization before the types are legal, because we 8387 // don't want to perform this optimization on every DAGCombine invocation. 8388 if (!LegalTypes) { 8389 bool EverChanged = false; 8390 8391 do { 8392 // There can be multiple store sequences on the same chain. 8393 // Keep trying to merge store sequences until we are unable to do so 8394 // or until we merge the last store on the chain. 8395 bool Changed = MergeConsecutiveStores(ST); 8396 EverChanged |= Changed; 8397 if (!Changed) break; 8398 } while (ST->getOpcode() != ISD::DELETED_NODE); 8399 8400 if (EverChanged) 8401 return SDValue(N, 0); 8402 } 8403 8404 return ReduceLoadOpStoreWidth(N); 8405} 8406 8407SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 8408 SDValue InVec = N->getOperand(0); 8409 SDValue InVal = N->getOperand(1); 8410 SDValue EltNo = N->getOperand(2); 8411 DebugLoc dl = N->getDebugLoc(); 8412 8413 // If the inserted element is an UNDEF, just use the input vector. 8414 if (InVal.getOpcode() == ISD::UNDEF) 8415 return InVec; 8416 8417 EVT VT = InVec.getValueType(); 8418 8419 // If we can't generate a legal BUILD_VECTOR, exit 8420 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) 8421 return SDValue(); 8422 8423 // Check that we know which element is being inserted 8424 if (!isa<ConstantSDNode>(EltNo)) 8425 return SDValue(); 8426 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 8427 8428 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially 8429 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the 8430 // vector elements. 8431 SmallVector<SDValue, 8> Ops; 8432 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 8433 Ops.append(InVec.getNode()->op_begin(), 8434 InVec.getNode()->op_end()); 8435 } else if (InVec.getOpcode() == ISD::UNDEF) { 8436 unsigned NElts = VT.getVectorNumElements(); 8437 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType())); 8438 } else { 8439 return SDValue(); 8440 } 8441 8442 // Insert the element 8443 if (Elt < Ops.size()) { 8444 // All the operands of BUILD_VECTOR must have the same type; 8445 // we enforce that here. 8446 EVT OpVT = Ops[0].getValueType(); 8447 if (InVal.getValueType() != OpVT) 8448 InVal = OpVT.bitsGT(InVal.getValueType()) ? 8449 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) : 8450 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal); 8451 Ops[Elt] = InVal; 8452 } 8453 8454 // Return the new vector 8455 return DAG.getNode(ISD::BUILD_VECTOR, dl, 8456 VT, &Ops[0], Ops.size()); 8457} 8458 8459SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 8460 // (vextract (scalar_to_vector val, 0) -> val 8461 SDValue InVec = N->getOperand(0); 8462 EVT VT = InVec.getValueType(); 8463 EVT NVT = N->getValueType(0); 8464 8465 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 8466 // Check if the result type doesn't match the inserted element type. A 8467 // SCALAR_TO_VECTOR may truncate the inserted element and the 8468 // EXTRACT_VECTOR_ELT may widen the extracted vector. 8469 SDValue InOp = InVec.getOperand(0); 8470 if (InOp.getValueType() != NVT) { 8471 assert(InOp.getValueType().isInteger() && NVT.isInteger()); 8472 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT); 8473 } 8474 return InOp; 8475 } 8476 8477 SDValue EltNo = N->getOperand(1); 8478 bool ConstEltNo = isa<ConstantSDNode>(EltNo); 8479 8480 // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT. 8481 // We only perform this optimization before the op legalization phase because 8482 // we may introduce new vector instructions which are not backed by TD 8483 // patterns. For example on AVX, extracting elements from a wide vector 8484 // without using extract_subvector. 8485 if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE 8486 && ConstEltNo && !LegalOperations) { 8487 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 8488 int NumElem = VT.getVectorNumElements(); 8489 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(InVec); 8490 // Find the new index to extract from. 8491 int OrigElt = SVOp->getMaskElt(Elt); 8492 8493 // Extracting an undef index is undef. 8494 if (OrigElt == -1) 8495 return DAG.getUNDEF(NVT); 8496 8497 // Select the right vector half to extract from. 8498 if (OrigElt < NumElem) { 8499 InVec = InVec->getOperand(0); 8500 } else { 8501 InVec = InVec->getOperand(1); 8502 OrigElt -= NumElem; 8503 } 8504 8505 EVT IndexTy = N->getOperand(1).getValueType(); 8506 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), NVT, 8507 InVec, DAG.getConstant(OrigElt, IndexTy)); 8508 } 8509 8510 // Perform only after legalization to ensure build_vector / vector_shuffle 8511 // optimizations have already been done. 8512 if (!LegalOperations) return SDValue(); 8513 8514 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 8515 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 8516 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 8517 8518 if (ConstEltNo) { 8519 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 8520 bool NewLoad = false; 8521 bool BCNumEltsChanged = false; 8522 EVT ExtVT = VT.getVectorElementType(); 8523 EVT LVT = ExtVT; 8524 8525 // If the result of load has to be truncated, then it's not necessarily 8526 // profitable. 8527 if (NVT.bitsLT(LVT) && !TLI.isTruncateFree(LVT, NVT)) 8528 return SDValue(); 8529 8530 if (InVec.getOpcode() == ISD::BITCAST) { 8531 // Don't duplicate a load with other uses. 8532 if (!InVec.hasOneUse()) 8533 return SDValue(); 8534 8535 EVT BCVT = InVec.getOperand(0).getValueType(); 8536 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) 8537 return SDValue(); 8538 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 8539 BCNumEltsChanged = true; 8540 InVec = InVec.getOperand(0); 8541 ExtVT = BCVT.getVectorElementType(); 8542 NewLoad = true; 8543 } 8544 8545 LoadSDNode *LN0 = NULL; 8546 const ShuffleVectorSDNode *SVN = NULL; 8547 if (ISD::isNormalLoad(InVec.getNode())) { 8548 LN0 = cast<LoadSDNode>(InVec); 8549 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 8550 InVec.getOperand(0).getValueType() == ExtVT && 8551 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 8552 // Don't duplicate a load with other uses. 8553 if (!InVec.hasOneUse()) 8554 return SDValue(); 8555 8556 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 8557 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 8558 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 8559 // => 8560 // (load $addr+1*size) 8561 8562 // Don't duplicate a load with other uses. 8563 if (!InVec.hasOneUse()) 8564 return SDValue(); 8565 8566 // If the bit convert changed the number of elements, it is unsafe 8567 // to examine the mask. 8568 if (BCNumEltsChanged) 8569 return SDValue(); 8570 8571 // Select the input vector, guarding against out of range extract vector. 8572 unsigned NumElems = VT.getVectorNumElements(); 8573 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt); 8574 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 8575 8576 if (InVec.getOpcode() == ISD::BITCAST) { 8577 // Don't duplicate a load with other uses. 8578 if (!InVec.hasOneUse()) 8579 return SDValue(); 8580 8581 InVec = InVec.getOperand(0); 8582 } 8583 if (ISD::isNormalLoad(InVec.getNode())) { 8584 LN0 = cast<LoadSDNode>(InVec); 8585 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems; 8586 } 8587 } 8588 8589 // Make sure we found a non-volatile load and the extractelement is 8590 // the only use. 8591 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile()) 8592 return SDValue(); 8593 8594 // If Idx was -1 above, Elt is going to be -1, so just return undef. 8595 if (Elt == -1) 8596 return DAG.getUNDEF(LVT); 8597 8598 unsigned Align = LN0->getAlignment(); 8599 if (NewLoad) { 8600 // Check the resultant load doesn't need a higher alignment than the 8601 // original load. 8602 unsigned NewAlign = 8603 TLI.getDataLayout() 8604 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext())); 8605 8606 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 8607 return SDValue(); 8608 8609 Align = NewAlign; 8610 } 8611 8612 SDValue NewPtr = LN0->getBasePtr(); 8613 unsigned PtrOff = 0; 8614 8615 if (Elt) { 8616 PtrOff = LVT.getSizeInBits() * Elt / 8; 8617 EVT PtrType = NewPtr.getValueType(); 8618 if (TLI.isBigEndian()) 8619 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 8620 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 8621 DAG.getConstant(PtrOff, PtrType)); 8622 } 8623 8624 // The replacement we need to do here is a little tricky: we need to 8625 // replace an extractelement of a load with a load. 8626 // Use ReplaceAllUsesOfValuesWith to do the replacement. 8627 // Note that this replacement assumes that the extractvalue is the only 8628 // use of the load; that's okay because we don't want to perform this 8629 // transformation in other cases anyway. 8630 SDValue Load; 8631 SDValue Chain; 8632 if (NVT.bitsGT(LVT)) { 8633 // If the result type of vextract is wider than the load, then issue an 8634 // extending load instead. 8635 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, LVT) 8636 ? ISD::ZEXTLOAD : ISD::EXTLOAD; 8637 Load = DAG.getExtLoad(ExtType, N->getDebugLoc(), NVT, LN0->getChain(), 8638 NewPtr, LN0->getPointerInfo().getWithOffset(PtrOff), 8639 LVT, LN0->isVolatile(), LN0->isNonTemporal(),Align); 8640 Chain = Load.getValue(1); 8641 } else { 8642 Load = DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 8643 LN0->getPointerInfo().getWithOffset(PtrOff), 8644 LN0->isVolatile(), LN0->isNonTemporal(), 8645 LN0->isInvariant(), Align); 8646 Chain = Load.getValue(1); 8647 if (NVT.bitsLT(LVT)) 8648 Load = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Load); 8649 else 8650 Load = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), NVT, Load); 8651 } 8652 WorkListRemover DeadNodes(*this); 8653 SDValue From[] = { SDValue(N, 0), SDValue(LN0,1) }; 8654 SDValue To[] = { Load, Chain }; 8655 DAG.ReplaceAllUsesOfValuesWith(From, To, 2); 8656 // Since we're explcitly calling ReplaceAllUses, add the new node to the 8657 // worklist explicitly as well. 8658 AddToWorkList(Load.getNode()); 8659 AddUsersToWorkList(Load.getNode()); // Add users too 8660 // Make sure to revisit this node to clean it up; it will usually be dead. 8661 AddToWorkList(N); 8662 return SDValue(N, 0); 8663 } 8664 8665 return SDValue(); 8666} 8667 8668// Simplify (build_vec (ext )) to (bitcast (build_vec )) 8669SDValue DAGCombiner::reduceBuildVecExtToExtBuildVec(SDNode *N) { 8670 // We perform this optimization post type-legalization because 8671 // the type-legalizer often scalarizes integer-promoted vectors. 8672 // Performing this optimization before may create bit-casts which 8673 // will be type-legalized to complex code sequences. 8674 // We perform this optimization only before the operation legalizer because we 8675 // may introduce illegal operations. 8676 if (Level != AfterLegalizeVectorOps && Level != AfterLegalizeTypes) 8677 return SDValue(); 8678 8679 unsigned NumInScalars = N->getNumOperands(); 8680 DebugLoc dl = N->getDebugLoc(); 8681 EVT VT = N->getValueType(0); 8682 8683 // Check to see if this is a BUILD_VECTOR of a bunch of values 8684 // which come from any_extend or zero_extend nodes. If so, we can create 8685 // a new BUILD_VECTOR using bit-casts which may enable other BUILD_VECTOR 8686 // optimizations. We do not handle sign-extend because we can't fill the sign 8687 // using shuffles. 8688 EVT SourceType = MVT::Other; 8689 bool AllAnyExt = true; 8690 8691 for (unsigned i = 0; i != NumInScalars; ++i) { 8692 SDValue In = N->getOperand(i); 8693 // Ignore undef inputs. 8694 if (In.getOpcode() == ISD::UNDEF) continue; 8695 8696 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND; 8697 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND; 8698 8699 // Abort if the element is not an extension. 8700 if (!ZeroExt && !AnyExt) { 8701 SourceType = MVT::Other; 8702 break; 8703 } 8704 8705 // The input is a ZeroExt or AnyExt. Check the original type. 8706 EVT InTy = In.getOperand(0).getValueType(); 8707 8708 // Check that all of the widened source types are the same. 8709 if (SourceType == MVT::Other) 8710 // First time. 8711 SourceType = InTy; 8712 else if (InTy != SourceType) { 8713 // Multiple income types. Abort. 8714 SourceType = MVT::Other; 8715 break; 8716 } 8717 8718 // Check if all of the extends are ANY_EXTENDs. 8719 AllAnyExt &= AnyExt; 8720 } 8721 8722 // In order to have valid types, all of the inputs must be extended from the 8723 // same source type and all of the inputs must be any or zero extend. 8724 // Scalar sizes must be a power of two. 8725 EVT OutScalarTy = VT.getScalarType(); 8726 bool ValidTypes = SourceType != MVT::Other && 8727 isPowerOf2_32(OutScalarTy.getSizeInBits()) && 8728 isPowerOf2_32(SourceType.getSizeInBits()); 8729 8730 // Create a new simpler BUILD_VECTOR sequence which other optimizations can 8731 // turn into a single shuffle instruction. 8732 if (!ValidTypes) 8733 return SDValue(); 8734 8735 bool isLE = TLI.isLittleEndian(); 8736 unsigned ElemRatio = OutScalarTy.getSizeInBits()/SourceType.getSizeInBits(); 8737 assert(ElemRatio > 1 && "Invalid element size ratio"); 8738 SDValue Filler = AllAnyExt ? DAG.getUNDEF(SourceType): 8739 DAG.getConstant(0, SourceType); 8740 8741 unsigned NewBVElems = ElemRatio * VT.getVectorNumElements(); 8742 SmallVector<SDValue, 8> Ops(NewBVElems, Filler); 8743 8744 // Populate the new build_vector 8745 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 8746 SDValue Cast = N->getOperand(i); 8747 assert((Cast.getOpcode() == ISD::ANY_EXTEND || 8748 Cast.getOpcode() == ISD::ZERO_EXTEND || 8749 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode"); 8750 SDValue In; 8751 if (Cast.getOpcode() == ISD::UNDEF) 8752 In = DAG.getUNDEF(SourceType); 8753 else 8754 In = Cast->getOperand(0); 8755 unsigned Index = isLE ? (i * ElemRatio) : 8756 (i * ElemRatio + (ElemRatio - 1)); 8757 8758 assert(Index < Ops.size() && "Invalid index"); 8759 Ops[Index] = In; 8760 } 8761 8762 // The type of the new BUILD_VECTOR node. 8763 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems); 8764 assert(VecVT.getSizeInBits() == VT.getSizeInBits() && 8765 "Invalid vector size"); 8766 // Check if the new vector type is legal. 8767 if (!isTypeLegal(VecVT)) return SDValue(); 8768 8769 // Make the new BUILD_VECTOR. 8770 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], Ops.size()); 8771 8772 // The new BUILD_VECTOR node has the potential to be further optimized. 8773 AddToWorkList(BV.getNode()); 8774 // Bitcast to the desired type. 8775 return DAG.getNode(ISD::BITCAST, dl, VT, BV); 8776} 8777 8778SDValue DAGCombiner::reduceBuildVecConvertToConvertBuildVec(SDNode *N) { 8779 EVT VT = N->getValueType(0); 8780 8781 unsigned NumInScalars = N->getNumOperands(); 8782 DebugLoc dl = N->getDebugLoc(); 8783 8784 EVT SrcVT = MVT::Other; 8785 unsigned Opcode = ISD::DELETED_NODE; 8786 unsigned NumDefs = 0; 8787 8788 for (unsigned i = 0; i != NumInScalars; ++i) { 8789 SDValue In = N->getOperand(i); 8790 unsigned Opc = In.getOpcode(); 8791 8792 if (Opc == ISD::UNDEF) 8793 continue; 8794 8795 // If all scalar values are floats and converted from integers. 8796 if (Opcode == ISD::DELETED_NODE && 8797 (Opc == ISD::UINT_TO_FP || Opc == ISD::SINT_TO_FP)) { 8798 Opcode = Opc; 8799 } 8800 8801 if (Opc != Opcode) 8802 return SDValue(); 8803 8804 EVT InVT = In.getOperand(0).getValueType(); 8805 8806 // If all scalar values are typed differently, bail out. It's chosen to 8807 // simplify BUILD_VECTOR of integer types. 8808 if (SrcVT == MVT::Other) 8809 SrcVT = InVT; 8810 if (SrcVT != InVT) 8811 return SDValue(); 8812 NumDefs++; 8813 } 8814 8815 // If the vector has just one element defined, it's not worth to fold it into 8816 // a vectorized one. 8817 if (NumDefs < 2) 8818 return SDValue(); 8819 8820 assert((Opcode == ISD::UINT_TO_FP || Opcode == ISD::SINT_TO_FP) 8821 && "Should only handle conversion from integer to float."); 8822 assert(SrcVT != MVT::Other && "Cannot determine source type!"); 8823 8824 EVT NVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumInScalars); 8825 8826 if (!TLI.isOperationLegalOrCustom(Opcode, NVT)) 8827 return SDValue(); 8828 8829 SmallVector<SDValue, 8> Opnds; 8830 for (unsigned i = 0; i != NumInScalars; ++i) { 8831 SDValue In = N->getOperand(i); 8832 8833 if (In.getOpcode() == ISD::UNDEF) 8834 Opnds.push_back(DAG.getUNDEF(SrcVT)); 8835 else 8836 Opnds.push_back(In.getOperand(0)); 8837 } 8838 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, 8839 &Opnds[0], Opnds.size()); 8840 AddToWorkList(BV.getNode()); 8841 8842 return DAG.getNode(Opcode, dl, VT, BV); 8843} 8844 8845SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 8846 unsigned NumInScalars = N->getNumOperands(); 8847 DebugLoc dl = N->getDebugLoc(); 8848 EVT VT = N->getValueType(0); 8849 8850 // A vector built entirely of undefs is undef. 8851 if (ISD::allOperandsUndef(N)) 8852 return DAG.getUNDEF(VT); 8853 8854 SDValue V = reduceBuildVecExtToExtBuildVec(N); 8855 if (V.getNode()) 8856 return V; 8857 8858 V = reduceBuildVecConvertToConvertBuildVec(N); 8859 if (V.getNode()) 8860 return V; 8861 8862 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 8863 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 8864 // at most two distinct vectors, turn this into a shuffle node. 8865 8866 // May only combine to shuffle after legalize if shuffle is legal. 8867 if (LegalOperations && 8868 !TLI.isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, VT)) 8869 return SDValue(); 8870 8871 SDValue VecIn1, VecIn2; 8872 for (unsigned i = 0; i != NumInScalars; ++i) { 8873 // Ignore undef inputs. 8874 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 8875 8876 // If this input is something other than a EXTRACT_VECTOR_ELT with a 8877 // constant index, bail out. 8878 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 8879 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 8880 VecIn1 = VecIn2 = SDValue(0, 0); 8881 break; 8882 } 8883 8884 // We allow up to two distinct input vectors. 8885 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 8886 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 8887 continue; 8888 8889 if (VecIn1.getNode() == 0) { 8890 VecIn1 = ExtractedFromVec; 8891 } else if (VecIn2.getNode() == 0) { 8892 VecIn2 = ExtractedFromVec; 8893 } else { 8894 // Too many inputs. 8895 VecIn1 = VecIn2 = SDValue(0, 0); 8896 break; 8897 } 8898 } 8899 8900 // If everything is good, we can make a shuffle operation. 8901 if (VecIn1.getNode()) { 8902 SmallVector<int, 8> Mask; 8903 for (unsigned i = 0; i != NumInScalars; ++i) { 8904 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 8905 Mask.push_back(-1); 8906 continue; 8907 } 8908 8909 // If extracting from the first vector, just use the index directly. 8910 SDValue Extract = N->getOperand(i); 8911 SDValue ExtVal = Extract.getOperand(1); 8912 if (Extract.getOperand(0) == VecIn1) { 8913 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 8914 if (ExtIndex > VT.getVectorNumElements()) 8915 return SDValue(); 8916 8917 Mask.push_back(ExtIndex); 8918 continue; 8919 } 8920 8921 // Otherwise, use InIdx + VecSize 8922 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 8923 Mask.push_back(Idx+NumInScalars); 8924 } 8925 8926 // We can't generate a shuffle node with mismatched input and output types. 8927 // Attempt to transform a single input vector to the correct type. 8928 if ((VT != VecIn1.getValueType())) { 8929 // We don't support shuffeling between TWO values of different types. 8930 if (VecIn2.getNode() != 0) 8931 return SDValue(); 8932 8933 // We only support widening of vectors which are half the size of the 8934 // output registers. For example XMM->YMM widening on X86 with AVX. 8935 if (VecIn1.getValueType().getSizeInBits()*2 != VT.getSizeInBits()) 8936 return SDValue(); 8937 8938 // If the input vector type has a different base type to the output 8939 // vector type, bail out. 8940 if (VecIn1.getValueType().getVectorElementType() != 8941 VT.getVectorElementType()) 8942 return SDValue(); 8943 8944 // Widen the input vector by adding undef values. 8945 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 8946 VecIn1, DAG.getUNDEF(VecIn1.getValueType())); 8947 } 8948 8949 // If VecIn2 is unused then change it to undef. 8950 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 8951 8952 // Check that we were able to transform all incoming values to the same 8953 // type. 8954 if (VecIn2.getValueType() != VecIn1.getValueType() || 8955 VecIn1.getValueType() != VT) 8956 return SDValue(); 8957 8958 // Only type-legal BUILD_VECTOR nodes are converted to shuffle nodes. 8959 if (!isTypeLegal(VT)) 8960 return SDValue(); 8961 8962 // Return the new VECTOR_SHUFFLE node. 8963 SDValue Ops[2]; 8964 Ops[0] = VecIn1; 8965 Ops[1] = VecIn2; 8966 return DAG.getVectorShuffle(VT, dl, Ops[0], Ops[1], &Mask[0]); 8967 } 8968 8969 return SDValue(); 8970} 8971 8972SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 8973 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 8974 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 8975 // inputs come from at most two distinct vectors, turn this into a shuffle 8976 // node. 8977 8978 // If we only have one input vector, we don't need to do any concatenation. 8979 if (N->getNumOperands() == 1) 8980 return N->getOperand(0); 8981 8982 // Check if all of the operands are undefs. 8983 if (ISD::allOperandsUndef(N)) 8984 return DAG.getUNDEF(N->getValueType(0)); 8985 8986 return SDValue(); 8987} 8988 8989SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) { 8990 EVT NVT = N->getValueType(0); 8991 SDValue V = N->getOperand(0); 8992 8993 if (V->getOpcode() == ISD::CONCAT_VECTORS) { 8994 // Combine: 8995 // (extract_subvec (concat V1, V2, ...), i) 8996 // Into: 8997 // Vi if possible 8998 // Only operand 0 is checked as 'concat' assumes all inputs of the same type. 8999 if (V->getOperand(0).getValueType() != NVT) 9000 return SDValue(); 9001 unsigned Idx = dyn_cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); 9002 unsigned NumElems = NVT.getVectorNumElements(); 9003 assert((Idx % NumElems) == 0 && 9004 "IDX in concat is not a multiple of the result vector length."); 9005 return V->getOperand(Idx / NumElems); 9006 } 9007 9008 // Skip bitcasting 9009 if (V->getOpcode() == ISD::BITCAST) 9010 V = V.getOperand(0); 9011 9012 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) { 9013 DebugLoc dl = N->getDebugLoc(); 9014 // Handle only simple case where vector being inserted and vector 9015 // being extracted are of same type, and are half size of larger vectors. 9016 EVT BigVT = V->getOperand(0).getValueType(); 9017 EVT SmallVT = V->getOperand(1).getValueType(); 9018 if (!NVT.bitsEq(SmallVT) || NVT.getSizeInBits()*2 != BigVT.getSizeInBits()) 9019 return SDValue(); 9020 9021 // Only handle cases where both indexes are constants with the same type. 9022 ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(N->getOperand(1)); 9023 ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(V->getOperand(2)); 9024 9025 if (InsIdx && ExtIdx && 9026 InsIdx->getValueType(0).getSizeInBits() <= 64 && 9027 ExtIdx->getValueType(0).getSizeInBits() <= 64) { 9028 // Combine: 9029 // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx) 9030 // Into: 9031 // indices are equal or bit offsets are equal => V1 9032 // otherwise => (extract_subvec V1, ExtIdx) 9033 if (InsIdx->getZExtValue() * SmallVT.getScalarType().getSizeInBits() == 9034 ExtIdx->getZExtValue() * NVT.getScalarType().getSizeInBits()) 9035 return DAG.getNode(ISD::BITCAST, dl, NVT, V->getOperand(1)); 9036 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, 9037 DAG.getNode(ISD::BITCAST, dl, 9038 N->getOperand(0).getValueType(), 9039 V->getOperand(0)), N->getOperand(1)); 9040 } 9041 } 9042 9043 return SDValue(); 9044} 9045 9046SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 9047 EVT VT = N->getValueType(0); 9048 unsigned NumElts = VT.getVectorNumElements(); 9049 9050 SDValue N0 = N->getOperand(0); 9051 SDValue N1 = N->getOperand(1); 9052 9053 assert(N0.getValueType() == VT && "Vector shuffle must be normalized in DAG"); 9054 9055 // Canonicalize shuffle undef, undef -> undef 9056 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 9057 return DAG.getUNDEF(VT); 9058 9059 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 9060 9061 // Canonicalize shuffle v, v -> v, undef 9062 if (N0 == N1) { 9063 SmallVector<int, 8> NewMask; 9064 for (unsigned i = 0; i != NumElts; ++i) { 9065 int Idx = SVN->getMaskElt(i); 9066 if (Idx >= (int)NumElts) Idx -= NumElts; 9067 NewMask.push_back(Idx); 9068 } 9069 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, DAG.getUNDEF(VT), 9070 &NewMask[0]); 9071 } 9072 9073 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask. 9074 if (N0.getOpcode() == ISD::UNDEF) { 9075 SmallVector<int, 8> NewMask; 9076 for (unsigned i = 0; i != NumElts; ++i) { 9077 int Idx = SVN->getMaskElt(i); 9078 if (Idx >= 0) { 9079 if (Idx < (int)NumElts) 9080 Idx += NumElts; 9081 else 9082 Idx -= NumElts; 9083 } 9084 NewMask.push_back(Idx); 9085 } 9086 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N1, DAG.getUNDEF(VT), 9087 &NewMask[0]); 9088 } 9089 9090 // Remove references to rhs if it is undef 9091 if (N1.getOpcode() == ISD::UNDEF) { 9092 bool Changed = false; 9093 SmallVector<int, 8> NewMask; 9094 for (unsigned i = 0; i != NumElts; ++i) { 9095 int Idx = SVN->getMaskElt(i); 9096 if (Idx >= (int)NumElts) { 9097 Idx = -1; 9098 Changed = true; 9099 } 9100 NewMask.push_back(Idx); 9101 } 9102 if (Changed) 9103 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, N1, &NewMask[0]); 9104 } 9105 9106 // If it is a splat, check if the argument vector is another splat or a 9107 // build_vector with all scalar elements the same. 9108 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) { 9109 SDNode *V = N0.getNode(); 9110 9111 // If this is a bit convert that changes the element type of the vector but 9112 // not the number of vector elements, look through it. Be careful not to 9113 // look though conversions that change things like v4f32 to v2f64. 9114 if (V->getOpcode() == ISD::BITCAST) { 9115 SDValue ConvInput = V->getOperand(0); 9116 if (ConvInput.getValueType().isVector() && 9117 ConvInput.getValueType().getVectorNumElements() == NumElts) 9118 V = ConvInput.getNode(); 9119 } 9120 9121 if (V->getOpcode() == ISD::BUILD_VECTOR) { 9122 assert(V->getNumOperands() == NumElts && 9123 "BUILD_VECTOR has wrong number of operands"); 9124 SDValue Base; 9125 bool AllSame = true; 9126 for (unsigned i = 0; i != NumElts; ++i) { 9127 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 9128 Base = V->getOperand(i); 9129 break; 9130 } 9131 } 9132 // Splat of <u, u, u, u>, return <u, u, u, u> 9133 if (!Base.getNode()) 9134 return N0; 9135 for (unsigned i = 0; i != NumElts; ++i) { 9136 if (V->getOperand(i) != Base) { 9137 AllSame = false; 9138 break; 9139 } 9140 } 9141 // Splat of <x, x, x, x>, return <x, x, x, x> 9142 if (AllSame) 9143 return N0; 9144 } 9145 } 9146 9147 // If this shuffle node is simply a swizzle of another shuffle node, 9148 // and it reverses the swizzle of the previous shuffle then we can 9149 // optimize shuffle(shuffle(x, undef), undef) -> x. 9150 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG && 9151 N1.getOpcode() == ISD::UNDEF) { 9152 9153 ShuffleVectorSDNode *OtherSV = cast<ShuffleVectorSDNode>(N0); 9154 9155 // Shuffle nodes can only reverse shuffles with a single non-undef value. 9156 if (N0.getOperand(1).getOpcode() != ISD::UNDEF) 9157 return SDValue(); 9158 9159 // The incoming shuffle must be of the same type as the result of the 9160 // current shuffle. 9161 assert(OtherSV->getOperand(0).getValueType() == VT && 9162 "Shuffle types don't match"); 9163 9164 for (unsigned i = 0; i != NumElts; ++i) { 9165 int Idx = SVN->getMaskElt(i); 9166 assert(Idx < (int)NumElts && "Index references undef operand"); 9167 // Next, this index comes from the first value, which is the incoming 9168 // shuffle. Adopt the incoming index. 9169 if (Idx >= 0) 9170 Idx = OtherSV->getMaskElt(Idx); 9171 9172 // The combined shuffle must map each index to itself. 9173 if (Idx >= 0 && (unsigned)Idx != i) 9174 return SDValue(); 9175 } 9176 9177 return OtherSV->getOperand(0); 9178 } 9179 9180 return SDValue(); 9181} 9182 9183SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) { 9184 if (!TLI.getShouldFoldAtomicFences()) 9185 return SDValue(); 9186 9187 SDValue atomic = N->getOperand(0); 9188 switch (atomic.getOpcode()) { 9189 case ISD::ATOMIC_CMP_SWAP: 9190 case ISD::ATOMIC_SWAP: 9191 case ISD::ATOMIC_LOAD_ADD: 9192 case ISD::ATOMIC_LOAD_SUB: 9193 case ISD::ATOMIC_LOAD_AND: 9194 case ISD::ATOMIC_LOAD_OR: 9195 case ISD::ATOMIC_LOAD_XOR: 9196 case ISD::ATOMIC_LOAD_NAND: 9197 case ISD::ATOMIC_LOAD_MIN: 9198 case ISD::ATOMIC_LOAD_MAX: 9199 case ISD::ATOMIC_LOAD_UMIN: 9200 case ISD::ATOMIC_LOAD_UMAX: 9201 break; 9202 default: 9203 return SDValue(); 9204 } 9205 9206 SDValue fence = atomic.getOperand(0); 9207 if (fence.getOpcode() != ISD::MEMBARRIER) 9208 return SDValue(); 9209 9210 switch (atomic.getOpcode()) { 9211 case ISD::ATOMIC_CMP_SWAP: 9212 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 9213 fence.getOperand(0), 9214 atomic.getOperand(1), atomic.getOperand(2), 9215 atomic.getOperand(3)), atomic.getResNo()); 9216 case ISD::ATOMIC_SWAP: 9217 case ISD::ATOMIC_LOAD_ADD: 9218 case ISD::ATOMIC_LOAD_SUB: 9219 case ISD::ATOMIC_LOAD_AND: 9220 case ISD::ATOMIC_LOAD_OR: 9221 case ISD::ATOMIC_LOAD_XOR: 9222 case ISD::ATOMIC_LOAD_NAND: 9223 case ISD::ATOMIC_LOAD_MIN: 9224 case ISD::ATOMIC_LOAD_MAX: 9225 case ISD::ATOMIC_LOAD_UMIN: 9226 case ISD::ATOMIC_LOAD_UMAX: 9227 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 9228 fence.getOperand(0), 9229 atomic.getOperand(1), atomic.getOperand(2)), 9230 atomic.getResNo()); 9231 default: 9232 return SDValue(); 9233 } 9234} 9235 9236/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 9237/// an AND to a vector_shuffle with the destination vector and a zero vector. 9238/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 9239/// vector_shuffle V, Zero, <0, 4, 2, 4> 9240SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 9241 EVT VT = N->getValueType(0); 9242 DebugLoc dl = N->getDebugLoc(); 9243 SDValue LHS = N->getOperand(0); 9244 SDValue RHS = N->getOperand(1); 9245 if (N->getOpcode() == ISD::AND) { 9246 if (RHS.getOpcode() == ISD::BITCAST) 9247 RHS = RHS.getOperand(0); 9248 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 9249 SmallVector<int, 8> Indices; 9250 unsigned NumElts = RHS.getNumOperands(); 9251 for (unsigned i = 0; i != NumElts; ++i) { 9252 SDValue Elt = RHS.getOperand(i); 9253 if (!isa<ConstantSDNode>(Elt)) 9254 return SDValue(); 9255 9256 if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 9257 Indices.push_back(i); 9258 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 9259 Indices.push_back(NumElts); 9260 else 9261 return SDValue(); 9262 } 9263 9264 // Let's see if the target supports this vector_shuffle. 9265 EVT RVT = RHS.getValueType(); 9266 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 9267 return SDValue(); 9268 9269 // Return the new VECTOR_SHUFFLE node. 9270 EVT EltVT = RVT.getVectorElementType(); 9271 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 9272 DAG.getConstant(0, EltVT)); 9273 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 9274 RVT, &ZeroOps[0], ZeroOps.size()); 9275 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS); 9276 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 9277 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf); 9278 } 9279 } 9280 9281 return SDValue(); 9282} 9283 9284/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 9285SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 9286 assert(N->getValueType(0).isVector() && 9287 "SimplifyVBinOp only works on vectors!"); 9288 9289 SDValue LHS = N->getOperand(0); 9290 SDValue RHS = N->getOperand(1); 9291 SDValue Shuffle = XformToShuffleWithZero(N); 9292 if (Shuffle.getNode()) return Shuffle; 9293 9294 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 9295 // this operation. 9296 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 9297 RHS.getOpcode() == ISD::BUILD_VECTOR) { 9298 SmallVector<SDValue, 8> Ops; 9299 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 9300 SDValue LHSOp = LHS.getOperand(i); 9301 SDValue RHSOp = RHS.getOperand(i); 9302 // If these two elements can't be folded, bail out. 9303 if ((LHSOp.getOpcode() != ISD::UNDEF && 9304 LHSOp.getOpcode() != ISD::Constant && 9305 LHSOp.getOpcode() != ISD::ConstantFP) || 9306 (RHSOp.getOpcode() != ISD::UNDEF && 9307 RHSOp.getOpcode() != ISD::Constant && 9308 RHSOp.getOpcode() != ISD::ConstantFP)) 9309 break; 9310 9311 // Can't fold divide by zero. 9312 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 9313 N->getOpcode() == ISD::FDIV) { 9314 if ((RHSOp.getOpcode() == ISD::Constant && 9315 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 9316 (RHSOp.getOpcode() == ISD::ConstantFP && 9317 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 9318 break; 9319 } 9320 9321 EVT VT = LHSOp.getValueType(); 9322 EVT RVT = RHSOp.getValueType(); 9323 if (RVT != VT) { 9324 // Integer BUILD_VECTOR operands may have types larger than the element 9325 // size (e.g., when the element type is not legal). Prior to type 9326 // legalization, the types may not match between the two BUILD_VECTORS. 9327 // Truncate one of the operands to make them match. 9328 if (RVT.getSizeInBits() > VT.getSizeInBits()) { 9329 RHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, RHSOp); 9330 } else { 9331 LHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), RVT, LHSOp); 9332 VT = RVT; 9333 } 9334 } 9335 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), VT, 9336 LHSOp, RHSOp); 9337 if (FoldOp.getOpcode() != ISD::UNDEF && 9338 FoldOp.getOpcode() != ISD::Constant && 9339 FoldOp.getOpcode() != ISD::ConstantFP) 9340 break; 9341 Ops.push_back(FoldOp); 9342 AddToWorkList(FoldOp.getNode()); 9343 } 9344 9345 if (Ops.size() == LHS.getNumOperands()) 9346 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 9347 LHS.getValueType(), &Ops[0], Ops.size()); 9348 } 9349 9350 return SDValue(); 9351} 9352 9353/// SimplifyVUnaryOp - Visit a binary vector operation, like FABS/FNEG. 9354SDValue DAGCombiner::SimplifyVUnaryOp(SDNode *N) { 9355 assert(N->getValueType(0).isVector() && 9356 "SimplifyVUnaryOp only works on vectors!"); 9357 9358 SDValue N0 = N->getOperand(0); 9359 9360 if (N0.getOpcode() != ISD::BUILD_VECTOR) 9361 return SDValue(); 9362 9363 // Operand is a BUILD_VECTOR node, see if we can constant fold it. 9364 SmallVector<SDValue, 8> Ops; 9365 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) { 9366 SDValue Op = N0.getOperand(i); 9367 if (Op.getOpcode() != ISD::UNDEF && 9368 Op.getOpcode() != ISD::ConstantFP) 9369 break; 9370 EVT EltVT = Op.getValueType(); 9371 SDValue FoldOp = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), EltVT, Op); 9372 if (FoldOp.getOpcode() != ISD::UNDEF && 9373 FoldOp.getOpcode() != ISD::ConstantFP) 9374 break; 9375 Ops.push_back(FoldOp); 9376 AddToWorkList(FoldOp.getNode()); 9377 } 9378 9379 if (Ops.size() != N0.getNumOperands()) 9380 return SDValue(); 9381 9382 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 9383 N0.getValueType(), &Ops[0], Ops.size()); 9384} 9385 9386SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 9387 SDValue N1, SDValue N2){ 9388 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 9389 9390 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 9391 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 9392 9393 // If we got a simplified select_cc node back from SimplifySelectCC, then 9394 // break it down into a new SETCC node, and a new SELECT node, and then return 9395 // the SELECT node, since we were called with a SELECT node. 9396 if (SCC.getNode()) { 9397 // Check to see if we got a select_cc back (to turn into setcc/select). 9398 // Otherwise, just return whatever node we got back, like fabs. 9399 if (SCC.getOpcode() == ISD::SELECT_CC) { 9400 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 9401 N0.getValueType(), 9402 SCC.getOperand(0), SCC.getOperand(1), 9403 SCC.getOperand(4)); 9404 AddToWorkList(SETCC.getNode()); 9405 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 9406 SCC.getOperand(2), SCC.getOperand(3), SETCC); 9407 } 9408 9409 return SCC; 9410 } 9411 return SDValue(); 9412} 9413 9414/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 9415/// are the two values being selected between, see if we can simplify the 9416/// select. Callers of this should assume that TheSelect is deleted if this 9417/// returns true. As such, they should return the appropriate thing (e.g. the 9418/// node) back to the top-level of the DAG combiner loop to avoid it being 9419/// looked at. 9420bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 9421 SDValue RHS) { 9422 9423 // Cannot simplify select with vector condition 9424 if (TheSelect->getOperand(0).getValueType().isVector()) return false; 9425 9426 // If this is a select from two identical things, try to pull the operation 9427 // through the select. 9428 if (LHS.getOpcode() != RHS.getOpcode() || 9429 !LHS.hasOneUse() || !RHS.hasOneUse()) 9430 return false; 9431 9432 // If this is a load and the token chain is identical, replace the select 9433 // of two loads with a load through a select of the address to load from. 9434 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 9435 // constants have been dropped into the constant pool. 9436 if (LHS.getOpcode() == ISD::LOAD) { 9437 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 9438 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 9439 9440 // Token chains must be identical. 9441 if (LHS.getOperand(0) != RHS.getOperand(0) || 9442 // Do not let this transformation reduce the number of volatile loads. 9443 LLD->isVolatile() || RLD->isVolatile() || 9444 // If this is an EXTLOAD, the VT's must match. 9445 LLD->getMemoryVT() != RLD->getMemoryVT() || 9446 // If this is an EXTLOAD, the kind of extension must match. 9447 (LLD->getExtensionType() != RLD->getExtensionType() && 9448 // The only exception is if one of the extensions is anyext. 9449 LLD->getExtensionType() != ISD::EXTLOAD && 9450 RLD->getExtensionType() != ISD::EXTLOAD) || 9451 // FIXME: this discards src value information. This is 9452 // over-conservative. It would be beneficial to be able to remember 9453 // both potential memory locations. Since we are discarding 9454 // src value info, don't do the transformation if the memory 9455 // locations are not in the default address space. 9456 LLD->getPointerInfo().getAddrSpace() != 0 || 9457 RLD->getPointerInfo().getAddrSpace() != 0 || 9458 !TLI.isOperationLegalOrCustom(TheSelect->getOpcode(), 9459 LLD->getBasePtr().getValueType())) 9460 return false; 9461 9462 // Check that the select condition doesn't reach either load. If so, 9463 // folding this will induce a cycle into the DAG. If not, this is safe to 9464 // xform, so create a select of the addresses. 9465 SDValue Addr; 9466 if (TheSelect->getOpcode() == ISD::SELECT) { 9467 SDNode *CondNode = TheSelect->getOperand(0).getNode(); 9468 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) || 9469 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode))) 9470 return false; 9471 // The loads must not depend on one another. 9472 if (LLD->isPredecessorOf(RLD) || 9473 RLD->isPredecessorOf(LLD)) 9474 return false; 9475 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 9476 LLD->getBasePtr().getValueType(), 9477 TheSelect->getOperand(0), LLD->getBasePtr(), 9478 RLD->getBasePtr()); 9479 } else { // Otherwise SELECT_CC 9480 SDNode *CondLHS = TheSelect->getOperand(0).getNode(); 9481 SDNode *CondRHS = TheSelect->getOperand(1).getNode(); 9482 9483 if ((LLD->hasAnyUseOfValue(1) && 9484 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) || 9485 (RLD->hasAnyUseOfValue(1) && 9486 (RLD->isPredecessorOf(CondLHS) || RLD->isPredecessorOf(CondRHS)))) 9487 return false; 9488 9489 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 9490 LLD->getBasePtr().getValueType(), 9491 TheSelect->getOperand(0), 9492 TheSelect->getOperand(1), 9493 LLD->getBasePtr(), RLD->getBasePtr(), 9494 TheSelect->getOperand(4)); 9495 } 9496 9497 SDValue Load; 9498 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 9499 Load = DAG.getLoad(TheSelect->getValueType(0), 9500 TheSelect->getDebugLoc(), 9501 // FIXME: Discards pointer info. 9502 LLD->getChain(), Addr, MachinePointerInfo(), 9503 LLD->isVolatile(), LLD->isNonTemporal(), 9504 LLD->isInvariant(), LLD->getAlignment()); 9505 } else { 9506 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ? 9507 RLD->getExtensionType() : LLD->getExtensionType(), 9508 TheSelect->getDebugLoc(), 9509 TheSelect->getValueType(0), 9510 // FIXME: Discards pointer info. 9511 LLD->getChain(), Addr, MachinePointerInfo(), 9512 LLD->getMemoryVT(), LLD->isVolatile(), 9513 LLD->isNonTemporal(), LLD->getAlignment()); 9514 } 9515 9516 // Users of the select now use the result of the load. 9517 CombineTo(TheSelect, Load); 9518 9519 // Users of the old loads now use the new load's chain. We know the 9520 // old-load value is dead now. 9521 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 9522 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 9523 return true; 9524 } 9525 9526 return false; 9527} 9528 9529/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 9530/// where 'cond' is the comparison specified by CC. 9531SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 9532 SDValue N2, SDValue N3, 9533 ISD::CondCode CC, bool NotExtCompare) { 9534 // (x ? y : y) -> y. 9535 if (N2 == N3) return N2; 9536 9537 EVT VT = N2.getValueType(); 9538 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 9539 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 9540 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 9541 9542 // Determine if the condition we're dealing with is constant 9543 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 9544 N0, N1, CC, DL, false); 9545 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 9546 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 9547 9548 // fold select_cc true, x, y -> x 9549 if (SCCC && !SCCC->isNullValue()) 9550 return N2; 9551 // fold select_cc false, x, y -> y 9552 if (SCCC && SCCC->isNullValue()) 9553 return N3; 9554 9555 // Check to see if we can simplify the select into an fabs node 9556 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 9557 // Allow either -0.0 or 0.0 9558 if (CFP->getValueAPF().isZero()) { 9559 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 9560 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 9561 N0 == N2 && N3.getOpcode() == ISD::FNEG && 9562 N2 == N3.getOperand(0)) 9563 return DAG.getNode(ISD::FABS, DL, VT, N0); 9564 9565 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 9566 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 9567 N0 == N3 && N2.getOpcode() == ISD::FNEG && 9568 N2.getOperand(0) == N3) 9569 return DAG.getNode(ISD::FABS, DL, VT, N3); 9570 } 9571 } 9572 9573 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 9574 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 9575 // in it. This is a win when the constant is not otherwise available because 9576 // it replaces two constant pool loads with one. We only do this if the FP 9577 // type is known to be legal, because if it isn't, then we are before legalize 9578 // types an we want the other legalization to happen first (e.g. to avoid 9579 // messing with soft float) and if the ConstantFP is not legal, because if 9580 // it is legal, we may not need to store the FP constant in a constant pool. 9581 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 9582 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 9583 if (TLI.isTypeLegal(N2.getValueType()) && 9584 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 9585 TargetLowering::Legal) && 9586 // If both constants have multiple uses, then we won't need to do an 9587 // extra load, they are likely around in registers for other users. 9588 (TV->hasOneUse() || FV->hasOneUse())) { 9589 Constant *Elts[] = { 9590 const_cast<ConstantFP*>(FV->getConstantFPValue()), 9591 const_cast<ConstantFP*>(TV->getConstantFPValue()) 9592 }; 9593 Type *FPTy = Elts[0]->getType(); 9594 const DataLayout &TD = *TLI.getDataLayout(); 9595 9596 // Create a ConstantArray of the two constants. 9597 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts); 9598 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 9599 TD.getPrefTypeAlignment(FPTy)); 9600 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 9601 9602 // Get the offsets to the 0 and 1 element of the array so that we can 9603 // select between them. 9604 SDValue Zero = DAG.getIntPtrConstant(0); 9605 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 9606 SDValue One = DAG.getIntPtrConstant(EltSize); 9607 9608 SDValue Cond = DAG.getSetCC(DL, 9609 TLI.getSetCCResultType(N0.getValueType()), 9610 N0, N1, CC); 9611 AddToWorkList(Cond.getNode()); 9612 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 9613 Cond, One, Zero); 9614 AddToWorkList(CstOffset.getNode()); 9615 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 9616 CstOffset); 9617 AddToWorkList(CPIdx.getNode()); 9618 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 9619 MachinePointerInfo::getConstantPool(), false, 9620 false, false, Alignment); 9621 9622 } 9623 } 9624 9625 // Check to see if we can perform the "gzip trick", transforming 9626 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 9627 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 9628 (N1C->isNullValue() || // (a < 0) ? b : 0 9629 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 9630 EVT XType = N0.getValueType(); 9631 EVT AType = N2.getValueType(); 9632 if (XType.bitsGE(AType)) { 9633 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 9634 // single-bit constant. 9635 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 9636 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 9637 ShCtV = XType.getSizeInBits()-ShCtV-1; 9638 SDValue ShCt = DAG.getConstant(ShCtV, 9639 getShiftAmountTy(N0.getValueType())); 9640 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 9641 XType, N0, ShCt); 9642 AddToWorkList(Shift.getNode()); 9643 9644 if (XType.bitsGT(AType)) { 9645 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 9646 AddToWorkList(Shift.getNode()); 9647 } 9648 9649 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 9650 } 9651 9652 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 9653 XType, N0, 9654 DAG.getConstant(XType.getSizeInBits()-1, 9655 getShiftAmountTy(N0.getValueType()))); 9656 AddToWorkList(Shift.getNode()); 9657 9658 if (XType.bitsGT(AType)) { 9659 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 9660 AddToWorkList(Shift.getNode()); 9661 } 9662 9663 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 9664 } 9665 } 9666 9667 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A) 9668 // where y is has a single bit set. 9669 // A plaintext description would be, we can turn the SELECT_CC into an AND 9670 // when the condition can be materialized as an all-ones register. Any 9671 // single bit-test can be materialized as an all-ones register with 9672 // shift-left and shift-right-arith. 9673 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND && 9674 N0->getValueType(0) == VT && 9675 N1C && N1C->isNullValue() && 9676 N2C && N2C->isNullValue()) { 9677 SDValue AndLHS = N0->getOperand(0); 9678 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1)); 9679 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) { 9680 // Shift the tested bit over the sign bit. 9681 APInt AndMask = ConstAndRHS->getAPIntValue(); 9682 SDValue ShlAmt = 9683 DAG.getConstant(AndMask.countLeadingZeros(), 9684 getShiftAmountTy(AndLHS.getValueType())); 9685 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt); 9686 9687 // Now arithmetic right shift it all the way over, so the result is either 9688 // all-ones, or zero. 9689 SDValue ShrAmt = 9690 DAG.getConstant(AndMask.getBitWidth()-1, 9691 getShiftAmountTy(Shl.getValueType())); 9692 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt); 9693 9694 return DAG.getNode(ISD::AND, DL, VT, Shr, N3); 9695 } 9696 } 9697 9698 // fold select C, 16, 0 -> shl C, 4 9699 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 9700 TLI.getBooleanContents(N0.getValueType().isVector()) == 9701 TargetLowering::ZeroOrOneBooleanContent) { 9702 9703 // If the caller doesn't want us to simplify this into a zext of a compare, 9704 // don't do it. 9705 if (NotExtCompare && N2C->getAPIntValue() == 1) 9706 return SDValue(); 9707 9708 // Get a SetCC of the condition 9709 // NOTE: Don't create a SETCC if it's not legal on this target. 9710 if (!LegalOperations || 9711 TLI.isOperationLegal(ISD::SETCC, 9712 LegalTypes ? TLI.getSetCCResultType(N0.getValueType()) : MVT::i1)) { 9713 SDValue Temp, SCC; 9714 // cast from setcc result type to select result type 9715 if (LegalTypes) { 9716 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 9717 N0, N1, CC); 9718 if (N2.getValueType().bitsLT(SCC.getValueType())) 9719 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), 9720 N2.getValueType()); 9721 else 9722 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 9723 N2.getValueType(), SCC); 9724 } else { 9725 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 9726 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 9727 N2.getValueType(), SCC); 9728 } 9729 9730 AddToWorkList(SCC.getNode()); 9731 AddToWorkList(Temp.getNode()); 9732 9733 if (N2C->getAPIntValue() == 1) 9734 return Temp; 9735 9736 // shl setcc result by log2 n2c 9737 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 9738 DAG.getConstant(N2C->getAPIntValue().logBase2(), 9739 getShiftAmountTy(Temp.getValueType()))); 9740 } 9741 } 9742 9743 // Check to see if this is the equivalent of setcc 9744 // FIXME: Turn all of these into setcc if setcc if setcc is legal 9745 // otherwise, go ahead with the folds. 9746 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 9747 EVT XType = N0.getValueType(); 9748 if (!LegalOperations || 9749 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 9750 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 9751 if (Res.getValueType() != VT) 9752 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 9753 return Res; 9754 } 9755 9756 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 9757 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 9758 (!LegalOperations || 9759 TLI.isOperationLegal(ISD::CTLZ, XType))) { 9760 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 9761 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 9762 DAG.getConstant(Log2_32(XType.getSizeInBits()), 9763 getShiftAmountTy(Ctlz.getValueType()))); 9764 } 9765 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 9766 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 9767 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 9768 XType, DAG.getConstant(0, XType), N0); 9769 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 9770 return DAG.getNode(ISD::SRL, DL, XType, 9771 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 9772 DAG.getConstant(XType.getSizeInBits()-1, 9773 getShiftAmountTy(XType))); 9774 } 9775 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 9776 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 9777 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 9778 DAG.getConstant(XType.getSizeInBits()-1, 9779 getShiftAmountTy(N0.getValueType()))); 9780 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 9781 } 9782 } 9783 9784 // Check to see if this is an integer abs. 9785 // select_cc setg[te] X, 0, X, -X -> 9786 // select_cc setgt X, -1, X, -X -> 9787 // select_cc setl[te] X, 0, -X, X -> 9788 // select_cc setlt X, 1, -X, X -> 9789 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 9790 if (N1C) { 9791 ConstantSDNode *SubC = NULL; 9792 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) || 9793 (N1C->isAllOnesValue() && CC == ISD::SETGT)) && 9794 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) 9795 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0)); 9796 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) || 9797 (N1C->isOne() && CC == ISD::SETLT)) && 9798 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) 9799 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0)); 9800 9801 EVT XType = N0.getValueType(); 9802 if (SubC && SubC->isNullValue() && XType.isInteger()) { 9803 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 9804 N0, 9805 DAG.getConstant(XType.getSizeInBits()-1, 9806 getShiftAmountTy(N0.getValueType()))); 9807 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 9808 XType, N0, Shift); 9809 AddToWorkList(Shift.getNode()); 9810 AddToWorkList(Add.getNode()); 9811 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 9812 } 9813 } 9814 9815 return SDValue(); 9816} 9817 9818/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 9819SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, 9820 SDValue N1, ISD::CondCode Cond, 9821 DebugLoc DL, bool foldBooleans) { 9822 TargetLowering::DAGCombinerInfo 9823 DagCombineInfo(DAG, Level, false, this); 9824 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 9825} 9826 9827/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 9828/// return a DAG expression to select that will generate the same value by 9829/// multiplying by a magic number. See: 9830/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 9831SDValue DAGCombiner::BuildSDIV(SDNode *N) { 9832 std::vector<SDNode*> Built; 9833 SDValue S = TLI.BuildSDIV(N, DAG, LegalOperations, &Built); 9834 9835 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 9836 ii != ee; ++ii) 9837 AddToWorkList(*ii); 9838 return S; 9839} 9840 9841/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 9842/// return a DAG expression to select that will generate the same value by 9843/// multiplying by a magic number. See: 9844/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 9845SDValue DAGCombiner::BuildUDIV(SDNode *N) { 9846 std::vector<SDNode*> Built; 9847 SDValue S = TLI.BuildUDIV(N, DAG, LegalOperations, &Built); 9848 9849 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 9850 ii != ee; ++ii) 9851 AddToWorkList(*ii); 9852 return S; 9853} 9854 9855/// FindBaseOffset - Return true if base is a frame index, which is known not 9856// to alias with anything but itself. Provides base object and offset as 9857// results. 9858static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset, 9859 const GlobalValue *&GV, const void *&CV) { 9860 // Assume it is a primitive operation. 9861 Base = Ptr; Offset = 0; GV = 0; CV = 0; 9862 9863 // If it's an adding a simple constant then integrate the offset. 9864 if (Base.getOpcode() == ISD::ADD) { 9865 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 9866 Base = Base.getOperand(0); 9867 Offset += C->getZExtValue(); 9868 } 9869 } 9870 9871 // Return the underlying GlobalValue, and update the Offset. Return false 9872 // for GlobalAddressSDNode since the same GlobalAddress may be represented 9873 // by multiple nodes with different offsets. 9874 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) { 9875 GV = G->getGlobal(); 9876 Offset += G->getOffset(); 9877 return false; 9878 } 9879 9880 // Return the underlying Constant value, and update the Offset. Return false 9881 // for ConstantSDNodes since the same constant pool entry may be represented 9882 // by multiple nodes with different offsets. 9883 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) { 9884 CV = C->isMachineConstantPoolEntry() ? (const void *)C->getMachineCPVal() 9885 : (const void *)C->getConstVal(); 9886 Offset += C->getOffset(); 9887 return false; 9888 } 9889 // If it's any of the following then it can't alias with anything but itself. 9890 return isa<FrameIndexSDNode>(Base); 9891} 9892 9893/// isAlias - Return true if there is any possibility that the two addresses 9894/// overlap. 9895bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 9896 const Value *SrcValue1, int SrcValueOffset1, 9897 unsigned SrcValueAlign1, 9898 const MDNode *TBAAInfo1, 9899 SDValue Ptr2, int64_t Size2, 9900 const Value *SrcValue2, int SrcValueOffset2, 9901 unsigned SrcValueAlign2, 9902 const MDNode *TBAAInfo2) const { 9903 // If they are the same then they must be aliases. 9904 if (Ptr1 == Ptr2) return true; 9905 9906 // Gather base node and offset information. 9907 SDValue Base1, Base2; 9908 int64_t Offset1, Offset2; 9909 const GlobalValue *GV1, *GV2; 9910 const void *CV1, *CV2; 9911 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1); 9912 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2); 9913 9914 // If they have a same base address then check to see if they overlap. 9915 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2))) 9916 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 9917 9918 // It is possible for different frame indices to alias each other, mostly 9919 // when tail call optimization reuses return address slots for arguments. 9920 // To catch this case, look up the actual index of frame indices to compute 9921 // the real alias relationship. 9922 if (isFrameIndex1 && isFrameIndex2) { 9923 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9924 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex()); 9925 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex()); 9926 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 9927 } 9928 9929 // Otherwise, if we know what the bases are, and they aren't identical, then 9930 // we know they cannot alias. 9931 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2)) 9932 return false; 9933 9934 // If we know required SrcValue1 and SrcValue2 have relatively large alignment 9935 // compared to the size and offset of the access, we may be able to prove they 9936 // do not alias. This check is conservative for now to catch cases created by 9937 // splitting vector types. 9938 if ((SrcValueAlign1 == SrcValueAlign2) && 9939 (SrcValueOffset1 != SrcValueOffset2) && 9940 (Size1 == Size2) && (SrcValueAlign1 > Size1)) { 9941 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1; 9942 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1; 9943 9944 // There is no overlap between these relatively aligned accesses of similar 9945 // size, return no alias. 9946 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1) 9947 return false; 9948 } 9949 9950 if (CombinerGlobalAA) { 9951 // Use alias analysis information. 9952 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 9953 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 9954 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 9955 AliasAnalysis::AliasResult AAResult = 9956 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1), 9957 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2)); 9958 if (AAResult == AliasAnalysis::NoAlias) 9959 return false; 9960 } 9961 9962 // Otherwise we have to assume they alias. 9963 return true; 9964} 9965 9966bool DAGCombiner::isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1) { 9967 SDValue Ptr0, Ptr1; 9968 int64_t Size0, Size1; 9969 const Value *SrcValue0, *SrcValue1; 9970 int SrcValueOffset0, SrcValueOffset1; 9971 unsigned SrcValueAlign0, SrcValueAlign1; 9972 const MDNode *SrcTBAAInfo0, *SrcTBAAInfo1; 9973 FindAliasInfo(Op0, Ptr0, Size0, SrcValue0, SrcValueOffset0, 9974 SrcValueAlign0, SrcTBAAInfo0); 9975 FindAliasInfo(Op1, Ptr1, Size1, SrcValue1, SrcValueOffset1, 9976 SrcValueAlign1, SrcTBAAInfo1); 9977 return isAlias(Ptr0, Size0, SrcValue0, SrcValueOffset0, 9978 SrcValueAlign0, SrcTBAAInfo0, 9979 Ptr1, Size1, SrcValue1, SrcValueOffset1, 9980 SrcValueAlign1, SrcTBAAInfo1); 9981} 9982 9983/// FindAliasInfo - Extracts the relevant alias information from the memory 9984/// node. Returns true if the operand was a load. 9985bool DAGCombiner::FindAliasInfo(SDNode *N, 9986 SDValue &Ptr, int64_t &Size, 9987 const Value *&SrcValue, 9988 int &SrcValueOffset, 9989 unsigned &SrcValueAlign, 9990 const MDNode *&TBAAInfo) const { 9991 LSBaseSDNode *LS = cast<LSBaseSDNode>(N); 9992 9993 Ptr = LS->getBasePtr(); 9994 Size = LS->getMemoryVT().getSizeInBits() >> 3; 9995 SrcValue = LS->getSrcValue(); 9996 SrcValueOffset = LS->getSrcValueOffset(); 9997 SrcValueAlign = LS->getOriginalAlignment(); 9998 TBAAInfo = LS->getTBAAInfo(); 9999 return isa<LoadSDNode>(LS); 10000} 10001 10002/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 10003/// looking for aliasing nodes and adding them to the Aliases vector. 10004void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 10005 SmallVector<SDValue, 8> &Aliases) { 10006 SmallVector<SDValue, 8> Chains; // List of chains to visit. 10007 SmallPtrSet<SDNode *, 16> Visited; // Visited node set. 10008 10009 // Get alias information for node. 10010 SDValue Ptr; 10011 int64_t Size; 10012 const Value *SrcValue; 10013 int SrcValueOffset; 10014 unsigned SrcValueAlign; 10015 const MDNode *SrcTBAAInfo; 10016 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset, 10017 SrcValueAlign, SrcTBAAInfo); 10018 10019 // Starting off. 10020 Chains.push_back(OriginalChain); 10021 unsigned Depth = 0; 10022 10023 // Look at each chain and determine if it is an alias. If so, add it to the 10024 // aliases list. If not, then continue up the chain looking for the next 10025 // candidate. 10026 while (!Chains.empty()) { 10027 SDValue Chain = Chains.back(); 10028 Chains.pop_back(); 10029 10030 // For TokenFactor nodes, look at each operand and only continue up the 10031 // chain until we find two aliases. If we've seen two aliases, assume we'll 10032 // find more and revert to original chain since the xform is unlikely to be 10033 // profitable. 10034 // 10035 // FIXME: The depth check could be made to return the last non-aliasing 10036 // chain we found before we hit a tokenfactor rather than the original 10037 // chain. 10038 if (Depth > 6 || Aliases.size() == 2) { 10039 Aliases.clear(); 10040 Aliases.push_back(OriginalChain); 10041 break; 10042 } 10043 10044 // Don't bother if we've been before. 10045 if (!Visited.insert(Chain.getNode())) 10046 continue; 10047 10048 switch (Chain.getOpcode()) { 10049 case ISD::EntryToken: 10050 // Entry token is ideal chain operand, but handled in FindBetterChain. 10051 break; 10052 10053 case ISD::LOAD: 10054 case ISD::STORE: { 10055 // Get alias information for Chain. 10056 SDValue OpPtr; 10057 int64_t OpSize; 10058 const Value *OpSrcValue; 10059 int OpSrcValueOffset; 10060 unsigned OpSrcValueAlign; 10061 const MDNode *OpSrcTBAAInfo; 10062 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 10063 OpSrcValue, OpSrcValueOffset, 10064 OpSrcValueAlign, 10065 OpSrcTBAAInfo); 10066 10067 // If chain is alias then stop here. 10068 if (!(IsLoad && IsOpLoad) && 10069 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign, 10070 SrcTBAAInfo, 10071 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset, 10072 OpSrcValueAlign, OpSrcTBAAInfo)) { 10073 Aliases.push_back(Chain); 10074 } else { 10075 // Look further up the chain. 10076 Chains.push_back(Chain.getOperand(0)); 10077 ++Depth; 10078 } 10079 break; 10080 } 10081 10082 case ISD::TokenFactor: 10083 // We have to check each of the operands of the token factor for "small" 10084 // token factors, so we queue them up. Adding the operands to the queue 10085 // (stack) in reverse order maintains the original order and increases the 10086 // likelihood that getNode will find a matching token factor (CSE.) 10087 if (Chain.getNumOperands() > 16) { 10088 Aliases.push_back(Chain); 10089 break; 10090 } 10091 for (unsigned n = Chain.getNumOperands(); n;) 10092 Chains.push_back(Chain.getOperand(--n)); 10093 ++Depth; 10094 break; 10095 10096 default: 10097 // For all other instructions we will just have to take what we can get. 10098 Aliases.push_back(Chain); 10099 break; 10100 } 10101 } 10102} 10103 10104/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 10105/// for a better chain (aliasing node.) 10106SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 10107 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 10108 10109 // Accumulate all the aliases to this node. 10110 GatherAllAliases(N, OldChain, Aliases); 10111 10112 // If no operands then chain to entry token. 10113 if (Aliases.size() == 0) 10114 return DAG.getEntryNode(); 10115 10116 // If a single operand then chain to it. We don't need to revisit it. 10117 if (Aliases.size() == 1) 10118 return Aliases[0]; 10119 10120 // Construct a custom tailored token factor. 10121 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 10122 &Aliases[0], Aliases.size()); 10123} 10124 10125// SelectionDAG::Combine - This is the entry point for the file. 10126// 10127void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 10128 CodeGenOpt::Level OptLevel) { 10129 /// run - This is the main entry point to this class. 10130 /// 10131 DAGCombiner(*this, AA, OptLevel).Run(Level); 10132} 10133